board: tegra30: switch to updated pre-dm i2c write

Configure PMIC voltages for early stages using updated
early i2c write.

Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>

12 files changed, 200 insertions, 46 deletions

diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig
index 5619d1c..85b8ce2 100644
--- a/arch/arm/mach-tegra/tegra30/Kconfig
+++ b/arch/arm/mach-tegra/tegra30/Kconfig
@@ -1,11 +1,5 @@
 if TEGRA30
 
-config TEGRA_VDD_CORE_TPS62361B_SET3
-	bool
-
-config TEGRA_VDD_CORE_TPS62366A_SET1
-	bool
-
 choice
 	prompt "Tegra30 board select"
 	optional
@@ -17,12 +11,10 @@ config TARGET_APALIS_T30
 config TARGET_BEAVER
 	bool "NVIDIA Tegra30 Beaver evaluation board"
 	select BOARD_LATE_INIT
-	select TEGRA_VDD_CORE_TPS62366A_SET1
 
 config TARGET_CARDHU
 	bool "NVIDIA Tegra30 Cardhu evaluation board"
 	select BOARD_LATE_INIT
-	select TEGRA_VDD_CORE_TPS62361B_SET3
 
 config TARGET_COLIBRI_T30
 	bool "Toradex Colibri T30 board"
diff --git a/arch/arm/mach-tegra/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c
index 6ac45af..60bbf13 100644
--- a/arch/arm/mach-tegra/tegra30/cpu.c
+++ b/arch/arm/mach-tegra/tegra30/cpu.c
@@ -15,20 +15,6 @@
 #include <linux/delay.h>
 #include "../cpu.h"
 
-#define TPS62366A_I2C_ADDR		0xC0
-#define TPS62366A_SET1_REG		0x01
-#define TPS62366A_SET1_DATA		(0x4600 | TPS62366A_SET1_REG)
-
-#define TPS62361B_I2C_ADDR		0xC0
-#define TPS62361B_SET3_REG		0x03
-#define TPS62361B_SET3_DATA		(0x4600 | TPS62361B_SET3_REG)
-
-#define TPS65911_I2C_ADDR		0x5A
-#define TPS65911_VDDCTRL_OP_REG		0x28
-#define TPS65911_VDDCTRL_SR_REG		0x27
-#define TPS65911_VDDCTRL_OP_DATA	(0x2400 | TPS65911_VDDCTRL_OP_REG)
-#define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
-
 /* In case this function is not defined */
 __weak void pmic_enable_cpu_vdd(void) {}
 
@@ -41,28 +27,6 @@ static void enable_cpu_power_rail(void)
 	reg = readl(&pmc->pmc_cntrl);
 	reg |= CPUPWRREQ_OE;
 	writel(reg, &pmc->pmc_cntrl);
-
-	/* Set VDD_CORE to 1.200V. */
-#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
-	tegra_i2c_ll_write(TPS62366A_I2C_ADDR,
-			   TPS62366A_SET1_DATA);
-#endif
-#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
-	tegra_i2c_ll_write(TPS62361B_I2C_ADDR,
-			   TPS62361B_SET3_DATA);
-#endif
-	udelay(1000);
-
-	/*
-	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
-	 * First set VDD to 1.0125V, then enable the VDD regulator.
-	 */
-	tegra_i2c_ll_write(TPS65911_I2C_ADDR,
-			   TPS65911_VDDCTRL_OP_DATA);
-	udelay(1000);
-	tegra_i2c_ll_write(TPS65911_I2C_ADDR,
-			   TPS65911_VDDCTRL_SR_DATA);
-	udelay(10 * 1000);
 }
 
 /**
diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile
index 46df14d..d6890e5 100644
--- a/board/avionic-design/tec-ng/Makefile
+++ b/board/avionic-design/tec-ng/Makefile
@@ -3,4 +3,6 @@
 # (C) Copyright 2013
 # Avionic Design GmbH <www.avionic-design.de>
 
-obj-y	:= ../common/tamonten-ng.o
+obj-$(CONFIG_SPL_BUILD) += tec-ng-spl.o
+
+obj-y	+= ../common/tamonten-ng.o
diff --git a/board/avionic-design/tec-ng/tec-ng-spl.c b/board/avionic-design/tec-ng/tec-ng-spl.c
new file mode 100644
index 0000000..6e54464
--- /dev/null
+++ b/board/avionic-design/tec-ng/tec-ng-spl.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2021
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+/* I2C addr is in 8 bit */
+#define TPS65911_I2C_ADDR		0x5A
+#define TPS65911_VDDCTRL_OP_REG		0x28
+#define TPS65911_VDDCTRL_SR_REG		0x27
+#define TPS65911_VDDCTRL_OP_DATA	(0x2400 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
+
+void pmic_enable_cpu_vdd(void)
+{
+	/*
+	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+	 * First set VDD to 1.0125V, then enable the VDD regulator.
+	 */
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR,
+			   TPS65911_VDDCTRL_OP_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR,
+			   TPS65911_VDDCTRL_SR_DATA);
+	udelay(10 * 1000);
+}
diff --git a/board/nvidia/beaver/Makefile b/board/nvidia/beaver/Makefile
index 80cff3e..5e9e708 100644
--- a/board/nvidia/beaver/Makefile
+++ b/board/nvidia/beaver/Makefile
@@ -2,4 +2,6 @@
 #
 # Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
 
+obj-$(CONFIG_SPL_BUILD) += beaver-spl.o
+
 obj-y	= ../cardhu/cardhu.o
diff --git a/board/nvidia/beaver/beaver-spl.c b/board/nvidia/beaver/beaver-spl.c
new file mode 100644
index 0000000..b5d0c14
--- /dev/null
+++ b/board/nvidia/beaver/beaver-spl.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2021
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+/* I2C addr is in 8 bit */
+#define TPS65911_I2C_ADDR		0x5A
+#define TPS65911_VDDCTRL_OP_REG		0x28
+#define TPS65911_VDDCTRL_SR_REG		0x27
+#define TPS65911_VDDCTRL_OP_DATA	(0x2400 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
+
+#define TPS62366A_I2C_ADDR		0xC0
+#define TPS62366A_SET1_REG		0x01
+#define TPS62366A_SET1_DATA		(0x4600 | TPS62366A_SET1_REG)
+
+void pmic_enable_cpu_vdd(void)
+{
+	/* Set VDD_CORE to 1.200V. */
+	tegra_i2c_ll_write(TPS62366A_I2C_ADDR,
+			   TPS62366A_SET1_DATA);
+
+	udelay(1000);
+
+	/*
+	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+	 * First set VDD to 1.0125V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR,
+			   TPS65911_VDDCTRL_OP_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR,
+			   TPS65911_VDDCTRL_SR_DATA);
+	udelay(10 * 1000);
+}
diff --git a/board/nvidia/cardhu/Makefile b/board/nvidia/cardhu/Makefile
index 9597105..6f480cd 100644
--- a/board/nvidia/cardhu/Makefile
+++ b/board/nvidia/cardhu/Makefile
@@ -3,4 +3,6 @@
 #  (C) Copyright 2010-2012
 #  NVIDIA Corporation <www.nvidia.com>
 
-obj-y	:= cardhu.o
+obj-$(CONFIG_SPL_BUILD) += cardhu-spl.o
+
+obj-y	+= cardhu.o
diff --git a/board/nvidia/cardhu/cardhu-spl.c b/board/nvidia/cardhu/cardhu-spl.c
new file mode 100644
index 0000000..de2fa30
--- /dev/null
+++ b/board/nvidia/cardhu/cardhu-spl.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2021
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+/* I2C addr is in 8 bit */
+#define TPS65911_I2C_ADDR		0x5A
+#define TPS65911_VDDCTRL_OP_REG		0x28
+#define TPS65911_VDDCTRL_SR_REG		0x27
+#define TPS65911_VDDCTRL_OP_DATA	(0x2400 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
+
+#define TPS62361B_I2C_ADDR		0xC0
+#define TPS62361B_SET3_REG		0x03
+#define TPS62361B_SET3_DATA		(0x4600 | TPS62361B_SET3_REG)
+
+void pmic_enable_cpu_vdd(void)
+{
+	/* Set VDD_CORE to 1.200V. */
+	tegra_i2c_ll_write(TPS62361B_I2C_ADDR,
+			   TPS62361B_SET3_DATA);
+
+	udelay(1000);
+
+	/*
+	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+	 * First set VDD to 1.0125V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR,
+			   TPS65911_VDDCTRL_OP_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR,
+			   TPS65911_VDDCTRL_SR_DATA);
+	udelay(10 * 1000);
+}
diff --git a/board/toradex/apalis_t30/Makefile b/board/toradex/apalis_t30/Makefile
index 0ea3d8f..eed6070 100644
--- a/board/toradex/apalis_t30/Makefile
+++ b/board/toradex/apalis_t30/Makefile
@@ -1,4 +1,6 @@
 # Copyright (c) 2014 Marcel Ziswiler
 # SPDX-License-Identifier:      GPL-2.0+
 
+obj-$(CONFIG_SPL_BUILD) += apalis_t30-spl.o
+
 obj-y	+= apalis_t30.o
diff --git a/board/toradex/apalis_t30/apalis_t30-spl.c b/board/toradex/apalis_t30/apalis_t30-spl.c
new file mode 100644
index 0000000..6e54464
--- /dev/null
+++ b/board/toradex/apalis_t30/apalis_t30-spl.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2021
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+/* I2C addr is in 8 bit */
+#define TPS65911_I2C_ADDR		0x5A
+#define TPS65911_VDDCTRL_OP_REG		0x28
+#define TPS65911_VDDCTRL_SR_REG		0x27
+#define TPS65911_VDDCTRL_OP_DATA	(0x2400 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
+
+void pmic_enable_cpu_vdd(void)
+{
+	/*
+	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+	 * First set VDD to 1.0125V, then enable the VDD regulator.
+	 */
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR,
+			   TPS65911_VDDCTRL_OP_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR,
+			   TPS65911_VDDCTRL_SR_DATA);
+	udelay(10 * 1000);
+}
diff --git a/board/toradex/colibri_t30/Makefile b/board/toradex/colibri_t30/Makefile
index 4242902..8f33323 100644
--- a/board/toradex/colibri_t30/Makefile
+++ b/board/toradex/colibri_t30/Makefile
@@ -1,4 +1,6 @@
 # Copyright (c) 2013-2014 Stefan Agner
 # SPDX-License-Identifier:      GPL-2.0+
 
+obj-$(CONFIG_SPL_BUILD) += colibri_t30-spl.o
+
 obj-y	+= colibri_t30.o
diff --git a/board/toradex/colibri_t30/colibri_t30-spl.c b/board/toradex/colibri_t30/colibri_t30-spl.c
new file mode 100644
index 0000000..6e54464
--- /dev/null
+++ b/board/toradex/colibri_t30/colibri_t30-spl.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2021
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+/* I2C addr is in 8 bit */
+#define TPS65911_I2C_ADDR		0x5A
+#define TPS65911_VDDCTRL_OP_REG		0x28
+#define TPS65911_VDDCTRL_SR_REG		0x27
+#define TPS65911_VDDCTRL_OP_DATA	(0x2400 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
+
+void pmic_enable_cpu_vdd(void)
+{
+	/*
+	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+	 * First set VDD to 1.0125V, then enable the VDD regulator.
+	 */
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR,
+			   TPS65911_VDDCTRL_OP_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR,
+			   TPS65911_VDDCTRL_SR_DATA);
+	udelay(10 * 1000);
+}