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author | Tom Rini <trini@konsulko.com> | 2021-02-19 21:06:16 -0500 |
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committer | Tom Rini <trini@konsulko.com> | 2021-02-19 21:06:16 -0500 |
commit | ea966d24ef3a9f7f32712a518a07374f9ae43905 (patch) | |
tree | 3c53ffa01c21b95dde2013a8ea04e93f496486d3 | |
parent | a1a652e8016426e2d67148cab225cd5ec45189fb (diff) | |
parent | e036a1d227112565cdf32b5558ac6ccaf5d1633f (diff) | |
download | u-boot-ea966d24ef3a9f7f32712a518a07374f9ae43905.zip u-boot-ea966d24ef3a9f7f32712a518a07374f9ae43905.tar.gz u-boot-ea966d24ef3a9f7f32712a518a07374f9ae43905.tar.bz2 |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiWIP/19Feb2021
- H616 clock fix to enable video PLL
- sunxi-common.h cleanups
- support for UART1 as the console on sun8i
- removing wrong linux,stdout-path from DTs
-rw-r--r-- | README | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/gpio.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-sunxi/board.c | 5 | ||||
-rw-r--r-- | arch/arm/mach-sunxi/clock_sun50i_h6.c | 5 | ||||
-rw-r--r-- | common/fdt_support.c | 9 | ||||
-rw-r--r-- | include/configs/sunxi-common.h | 33 | ||||
-rw-r--r-- | scripts/config_whitelist.txt | 1 |
7 files changed, 12 insertions, 43 deletions
@@ -575,7 +575,6 @@ The following options need to be configured: * The bootm command automatically updates the fdt OF_TBCLK - The timebase frequency. - OF_STDOUT_PATH - The path to the console device boards with QUICC Engines require OF_QE to set UCC MAC addresses diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index de77bf6..2969a53 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -190,6 +190,7 @@ enum sunxi_gpio_number { #define SUN5I_GPG_SDC1 2 #define SUN6I_GPG_SDC1 2 #define SUN8I_GPG_SDC1 2 +#define SUN8I_GPG_UART1 2 #define SUN6I_GPG_TWI3 2 #define SUN5I_GPG_UART1 4 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index ae6bc65..d25081c 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -144,6 +144,11 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \ + !defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1); + sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1); + sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP); #else #error Unsupported console port number. Please fix pin mux settings in board.c #endif diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 06d84eb..492fc4a 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -9,6 +9,11 @@ void clock_init_safe(void) { struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* this seems to enable PLLs on H616 */ + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) + setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10); + clock_set_pll1(408000000); writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg); diff --git a/common/fdt_support.c b/common/fdt_support.c index 1a1b408..08d540b 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -127,14 +127,7 @@ int fdt_find_or_add_subnode(void *fdt, int parentoffset, const char *name) return offset; } -/* rename to CONFIG_OF_STDOUT_PATH ? */ -#if defined(OF_STDOUT_PATH) -static int fdt_fixup_stdout(void *fdt, int chosenoff) -{ - return fdt_setprop(fdt, chosenoff, "linux,stdout-path", - OF_STDOUT_PATH, strlen(OF_STDOUT_PATH) + 1); -} -#elif defined(CONFIG_OF_STDOUT_VIA_ALIAS) && defined(CONFIG_CONS_INDEX) +#if defined(CONFIG_OF_STDOUT_VIA_ALIAS) && defined(CONFIG_CONS_INDEX) static int fdt_fixup_stdout(void *fdt, int chosenoff) { int err; diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 000f386..ded5aea 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -134,11 +134,6 @@ #define CONFIG_BOARD_SIZE_LIMIT 0x7e000 #endif -#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 -/* If we have two devices (most likely eMMC + MMC), favour the eMMC */ -#else -/* Otherwise, use the only device we have */ -#endif #define CONFIG_SYS_MMC_MAX_DEVICE 4 #endif @@ -199,10 +194,6 @@ /* I2C */ -#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ - defined CONFIG_SY8106A_POWER -#endif - #if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \ defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \ defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE @@ -232,30 +223,6 @@ extern int soft_i2c_gpio_scl; #define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */ #endif -/* PMU */ -#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ - defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER || \ - defined CONFIG_SY8106A_POWER -#endif - -#ifdef CONFIG_REQUIRE_SERIAL_CONSOLE -#if CONFIG_CONS_INDEX == 1 -#ifdef CONFIG_MACH_SUN9I -#define OF_STDOUT_PATH "/soc/serial@07000000:115200" -#else -#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28000:115200" -#endif -#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) -#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200" -#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) -#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200" -#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) -#define OF_STDOUT_PATH "/soc@01c00000/serial@01f02800:115200" -#else -#error Unsupported console port nr. Please fix stdout-path in sunxi-common.h. -#endif -#endif /* ifdef CONFIG_REQUIRE_SERIAL_CONSOLE */ - #ifdef CONFIG_VIDEO_SUNXI /* * The amount of RAM to keep free at the top of RAM when relocating u-boot, diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index c09d303..cd59acd 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1172,7 +1172,6 @@ CONFIG_NUM_PAMU CONFIG_ODROID_REV_AIN CONFIG_OFF_PADCONF CONFIG_OF_ -CONFIG_OF_STDOUT_PATH CONFIG_OMAP_EHCI_PHY1_RESET_GPIO CONFIG_OMAP_EHCI_PHY2_RESET_GPIO CONFIG_OMAP_EHCI_PHY3_RESET_GPIO |