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| author | Bin Meng <bmeng@tinylab.org> | 2023-04-13 14:20:08 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-04-20 20:45:08 +0800 |
| commit | 9a6569a043d336138fca857bc3140fab33a11afc (patch) | |
| tree | 515b536e978f00b2d8b89b3ab9dd92e23fe77de1 | |
| parent | 3f37baae83ed7f4879b06cf41214a647228fc72b (diff) | |
| download | u-boot-9a6569a043d336138fca857bc3140fab33a11afc.zip u-boot-9a6569a043d336138fca857bc3140fab33a11afc.tar.gz u-boot-9a6569a043d336138fca857bc3140fab33a11afc.tar.bz2 | |
riscv: Update alignment for some sections in linker scripts
Some sections in the linker scripts are aligned to 4 bytes, which
may cause misaligned exception on some platforms, e.g.: clearing
the bss section on 64-bit hardware if __bss_start does not start
from a naturally 8 bytes aligned address.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| -rw-r--r-- | arch/riscv/cpu/u-boot-spl.lds | 2 | ||||
| -rw-r--r-- | arch/riscv/cpu/u-boot.lds | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds index c3b4907..d1113a5 100644 --- a/arch/riscv/cpu/u-boot-spl.lds +++ b/arch/riscv/cpu/u-boot-spl.lds @@ -44,7 +44,7 @@ SECTIONS __binman_sym_end = .; } > .spl_mem - . = ALIGN(4); + . = ALIGN(8); _end = .; _image_binary_end = .; diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds index 1c937ae..15b5cbc 100644 --- a/arch/riscv/cpu/u-boot.lds +++ b/arch/riscv/cpu/u-boot.lds @@ -57,7 +57,7 @@ SECTIONS __efi_runtime_rel_stop = .; } - . = ALIGN(4); + . = ALIGN(8); /DISCARD/ : { *(.rela.plt*) } .rela.dyn : { @@ -66,7 +66,7 @@ SECTIONS __rel_dyn_end = .; } - . = ALIGN(4); + . = ALIGN(8); .dynsym : { __dyn_sym_start = .; @@ -74,7 +74,7 @@ SECTIONS __dyn_sym_end = .; } - . = ALIGN(4); + . = ALIGN(8); _end = .; |