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| author | Pali Rohár <pali@kernel.org> | 2022-08-05 22:09:39 +0200 |
|---|---|---|
| committer | Marek Behún <kabel@kernel.org> | 2022-09-16 17:39:44 +0200 |
| commit | 04e9cd7a98e7620a694e729c45e2d4aeb9317f6e (patch) | |
| tree | f993f18eeb056acf4b4968fd3bc1457d1d47b09d | |
| parent | 1e1d12adbc7bad37ea42351835ba864d5089f76c (diff) | |
| download | u-boot-04e9cd7a98e7620a694e729c45e2d4aeb9317f6e.zip u-boot-04e9cd7a98e7620a694e729c45e2d4aeb9317f6e.tar.gz u-boot-04e9cd7a98e7620a694e729c45e2d4aeb9317f6e.tar.bz2 | |
mmc: fsl_esdhc_spl: Add support for loading proper U-Boot from unaligned location
This allows to concatenate SPL and proper U-Boot without extra alignment.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Marek Behún <kabel@kernel.org>
| -rw-r--r-- | drivers/mmc/fsl_esdhc_spl.c | 35 |
1 files changed, 26 insertions, 9 deletions
diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index 760f13d..dd6d5fa 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -58,10 +58,10 @@ void __noreturn mmc_boot(void) { __attribute__((noreturn)) void (*uboot)(void); uint blk_start, blk_cnt, err; -#ifndef CONFIG_FSL_CORENET uchar *tmp_buf; u32 blklen; u32 blk_off; +#ifndef CONFIG_FSL_CORENET uchar val; #ifndef CONFIG_SPL_FSL_PBL u32 val32; @@ -83,9 +83,6 @@ void __noreturn mmc_boot(void) hang(); } -#ifdef CONFIG_FSL_CORENET - offset = CONFIG_SYS_MMC_U_BOOT_OFFS; -#else blklen = mmc->read_bl_len; if (blklen < 512) blklen = 512; @@ -95,6 +92,9 @@ void __noreturn mmc_boot(void) hang(); } +#ifdef CONFIG_FSL_CORENET + offset = CONFIG_SYS_MMC_U_BOOT_OFFS; +#else sector = 0; again: memset(tmp_buf, 0, blklen); @@ -155,17 +155,34 @@ again: * Load U-Boot image from mmc into RAM */ code_len = CONFIG_SYS_MMC_U_BOOT_SIZE; - blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; - blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len; + blk_start = offset / mmc->read_bl_len; + blk_off = offset % mmc->read_bl_len; + blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len + 1; + if (blk_off) { + err = mmc->block_dev.block_read(&mmc->block_dev, + blk_start, 1, tmp_buf); + if (err != 1) { + puts("spl: mmc read failed!!\n"); + hang(); + } + blk_start++; + } err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, - (uchar *)CONFIG_SYS_MMC_U_BOOT_DST); + (uchar *)CONFIG_SYS_MMC_U_BOOT_DST + + (blk_off ? (mmc->read_bl_len - blk_off) : 0)); if (err != blk_cnt) { puts("spl: mmc read failed!!\n"); -#ifndef CONFIG_FSL_CORENET free(tmp_buf); -#endif hang(); } + /* + * SDHC DMA may erase bytes at dst + bl_len - blk_off - 8 + * due to unaligned access. So copy leading bytes from tmp_buf + * after SDHC DMA transfer. + */ + if (blk_off) + memcpy((uchar *)CONFIG_SYS_MMC_U_BOOT_DST, + tmp_buf + blk_off, mmc->read_bl_len - blk_off); /* * Clean d-cache and invalidate i-cache, to |