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| author | Lukasz Wiecaszek <lukasz.wiecaszek@googlemail.com> | 2024-03-10 11:29:58 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-03-19 18:40:47 -0400 |
| commit | 95167db37c4b669ae47be885cd1cc1832e754fff (patch) | |
| tree | 9d16b0c873e0f1a91d62fff18f5efb60c19fd0d5 | |
| parent | c6a13f3d6f074a20680765309280994288c89ad1 (diff) | |
| download | u-boot-95167db37c4b669ae47be885cd1cc1832e754fff.zip u-boot-95167db37c4b669ae47be885cd1cc1832e754fff.tar.gz u-boot-95167db37c4b669ae47be885cd1cc1832e754fff.tar.bz2 | |
arm: Check FEAT_CCIDX when parsing ccsidr_el1 register
Current Cache Size ID Register (ccsidr_el1) has two "flavors"
depending on whether FEAT_CCIDX is implemented or not.
When FEAT_CCIDX is implemented Associativity parameter
is coded on bits [23:3] and NumSets parameter on bits [55:32].
When FEAT_CCIDX is not implemented then Associativity parameter
is coded on bits [12:3] and NumSets parameter on bits [27:13].
Current U-Boot code does not check whether FEAT_CCIDX is implemented
and always parses ccsidr_el1 as if FEAT_CCIDX was not implemented.
This is of course wrong on systems where FEAT_CCIDX is implemented.
This patch fixes that problems and tests whether FEAT_CCIDX
is implemented or not and accordingly parses the ccsidr_el1 register.
Signed-off-by: Lukasz Wiecaszek <lukasz.wiecaszek@gmail.com>
| -rw-r--r-- | arch/arm/cpu/armv8/cache.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 3fe935c..c9e4685 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -20,6 +20,7 @@ * * x0: cache level * x1: 0 clean & invalidate, 1 invalidate only + * x16: FEAT_CCIDX * x2~x9: clobbered */ .pushsection .text.__asm_dcache_level, "ax" @@ -29,8 +30,14 @@ ENTRY(__asm_dcache_level) isb /* sync change of cssidr_el1 */ mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */ + cbz x16, 3f /* check for FEAT_CCIDX */ + ubfx x3, x6, #3, #21 /* x3 <- number of cache ways - 1 */ + ubfx x4, x6, #32, #24 /* x4 <- number of cache sets - 1 */ + b 4f +3: ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */ ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */ +4: add x2, x2, #4 /* x2 <- log2(cache line size) */ clz w5, w3 /* bit position of #ways */ /* x12 <- cache level << 1 */ @@ -74,6 +81,8 @@ ENTRY(__asm_dcache_all) ubfx x11, x10, #24, #3 /* x11 <- loc */ cbz x11, finished /* if loc is 0, exit */ mov x15, lr + mrs x16, s3_0_c0_c7_2 /* read value of id_aa64mmfr2_el1*/ + ubfx x16, x16, #20, #4 /* save FEAT_CCIDX identifier in x16 */ mov x0, #0 /* start flush at cache level 0 */ /* x0 <- cache level */ /* x10 <- clidr_el1 */ |