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| author | Patrick Delaunay <patrick.delaunay@foss.st.com> | 2022-09-21 09:37:13 +0200 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@foss.st.com> | 2022-09-23 14:35:45 +0200 |
| commit | 9f7c58dc0deacd6c453ac628953741f1a6a68126 (patch) | |
| tree | 893e659f70e6061811312a32a27536010fa65d1d | |
| parent | 86d5a06ae3b826bf7b4627e926afd5378d88c574 (diff) | |
| download | u-boot-9f7c58dc0deacd6c453ac628953741f1a6a68126.zip u-boot-9f7c58dc0deacd6c453ac628953741f1a6a68126.tar.gz u-boot-9f7c58dc0deacd6c453ac628953741f1a6a68126.tar.bz2 | |
ARM: dts: stm32mp15: update DDR node
Remove the unnecessary nodes for TFABOOT and keep the mandatory part
in SOC dtsi, only the DDRCTRL and DDRPHY addresses.
This patch allows to manage the DDR configuration setting in U-Boot
device tree only if it is needed, when CONFIG_SPL is defined.
With TFABOOT, the DDR configuration is done in TF-A BL2 and the DDR size
is dynamically computed in U-Boot since commit d72e7bbe7c28 ("ram:
stm32mp1: compute DDR size from DDRCTL registers").
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| -rw-r--r-- | arch/arm/dts/stm32mp15-ddr.dtsi | 16 | ||||
| -rw-r--r-- | arch/arm/dts/stm32mp15-u-boot.dtsi | 14 | ||||
| -rw-r--r-- | arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi | 1 |
4 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi index 0aac913..d02f79d 100644 --- a/arch/arm/dts/stm32mp15-ddr.dtsi +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -4,7 +4,22 @@ */ #include <linux/stringify.h> +#ifdef CONFIG_SPL &ddr { + clocks = <&rcc AXIDCG>, + <&rcc DDRC1>, + <&rcc DDRC2>, + <&rcc DDRPHYC>, + <&rcc DDRCAPB>, + <&rcc DDRPHYCAPB>; + + clock-names = "axidcg", + "ddrc1", + "ddrc2", + "ddrphyc", + "ddrcapb", + "ddrphycapb"; + config-DDR_MEM_COMPATIBLE { u-boot,dm-pre-reloc; @@ -119,6 +134,7 @@ status = "okay"; }; }; +#endif #undef DDR_MEM_COMPATIBLE #undef DDR_MEM_NAME diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index d9d0474..d5c87d2 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -53,20 +53,6 @@ reg = <0x5a003000 0x550 0x5a004000 0x234>; - clocks = <&rcc AXIDCG>, - <&rcc DDRC1>, - <&rcc DDRC2>, - <&rcc DDRPHYC>, - <&rcc DDRCAPB>, - <&rcc DDRPHYCAPB>; - - clock-names = "axidcg", - "ddrc1", - "ddrc2", - "ddrphyc", - "ddrcapb", - "ddrphycapb"; - status = "okay"; }; }; diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi index 2db045e..1209dfe 100644 --- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi @@ -5,7 +5,6 @@ #include <dt-bindings/clock/stm32mp1-clksrc.h> #include "stm32mp15-scmi-u-boot.dtsi" -#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" / { aliases { diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi index 54662f7..c265745 100644 --- a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi @@ -5,7 +5,6 @@ #include <dt-bindings/clock/stm32mp1-clksrc.h> #include "stm32mp15-scmi-u-boot.dtsi" -#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" / { aliases { |