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| author | Saeed Nowshadi <saeed.nowshadi@xilinx.com> | 2021-03-22 11:58:38 -0700 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2021-05-19 09:44:50 +0200 |
| commit | 65a572b1d0faeffd6fa467c1115c13a8831316e3 (patch) | |
| tree | f219f4f148d2d68b613ec28e9c9e63857aca581e | |
| parent | a34a12fabc2558535643df6c98a73d52d25001fd (diff) | |
| download | u-boot-65a572b1d0faeffd6fa467c1115c13a8831316e3.zip u-boot-65a572b1d0faeffd6fa467c1115c13a8831316e3.tar.gz u-boot-65a572b1d0faeffd6fa467c1115c13a8831316e3.tar.bz2 | |
arm64: zynqmp: Add 'silabs,skip-recall' to DDR DIMM si570 clk node
The 'silabs,skip-recall' property prevents interruption in operation of
the clock while the driver is being probed. Without this property, the
DDR DIMM clk can cause a failure during Versal's boot.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
| -rw-r--r-- | arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 135c83f..e5d75e5 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019 - 2020, Xilinx, Inc. + * (C) Copyright 2019 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -505,6 +505,7 @@ factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; + silabs,skip-recall; }; }; i2c@4 { /* LPDDR4_SI570_CLK2 */ |