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| author | Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> | 2024-03-06 16:54:41 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-03-19 18:40:46 -0400 |
| commit | c6a13f3d6f074a20680765309280994288c89ad1 (patch) | |
| tree | 8c9e0063418d0b85ff5678db6415a8526fdc7b82 | |
| parent | db5c91b69a1a36a6e772524e1dd7e011d7ad0066 (diff) | |
| download | u-boot-c6a13f3d6f074a20680765309280994288c89ad1.zip u-boot-c6a13f3d6f074a20680765309280994288c89ad1.tar.gz u-boot-c6a13f3d6f074a20680765309280994288c89ad1.tar.bz2 | |
arm64: gic: Add power up sequence for GIC-600
Arm's GIC-600 features a Power Register (GICR_PWRR),
which needs to be programmed to enable redistributor
operation. Power on the redistributor and wait until
the power on state is reflected by checking the bit
GICR_PWRR.RDPD == 0. While running U-Boot in EL3
without enabling this register, GICR_WAKER.ChildrenAsleep
bit is not getting cleared and loops infinitely.
This register(GICR_PWRR) must be programmed to mark the frame
as powered on, before accessing other registers in the frame.
Rest of initialization sequence remains the same.
ARM GIC-600 IP complies with ARM GICv3 architecture.
Enable this config if GIC-600 IP present.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
| -rw-r--r-- | arch/arm/Kconfig | 9 | ||||
| -rw-r--r-- | arch/arm/include/asm/gic.h | 1 | ||||
| -rw-r--r-- | arch/arm/lib/gic_64.S | 10 | ||||
| -rw-r--r-- | arch/arm/mach-versal-net/Kconfig | 3 |
4 files changed, 22 insertions, 1 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0d978c0..a0842e1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -124,6 +124,15 @@ config GIC_V3_ITS ARM GICV3 has limitation, once the LPI table is enabled, LPI configuration table can not be re-programmed, unless GICV3 reset. +config GICV3_SUPPORT_GIC600 + bool "ARM GICV3 GIC600 SUPPORT" + help + ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, + implements a power control register in the Redistributor frame.This + register must be programmed to mark the frame as powered on, before + accessing other registers in the frame. Rest of initialization sequence + remains the same. + config STATIC_RELA bool default y if ARM64 diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h index bd3a80c..fb64ba0 100644 --- a/arch/arm/include/asm/gic.h +++ b/arch/arm/include/asm/gic.h @@ -57,6 +57,7 @@ #define GICR_TYPER 0x0008 #define GICR_STATUSR 0x0010 #define GICR_WAKER 0x0014 +#define GICR_PWRR 0x0024 #define GICR_SETLPIR 0x0040 #define GICR_CLRLPIR 0x0048 #define GICR_SEIR 0x0068 diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S index 86cd882..7fa4864 100644 --- a/arch/arm/lib/gic_64.S +++ b/arch/arm/lib/gic_64.S @@ -92,8 +92,16 @@ ENTRY(gic_init_secure_percpu) add x9, x9, #(2 << 16) b 1b +2: +#if defined(CONFIG_GICV3_SUPPORT_GIC600) + mov w10, #0x0 /* Power on redistributor */ + str w10, [x9, GICR_PWRR] +5: ldr w10, [x9, GICR_PWRR] /* Wait until the power on state is reflected */ + tbnz w10, #1, 5b /* If RDPD == 0 then powered on */ +#endif + /* x9: ReDistributor Base Address of Current CPU */ -2: mov w10, #~0x2 + mov w10, #~0x2 ldr w11, [x9, GICR_WAKER] and w11, w11, w10 /* Clear ProcessorSleep */ str w11, [x9, GICR_WAKER] diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig index 1b53399..54fb93a 100644 --- a/arch/arm/mach-versal-net/Kconfig +++ b/arch/arm/mach-versal-net/Kconfig @@ -35,6 +35,9 @@ config SYS_MEM_RSVD_FOR_MMU config GICV3 def_bool y +config GICV3_SUPPORT_GIC600 + def_bool y + config SYS_MALLOC_LEN default 0x2000000 |