Merge tag 'u-boot-rockchip-20230319' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into nextWIP/20Mar2023-next

- Fix for rockchip timer driver;
- Fix for rk3568 and rk3588 boot device and clock driver;
- Fix for rk3568 reset handler;
- Fix for rk3568 sdhci DLL at 52MHz;

96 files changed, 899 insertions, 187 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index d30676a..55b9a5e 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -67,6 +67,7 @@ config ARM
 config M68K
 	bool "M68000 architecture"
 	select HAVE_PRIVATE_LIBGCC
+	select USE_PRIVATE_LIBGCC
 	select NEEDS_MANUAL_RELOC
 	select SYS_BOOT_GET_CMDLINE
 	select SYS_BOOT_GET_KBD
diff --git a/arch/arm/dts/axp803.dtsi b/arch/arm/dts/axp803.dtsi
index 578ef36..a6b4b87 100644
--- a/arch/arm/dts/axp803.dtsi
+++ b/arch/arm/dts/axp803.dtsi
@@ -25,16 +25,6 @@
 		compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio";
 		gpio-controller;
 		#gpio-cells = <2>;
-
-		gpio0_ldo: gpio0-ldo-pin {
-			pins = "GPIO0";
-			function = "ldo";
-		};
-
-		gpio1_ldo: gpio1-ldo-pin {
-			pins = "GPIO1";
-			function = "ldo";
-		};
 	};
 
 	battery_power_supply: battery-power {
diff --git a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
index fe6aba7..7bcbc29 100644
--- a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
+++ b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
@@ -52,7 +52,6 @@
 };
 
 &timer3 {
-	compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
 	clock-frequency = <24000000>;
 	bootph-pre-ram;
 };
diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
index a27a3ad..27735c4 100644
--- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
@@ -11,7 +11,7 @@
 };
 
 &uart0 {
-	bootph-all;
+	u-boot,dm-pre-reloc;
 	clock-frequency = <24000000>;
 	status = "okay";
 };
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index 4e79173..5893325 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -13,6 +13,6 @@
 
 &uart2 {
 	clock-frequency = <24000000>;
-	bootph-all;
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index ed47efa..04bbb01 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -9,16 +9,20 @@
 / {
 	chosen {
 		stdout-path = &uart2;
-		u-boot,spl-boot-order = "same-as-spl", &sdmmc0;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
 	};
 };
 
-&sdmmc0 {
-	status = "okay";
+&sdmmc2 {
+	status = "disabled";
+};
+
+&uart1 {
+	status = "disabled";
 };
 
 &uart2 {
 	clock-frequency = <24000000>;
-	bootph-all;
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts
index a2f2baa..917f5b2 100644
--- a/arch/arm/dts/rk3568-rock-3a.dts
+++ b/arch/arm/dts/rk3568-rock-3a.dts
@@ -1,22 +1,37 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2023 Akash Gajjar <gajjar04akash@gmail.com>
- */
 
 /dts-v1/;
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
 #include "rk3568.dtsi"
 
 / {
 	model = "Radxa ROCK3 Model A";
 	compatible = "radxa,rock3a", "rockchip,rk3568";
 
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
+	};
+
 	chosen: chosen {
 		stdout-path = "serial2:1500000n8";
 	};
 
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
 	gmac1_clkin: external-gmac1-clock {
 		compatible = "fixed-clock";
 		clock-frequency = <125000000>;
@@ -24,13 +39,93 @@
 		#clock-cells = <0>;
 	};
 
+	leds {
+		compatible = "gpio-leds";
+
+		led_user: led-0 {
+			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_BLUE>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_user_en>;
+		};
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable>;
+		post-power-on-delay-ms = <100>;
+		power-off-delay-us = <5000000>;
+		reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
+	};
+
 	vcc12v_dcin: vcc12v-dcin-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc12v_dcin";
 		regulator-always-on;
 		regulator-boot-on;
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
+	};
+
+	pcie30_avdd0v9: pcie30-avdd0v9-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	/* pi6c pcie clock generator */
+	vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pi6c_03";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_enable_h>;
+		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
 	};
 
 	vcc3v3_sys: vcc3v3-sys-regulator {
@@ -91,6 +186,7 @@
 		enable-active-high;
 		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
 		regulator-name = "vcc5v0_usb_otg";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
@@ -164,7 +260,43 @@
 	clock_in_out = "input";
 	phy-handle = <&rgmii_phy1>;
 	phy-mode = "rgmii-id";
+	phy-supply = <&vcc_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_clkinout
+		     &gmac1m1_rgmii_bus>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
 	pinctrl-names = "default";
+	pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm1_cec>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
 	status = "okay";
 };
 
@@ -441,6 +573,13 @@
 };
 
 &i2s1_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&i2s2_2ch {
 	rockchip,trcm-sync-tx-only;
 	status = "okay";
 };
@@ -457,6 +596,27 @@
 	};
 };
 
+&pcie2x1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_h>;
+	reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pcie30phy {
+	phy-supply = <&vcc3v3_pi6c_03>;
+	status = "okay";
+};
+
+&pcie3x2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie30x2m1_pins>;
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
 &pinctrl {
 	cam {
 		vcc_cam_en: vcc_cam_en {
@@ -551,6 +711,78 @@
 	status = "okay";
 };
 
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr50;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&sdmmc2 {
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sys>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk809 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+		/* vddio comes from regulator on module, use IO bank voltage instead */
+	};
+};
+
 &uart2 {
 	status = "okay";
 };
@@ -607,3 +839,20 @@
 	phy-supply = <&vcc5v0_usb_host>;
 	status = "okay";
 };
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index ecf88e0..0a764ce 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -12,7 +12,7 @@
 	};
 
 	chosen {
-		u-boot,spl-boot-order = &sdhci, &sdmmc0;
+		u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc0;
 	};
 
 	dmc: dmc {
@@ -34,11 +34,6 @@
 	};
 };
 
-&combphy1 {
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-rates;
-};
-
 &cru {
 	bootph-all;
 	status = "okay";
diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
index 3235bd3..6129664 100644
--- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
@@ -18,7 +18,7 @@
 
 &sdmmc {
 	bus-width = <4>;
-	bootph-all;
+	u-boot,dm-pre-reloc;
 	u-boot,spl-fifo-mode;
 	status = "okay";
 };
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 1e225d7..f880f4a 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -8,12 +8,12 @@
 / {
 	dmc {
 		compatible = "rockchip,rk3588-dmc";
-		bootph-all;
+		u-boot,dm-pre-reloc;
 		status = "okay";
 	};
 
 	pmu1_grf: syscon@fd58a000 {
-		bootph-all;
+		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3588-pmu1-grf", "syscon";
 		reg = <0x0 0xfd58a000 0x0 0x2000>;
 	};
@@ -46,26 +46,26 @@
 };
 
 &xin24m {
-	bootph-all;
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 
 &cru {
-	bootph-pre-ram;
+	u-boot,dm-spl;
 	status = "okay";
 };
 
 &sys_grf {
-	bootph-pre-ram;
+	u-boot,dm-spl;
 	status = "okay";
 };
 
 &uart2 {
 	clock-frequency = <24000000>;
-	bootph-pre-ram;
+	u-boot,dm-spl;
 	status = "okay";
 };
 
 &ioc {
-	bootph-pre-ram;
+	u-boot,dm-spl;
 };
diff --git a/arch/arm/dts/sun50i-a64-pinebook.dts b/arch/arm/dts/sun50i-a64-pinebook.dts
index c00c4c1..576eae1 100644
--- a/arch/arm/dts/sun50i-a64-pinebook.dts
+++ b/arch/arm/dts/sun50i-a64-pinebook.dts
@@ -406,6 +406,20 @@
 	status = "okay";
 };
 
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth {
+		compatible = "realtek,rtl8723cs-bt";
+		device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
+		enable-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+		host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+	};
+};
+
 &usb_otg {
 	dr_mode = "host";
 };
diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
index 649b146..d6897ec 100644
--- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
@@ -5,6 +5,7 @@
 
 #include "sun50i-h6.dtsi"
 #include "sun50i-h6-cpu-opp.dtsi"
+#include "sun50i-h6-gpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
diff --git a/arch/arm/dts/sun50i-h6-gpu-opp.dtsi b/arch/arm/dts/sun50i-h6-gpu-opp.dtsi
new file mode 100644
index 0000000..b48049c
--- /dev/null
+++ b/arch/arm/dts/sun50i-h6-gpu-opp.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2022 Clément Péron <peron.clem@gmail.com>
+
+/ {
+	gpu_opp_table: opp-table-gpu {
+		compatible = "operating-points-v2";
+
+		opp-216000000 {
+			opp-hz = /bits/ 64 <216000000>;
+			opp-microvolt = <810000 810000 1200000>;
+		};
+
+		opp-264000000 {
+			opp-hz = /bits/ 64 <264000000>;
+			opp-microvolt = <810000 810000 1200000>;
+		};
+
+		opp-312000000 {
+			opp-hz = /bits/ 64 <312000000>;
+			opp-microvolt = <810000 810000 1200000>;
+		};
+
+		opp-336000000 {
+			opp-hz = /bits/ 64 <336000000>;
+			opp-microvolt = <810000 810000 1200000>;
+		};
+
+		opp-360000000 {
+			opp-hz = /bits/ 64 <360000000>;
+			opp-microvolt = <820000 820000 1200000>;
+		};
+
+		opp-384000000 {
+			opp-hz = /bits/ 64 <384000000>;
+			opp-microvolt = <830000 830000 1200000>;
+		};
+
+		opp-408000000 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <840000 840000 1200000>;
+		};
+
+		opp-420000000 {
+			opp-hz = /bits/ 64 <420000000>;
+			opp-microvolt = <850000 850000 1200000>;
+		};
+
+		opp-432000000 {
+			opp-hz = /bits/ 64 <432000000>;
+			opp-microvolt = <860000 860000 1200000>;
+		};
+
+		opp-456000000 {
+			opp-hz = /bits/ 64 <456000000>;
+			opp-microvolt = <870000 870000 1200000>;
+		};
+
+		opp-504000000 {
+			opp-hz = /bits/ 64 <504000000>;
+			opp-microvolt = <890000 890000 1200000>;
+		};
+
+		opp-540000000 {
+			opp-hz = /bits/ 64 <540000000>;
+			opp-microvolt = <910000 910000 1200000>;
+		};
+
+		opp-576000000 {
+			opp-hz = /bits/ 64 <576000000>;
+			opp-microvolt = <930000 930000 1200000>;
+		};
+
+		opp-624000000 {
+			opp-hz = /bits/ 64 <624000000>;
+			opp-microvolt = <950000 950000 1200000>;
+		};
+
+		opp-756000000 {
+			opp-hz = /bits/ 64 <756000000>;
+			opp-microvolt = <1040000 1040000 1200000>;
+		};
+	};
+};
+
+&gpu {
+	operating-points-v2 = <&gpu_opp_table>;
+};
diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi
index afbbfc2..3c85c8c 100644
--- a/arch/arm/dts/sun50i-h6.dtsi
+++ b/arch/arm/dts/sun50i-h6.dtsi
@@ -161,6 +161,7 @@
 			clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>;
 			clock-names = "bus", "mod";
 			resets = <&ccu RST_BUS_VP9>;
+			iommus = <&iommu 5>;
 		};
 
 		video-codec@1c0e000 {
@@ -186,6 +187,7 @@
 			clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
 			clock-names = "core", "bus";
 			resets = <&ccu RST_BUS_GPU>;
+			#cooling-cells = <2>;
 			status = "disabled";
 		};
 
@@ -1070,9 +1072,55 @@
 		};
 
 		gpu-thermal {
-			polling-delay-passive = <0>;
-			polling-delay = <0>;
+			polling-delay-passive = <1000>;
+			polling-delay = <2000>;
 			thermal-sensors = <&ths 1>;
+
+			trips {
+				gpu_alert0: gpu-alert-0 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				gpu_alert1: gpu-alert-1 {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				gpu_alert2: gpu-alert-2 {
+					temperature = <105000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				gpu-crit {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				// Forbid the GPU to go over 756MHz
+				map0 {
+					trip = <&gpu_alert0>;
+					cooling-device = <&gpu 1 THERMAL_NO_LIMIT>;
+				};
+
+				// Forbid the GPU to go over 624MHz
+				map1 {
+					trip = <&gpu_alert1>;
+					cooling-device = <&gpu 2 THERMAL_NO_LIMIT>;
+				};
+
+				// Forbid the GPU to go over 576MHz
+				map2 {
+					trip = <&gpu_alert2>;
+					cooling-device = <&gpu 3 THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts
index 02893f3..cb8600d 100644
--- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts
+++ b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts
@@ -49,8 +49,24 @@
 		regulator-max-microvolt = <5000000>;
 		regulator-always-on;
 	};
+
+	reg_usb1_vbus: regulator-usb1-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb1-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&reg_vcc5v>;
+		enable-active-high;
+		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+	};
 };
 
+&ehci1 {
+	status = "okay";
+};
+
+/* USB 2 & 3 are on headers only. */
+
 &emac0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&ext_rgmii_pins>;
@@ -76,6 +92,10 @@
 	status = "okay";
 };
 
+&ohci1 {
+	status = "okay";
+};
+
 &r_rsb {
 	status = "okay";
 
@@ -211,3 +231,24 @@
 	pinctrl-0 = <&uart0_ph_pins>;
 	status = "okay";
 };
+
+&usbotg {
+	/*
+	 * PHY0 pins are connected to a USB-C socket, but a role switch
+	 * is not implemented: both CC pins are pulled to GND.
+	 * The VBUS pins power the device, so a fixed peripheral mode
+	 * is the best choice.
+	 * The board can be powered via GPIOs, in this case port0 *can*
+	 * act as a host (with a cable/adapter ignoring CC), as VBUS is
+	 * then provided by the GPIOs. Any user of this setup would
+	 * need to adjust the DT accordingly: dr_mode set to "host",
+	 * enabling OHCI0 and EHCI0.
+	 */
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usbphy {
+	usb1_vbus-supply = <&reg_usb1_vbus>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-h616-x96-mate.dts b/arch/arm/dts/sun50i-h616-x96-mate.dts
index 6619db3..07424c2 100644
--- a/arch/arm/dts/sun50i-h616-x96-mate.dts
+++ b/arch/arm/dts/sun50i-h616-x96-mate.dts
@@ -32,6 +32,14 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
+&ehci2 {
+	status = "okay";
+};
+
 &ir {
 	status = "okay";
 };
@@ -54,6 +62,14 @@
 	status = "okay";
 };
 
+&ohci0 {
+	status = "okay";
+};
+
+&ohci2 {
+	status = "okay";
+};
+
 &r_rsb {
 	status = "okay";
 
@@ -175,3 +191,12 @@
 	pinctrl-0 = <&uart0_ph_pins>;
 	status = "okay";
 };
+
+&usbotg {
+	dr_mode = "host";	/* USB A type receptable */
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-h616.dtsi b/arch/arm/dts/sun50i-h616.dtsi
index 622a1f7..74aed0d 100644
--- a/arch/arm/dts/sun50i-h616.dtsi
+++ b/arch/arm/dts/sun50i-h616.dtsi
@@ -504,6 +504,166 @@
 			};
 		};
 
+		usbotg: usb@5100000 {
+			compatible = "allwinner,sun50i-h616-musb",
+				     "allwinner,sun8i-h3-musb";
+			reg = <0x05100000 0x0400>;
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mc";
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			extcon = <&usbphy 0>;
+			status = "disabled";
+		};
+
+		usbphy: phy@5100400 {
+			compatible = "allwinner,sun50i-h616-usb-phy";
+			reg = <0x05100400 0x24>,
+			      <0x05101800 0x14>,
+			      <0x05200800 0x14>,
+			      <0x05310800 0x14>,
+			      <0x05311800 0x14>;
+			reg-names = "phy_ctrl",
+				    "pmu0",
+				    "pmu1",
+				    "pmu2",
+				    "pmu3";
+			clocks = <&ccu CLK_USB_PHY0>,
+				 <&ccu CLK_USB_PHY1>,
+				 <&ccu CLK_USB_PHY2>,
+				 <&ccu CLK_USB_PHY3>,
+				 <&ccu CLK_BUS_EHCI2>;
+			clock-names = "usb0_phy",
+				      "usb1_phy",
+				      "usb2_phy",
+				      "usb3_phy",
+				      "pmu2_clk";
+			resets = <&ccu RST_USB_PHY0>,
+				 <&ccu RST_USB_PHY1>,
+				 <&ccu RST_USB_PHY2>,
+				 <&ccu RST_USB_PHY3>;
+			reset-names = "usb0_reset",
+				      "usb1_reset",
+				      "usb2_reset",
+				      "usb3_reset";
+			status = "disabled";
+			#phy-cells = <1>;
+		};
+
+		ehci0: usb@5101000 {
+			compatible = "allwinner,sun50i-h616-ehci",
+				     "generic-ehci";
+			reg = <0x05101000 0x100>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_BUS_EHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>,
+				 <&ccu RST_BUS_EHCI0>;
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci0: usb@5101400 {
+			compatible = "allwinner,sun50i-h616-ohci",
+				     "generic-ohci";
+			reg = <0x05101400 0x100>;
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>;
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ehci1: usb@5200000 {
+			compatible = "allwinner,sun50i-h616-ehci",
+				     "generic-ehci";
+			reg = <0x05200000 0x100>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI1>,
+				 <&ccu CLK_BUS_EHCI1>,
+				 <&ccu CLK_USB_OHCI1>;
+			resets = <&ccu RST_BUS_OHCI1>,
+				 <&ccu RST_BUS_EHCI1>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci1: usb@5200400 {
+			compatible = "allwinner,sun50i-h616-ohci",
+				     "generic-ohci";
+			reg = <0x05200400 0x100>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI1>,
+				 <&ccu CLK_USB_OHCI1>;
+			resets = <&ccu RST_BUS_OHCI1>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ehci2: usb@5310000 {
+			compatible = "allwinner,sun50i-h616-ehci",
+				     "generic-ehci";
+			reg = <0x05310000 0x100>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI2>,
+				 <&ccu CLK_BUS_EHCI2>,
+				 <&ccu CLK_USB_OHCI2>;
+			resets = <&ccu RST_BUS_OHCI2>,
+				 <&ccu RST_BUS_EHCI2>;
+			phys = <&usbphy 2>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci2: usb@5310400 {
+			compatible = "allwinner,sun50i-h616-ohci",
+				     "generic-ohci";
+			reg = <0x05310400 0x100>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI2>,
+				 <&ccu CLK_USB_OHCI2>;
+			resets = <&ccu RST_BUS_OHCI2>;
+			phys = <&usbphy 2>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ehci3: usb@5311000 {
+			compatible = "allwinner,sun50i-h616-ehci",
+				     "generic-ehci";
+			reg = <0x05311000 0x100>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI3>,
+				 <&ccu CLK_BUS_EHCI3>,
+				 <&ccu CLK_USB_OHCI3>;
+			resets = <&ccu RST_BUS_OHCI3>,
+				 <&ccu RST_BUS_EHCI3>;
+			phys = <&usbphy 3>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci3: usb@5311400 {
+			compatible = "allwinner,sun50i-h616-ohci",
+				     "generic-ohci";
+			reg = <0x05311400 0x100>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI3>,
+				 <&ccu CLK_USB_OHCI3>;
+			resets = <&ccu RST_BUS_OHCI3>;
+			phys = <&usbphy 3>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
 		rtc: rtc@7000000 {
 			compatible = "allwinner,sun50i-h616-rtc";
 			reg = <0x07000000 0x400>;
diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi
index 0edc172..9455d27 100644
--- a/arch/arm/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/dts/suniv-f1c100s.dtsi
@@ -166,6 +166,12 @@
 				drive-strength = <30>;
 			};
 
+			/omit-if-no-ref/
+			i2c0_pd_pins: i2c0-pd-pins {
+				pins = "PD0", "PD12";
+				function = "i2c0";
+			};
+
 			spi0_pc_pins: spi0-pc-pins {
 				pins = "PC0", "PC1", "PC2", "PC3";
 				function = "spi0";
@@ -177,6 +183,42 @@
 			};
 		};
 
+		i2c0: i2c@1c27000 {
+			compatible = "allwinner,suniv-f1c100s-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01c27000 0x400>;
+			interrupts = <7>;
+			clocks = <&ccu CLK_BUS_I2C0>;
+			resets = <&ccu RST_BUS_I2C0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@1c27400 {
+			compatible = "allwinner,suniv-f1c100s-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01c27400 0x400>;
+			interrupts = <8>;
+			clocks = <&ccu CLK_BUS_I2C1>;
+			resets = <&ccu RST_BUS_I2C1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@1c27800 {
+			compatible = "allwinner,suniv-f1c100s-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x01c27800 0x400>;
+			interrupts = <9>;
+			clocks = <&ccu CLK_BUS_I2C2>;
+			resets = <&ccu RST_BUS_I2C2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		timer@1c20c00 {
 			compatible = "allwinner,suniv-f1c100s-timer";
 			reg = <0x01c20c00 0x90>;
@@ -192,6 +234,34 @@
 			clocks = <&osc32k>;
 		};
 
+		pwm: pwm@1c21000 {
+			compatible = "allwinner,suniv-f1c100s-pwm",
+				     "allwinner,sun7i-a20-pwm";
+			reg = <0x01c21000 0x400>;
+			clocks = <&osc24M>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		ir: ir@1c22c00 {
+			compatible = "allwinner,suniv-f1c100s-ir",
+				     "allwinner,sun6i-a31-ir";
+			reg = <0x01c22c00 0x400>;
+			clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>;
+			clock-names = "apb", "ir";
+			resets = <&ccu RST_BUS_IR>;
+			interrupts = <6>;
+			status = "disabled";
+		};
+
+		lradc: lradc@1c23400 {
+			compatible = "allwinner,suniv-f1c100s-lradc",
+				     "allwinner,sun8i-a83t-r-lradc";
+			reg = <0x01c23400 0x400>;
+			interrupts = <22>;
+			status = "disabled";
+		};
+
 		uart0: serial@1c25000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c25000 0x400>;
diff --git a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi
index e899d14..1d1d127 100644
--- a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi
+++ b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi
@@ -89,13 +89,13 @@
 	};
 
 	reg_gmac_3v3: gmac-3v3 {
-		      compatible = "regulator-fixed";
-		      regulator-name = "gmac-3v3";
-		      regulator-min-microvolt = <3300000>;
-		      regulator-max-microvolt = <3300000>;
-		      startup-delay-us = <100000>;
-		      enable-active-high;
-		      gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+		compatible = "regulator-fixed";
+		regulator-name = "gmac-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <100000>;
+		enable-active-high;
+		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
 	};
 
 	wifi_pwrseq: wifi_pwrseq {
diff --git a/arch/arm/dts/sunxi-h3-h5.dtsi b/arch/arm/dts/sunxi-h3-h5.dtsi
index 6439141..fc1af9b 100644
--- a/arch/arm/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/dts/sunxi-h3-h5.dtsi
@@ -302,6 +302,8 @@
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
 			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+			phys = <&usbphy 0>;
+			phy-names = "usb";
 			status = "disabled";
 		};
 
@@ -312,6 +314,8 @@
 			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
 				 <&ccu CLK_USB_OHCI0>;
 			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+			phys = <&usbphy 0>;
+			phy-names = "usb";
 			status = "disabled";
 		};
 
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
index 4a08820a..69ef19c 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -82,7 +82,7 @@ static struct mm_region rk3568_mem_map[] = {
 };
 
 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
-	[BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000",
+	[BROM_BOOTSOURCE_EMMC] = "/mmc@fe310000",
 	[BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0",
 	[BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000",
 };
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c
index 2ee1db4..18e67b5 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -8,6 +8,7 @@
 #include <spl.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
 #include <asm/arch-rockchip/hardware.h>
 #include <asm/arch-rockchip/ioc_rk3588.h>
 
@@ -36,6 +37,12 @@ DECLARE_GLOBAL_DATA_PTR;
 #define BUS_IOC_GPIO2D_IOMUX_SEL_H	0x5c
 #define BUS_IOC_GPIO3A_IOMUX_SEL_L	0x60
 
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e0000",
+	[BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b0000/flash@0",
+	[BROM_BOOTSOURCE_SD] = "/mmc@fe2c0000",
+};
+
 static struct mm_region rk3588_mem_map[] = {
 	{
 		.virt = 0x0UL,
diff --git a/arch/m68k/cpu/mcf523x/interrupts.c b/arch/m68k/cpu/mcf523x/interrupts.c
index 331288e..b02ea29 100644
--- a/arch/m68k/cpu/mcf523x/interrupts.c
+++ b/arch/m68k/cpu/mcf523x/interrupts.c
@@ -22,7 +22,7 @@ int interrupt_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
 	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
diff --git a/arch/m68k/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c
index e8a1e13..e787c76 100644
--- a/arch/m68k/cpu/mcf52x2/interrupts.c
+++ b/arch/m68k/cpu/mcf52x2/interrupts.c
@@ -34,7 +34,7 @@ int interrupt_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
 	intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE);
@@ -42,7 +42,7 @@ void dtimer_intr_setup(void)
 	clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
 	setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI);
 }
-#endif				/* CONFIG_MCFTMR */
+#endif				/* CFG_MCFTMR */
 #endif				/* CONFIG_M5272 */
 
 #if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
@@ -63,7 +63,7 @@ int interrupt_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
 	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
@@ -72,7 +72,7 @@ void dtimer_intr_setup(void)
 	clrbits_be32(&intp->imrl0, 0x00000001);
 	clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
 }
-#endif				/* CONFIG_MCFTMR */
+#endif				/* CFG_MCFTMR */
 #endif				/* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
 
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
@@ -83,11 +83,11 @@ int interrupt_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
 	mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
 	mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI);
 }
-#endif				/* CONFIG_MCFTMR */
+#endif				/* CFG_MCFTMR */
 #endif				/* CONFIG_M5249 || CONFIG_M5253 */
diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S
index dbe2b54..cef8d79 100644
--- a/arch/m68k/cpu/mcf530x/start.S
+++ b/arch/m68k/cpu/mcf530x/start.S
@@ -132,7 +132,8 @@ _start:
 	 * then (and always) gd struct space will be reserved
 	 */
 	move.l	%sp, -(%sp)
-	bsr	board_init_f_alloc_reserve
+	move.l	#board_init_f_alloc_reserve, %a1
+	jsr	(%a1)
 
 	/* update stack and frame-pointers */
 	move.l	%d0, %sp
@@ -140,14 +141,17 @@ _start:
 
 	/* initialize reserved area */
 	move.l	%d0, -(%sp)
-	bsr	board_init_f_init_reserve
+	move.l	#board_init_f_init_reserve, %a1
+	jsr	(%a1)
 
 	/* run low-level CPU init code (from flash) */
-	bsr	cpu_init_f
+	move.l	#cpu_init_f, %a1
+	jsr	(%a1)
 
 	/* run low-level board init code (from flash) */
 	clr.l	%sp@-
-	bsr	board_init_f
+	move.l	#board_init_f, %a1
+	jsr	(%a1)
 
 	/* board_init_f() does not return */
 
@@ -239,7 +243,8 @@ _fault:
 _exc_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr	exc_handler
+	move.l	#exc_handler, %a1
+	jsr	(%a1)
 	addql	#4,%sp
 	RESTORE_ALL
 
@@ -247,7 +252,8 @@ _exc_handler:
 _int_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr	int_handler
+	move.l	#int_handler, %a1
+	jsr	(%a1)
 	addql	#4,%sp
 	RESTORE_ALL
 
diff --git a/arch/m68k/cpu/mcf532x/interrupts.c b/arch/m68k/cpu/mcf532x/interrupts.c
index 64e0466..bbe823c 100644
--- a/arch/m68k/cpu/mcf532x/interrupts.c
+++ b/arch/m68k/cpu/mcf532x/interrupts.c
@@ -23,7 +23,7 @@ int interrupt_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
 	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
diff --git a/arch/m68k/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c
index ea0cf87..fb80a87 100644
--- a/arch/m68k/cpu/mcf5445x/interrupts.c
+++ b/arch/m68k/cpu/mcf5445x/interrupts.c
@@ -26,7 +26,7 @@ int interrupt_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 void dtimer_intr_setup(void)
 {
 	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
diff --git a/arch/m68k/dts/stmark2.dts b/arch/m68k/dts/stmark2.dts
index 56c328f..ebe8580 100644
--- a/arch/m68k/dts/stmark2.dts
+++ b/arch/m68k/dts/stmark2.dts
@@ -27,7 +27,7 @@
 	flash: is25lp128@1 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "spi-flash";
+		compatible = "jedec,spi-nor";
 		spi-max-frequency = <60000000>;
 		reg = <1>;
 	};
diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h
index 273e843..5f576ba 100644
--- a/arch/m68k/include/asm/global_data.h
+++ b/arch/m68k/include/asm/global_data.h
@@ -23,6 +23,9 @@ struct arch_global_data {
 #ifdef CONFIG_MCF5441x
 	unsigned long sdhc_clk;
 #endif
+#if defined(CONFIG_FSL_ESDHC)
+	u32 sdhc_per_clk;
+#endif
 };
 
 #include <asm-generic/global_data.h>
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index 8207c8d..74516cc 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -16,7 +16,7 @@
 #define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -38,7 +38,7 @@
 #define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -63,7 +63,7 @@
 #define CFG_SYS_NUM_IRQS		(64)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
@@ -86,7 +86,7 @@
 #define CFG_SYS_NUM_IRQS		(64)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
@@ -105,7 +105,7 @@
 #define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -130,7 +130,7 @@
 #define CFG_SYS_NUM_IRQS		(64)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_TMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_TMR3)
 #define CFG_SYS_TMRPND_REG		(((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
@@ -152,7 +152,7 @@
 #define CFG_SYS_NUM_IRQS		(192)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -174,7 +174,7 @@
 #define CFG_SYS_NUM_IRQS		(128)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -196,7 +196,7 @@
 #define CFG_SYS_NUM_IRQS             (64)
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE          (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE             (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG		(((volatile intctrl_t *) \
@@ -217,7 +217,7 @@
 #define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -239,7 +239,7 @@
 #define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -269,7 +269,7 @@
 #define MMAP_DSPI			MMAP_DSPI0
 
 /* Timer */
-#ifdef CONFIG_MCFTMR
+#ifdef CFG_MCFTMR
 #define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG	(((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile
index b66d66a..6e1fd93 100644
--- a/arch/m68k/lib/Makefile
+++ b/arch/m68k/lib/Makefile
@@ -5,7 +5,7 @@
 
 ## Build a couple of necessary functions into a private libgcc
 ## if the user asked for it
-lib-$(CONFIG_USE_PRIVATE_LIBGCC) += lshrdi3.o muldi3.o ashldi3.o
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += lshrdi3.o muldi3.o ashldi3.o ashrdi3.o
 
 obj-y	+= bdinfo.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/m68k/lib/ashrdi3.c b/arch/m68k/lib/ashrdi3.c
new file mode 100644
index 0000000..e144378
--- /dev/null
+++ b/arch/m68k/lib/ashrdi3.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ashrdi3.c extracted from gcc-2.7.2/libgcc2.c which is:
+ * Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
+ */
+
+#define BITS_PER_UNIT 8
+
+typedef		 int SItype	__attribute__((mode(SI)));
+typedef unsigned int USItype	__attribute__((mode(SI)));
+typedef		 int DItype	__attribute__((mode(DI)));
+typedef int word_type           __attribute__((mode(__word__)));
+
+struct DIstruct {
+	SItype high, low;
+};
+
+typedef union {
+	struct DIstruct s;
+	DItype ll;
+} di_union;
+
+DItype __ashrdi3(DItype u, word_type b)
+{
+	di_union w;
+	word_type bm;
+	di_union uu;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+
+	bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
+	if (bm <= 0) {
+		/* w.s.high = 1..1 or 0..0 */
+		w.s.high = uu.s.high >> (sizeof(SItype) * BITS_PER_UNIT - 1);
+		w.s.low = uu.s.high >> -bm;
+	} else {
+		USItype carries = (USItype)uu.s.high << bm;
+
+		w.s.high = uu.s.high >> b;
+		w.s.low = ((USItype)uu.s.low >> b) | carries;
+	}
+
+	return w.ll;
+}
+
diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c
index 2ce6908..ca8c039 100644
--- a/arch/m68k/lib/time.c
+++ b/arch/m68k/lib/time.c
@@ -25,7 +25,7 @@ static volatile ulong timestamp = 0;
 #define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
 #endif
 
-#if defined(CONFIG_MCFTMR)
+#if defined(CFG_MCFTMR)
 #ifndef CFG_SYS_UDELAY_BASE
 #	error	"uDelay base not defined!"
 #endif
@@ -111,7 +111,7 @@ ulong get_timer(ulong base)
 	return (timestamp - base);
 }
 
-#endif				/* CONFIG_MCFTMR */
+#endif				/* CFG_MCFTMR */
 
 /*
  * This function is derived from PowerPC code (read timebase as long long).
diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c
index fbd4835..eeb9cfd 100644
--- a/board/freescale/m5253demo/flash.c
+++ b/board/freescale/m5253demo/flash.c
@@ -96,24 +96,8 @@ void flash_print_info(flash_info_t * info)
 		return;
 	}
 
-	if (info->size > 0x100000) {
-		int remainder;
-
-		printf("  Size: %ld", info->size >> 20);
-
-		remainder = (info->size % 0x100000);
-		if (remainder) {
-			remainder >>= 10;
-			remainder = (int)((float)
-					  (((float)remainder / (float)1024) *
-					   10000));
-			printf(".%d ", remainder);
-		}
-
-		printf("MB in %d Sectors\n", info->sector_count);
-	} else
-		printf("  Size: %ld KB in %d Sectors\n",
-		       info->size >> 10, info->sector_count);
+	printf("  Size: %ld KB in %d Sectors\n",
+	       info->size >> 10, info->sector_count);
 
 	printf("  Sector Start Addresses:");
 	for (i = 0; i < info->sector_count; ++i) {
diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README
index 34f05f3..5d5c5e7 100644
--- a/board/freescale/m53017evb/README
+++ b/board/freescale/m53017evb/README
@@ -87,7 +87,7 @@ CONFIG_SYS_FEC0_PINMUX		-- Set FEC0 Pin configuration
 CONFIG_SYS_FEC0_MIIBASE		-- Set FEC0 MII base register
 MCFFEC_TOUT_LOOP		-- set FEC timeout loop
 
-CONFIG_MCFTMR			-- define to use DMA timer
+CFG_MCFTMR			-- define to use DMA timer
 
 CONFIG_SYS_I2C_FSL		-- define to use FSL common I2C driver
 CONFIG_SYS_I2C_SOFT		-- define for I2C bit-banged
diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README
index 7240648..e8bf75f 100644
--- a/board/freescale/m5373evb/README
+++ b/board/freescale/m5373evb/README
@@ -86,7 +86,7 @@ CONFIG_SYS_FEC0_PINMUX		-- Set FEC0 Pin configuration
 CONFIG_SYS_FEC0_MIIBASE	-- Set FEC0 MII base register
 MCFFEC_TOUT_LOOP	-- set FEC timeout loop
 
-CONFIG_MCFTMR		-- define to use DMA timer
+CFG_MCFTMR		-- define to use DMA timer
 
 CONFIG_SYS_I2C_FSL	-- define to use FSL common I2C driver
 CONFIG_SYS_I2C_SOFT	-- define for I2C bit-banged
diff --git a/board/sysam/stmark2/Kconfig b/board/sysam/stmark2/Kconfig
index b259505..94f5049 100644
--- a/board/sysam/stmark2/Kconfig
+++ b/board/sysam/stmark2/Kconfig
@@ -11,7 +11,7 @@ config SERIAL_BOOT
 	depends on CF_SBF
 
 config SYS_INPUT_CLKSRC
-	hex
+	int "External crystal clock"
 	default 30000000
 
 config SYS_CPU
diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig
index 263e57f..3263414 100644
--- a/configs/M5208EVBE_defconfig
+++ b/configs/M5208EVBE_defconfig
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_ENV_ADDR=0x2000
 CONFIG_TARGET_M5208EVBE=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0x00000400
 CONFIG_BOOTDELAY=1
diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig
index 88c1116..0b92456 100644
--- a/configs/M5235EVB_Flash32_defconfig
+++ b/configs/M5235EVB_Flash32_defconfig
@@ -8,7 +8,6 @@ CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5235EVB=y
 CONFIG_NORFLASH_PS32BIT=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0xFFC00400
 CONFIG_BOOTDELAY=1
diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig
index 255f3b9..fbd3e08 100644
--- a/configs/M5235EVB_defconfig
+++ b/configs/M5235EVB_defconfig
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5235EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0xFFE00400
 CONFIG_BOOTDELAY=1
diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig
index de7f141..78f1f4f 100644
--- a/configs/M5249EVB_defconfig
+++ b/configs/M5249EVB_defconfig
@@ -7,7 +7,6 @@ CONFIG_DEFAULT_DEVICE_TREE="M5249EVB"
 CONFIG_SYS_LOAD_ADDR=0x200000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5249EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=131072
 CONFIG_SYS_MONITOR_BASE=0xFFE00400
 # CONFIG_AUTOBOOT is not set
diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig
index ea07997..e6ab998 100644
--- a/configs/M5253DEMO_defconfig
+++ b/configs/M5253DEMO_defconfig
@@ -7,7 +7,6 @@ CONFIG_DEFAULT_DEVICE_TREE="M5253DEMO"
 CONFIG_SYS_LOAD_ADDR=0x100000
 CONFIG_ENV_ADDR=0xFF804000
 CONFIG_TARGET_M5253DEMO=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0xFF800400
 CONFIG_BOOTDELAY=5
diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig
index 324daa0..1c51c4a 100644
--- a/configs/M5272C3_defconfig
+++ b/configs/M5272C3_defconfig
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5272C3=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=131072
 CONFIG_SYS_MONITOR_BASE=0xFFE00400
 CONFIG_BOOTDELAY=5
diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig
index d84d9d9..ca1c184 100644
--- a/configs/M5275EVB_defconfig
+++ b/configs/M5275EVB_defconfig
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x800000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5275EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=131072
 CONFIG_SYS_MONITOR_BASE=0xFFE00400
 CONFIG_BOOTDELAY=5
diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig
index 7988d25..2b053e3 100644
--- a/configs/M5282EVB_defconfig
+++ b/configs/M5282EVB_defconfig
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_M5282EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=131072
 CONFIG_SYS_MONITOR_BASE=0xFFE00400
 CONFIG_BOOTDELAY=5
diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig
index d7c07aa..c70964f 100644
--- a/configs/M53017EVB_defconfig
+++ b/configs/M53017EVB_defconfig
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_ENV_ADDR=0x40000
 CONFIG_TARGET_M53017EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0x00000400
 CONFIG_BOOTDELAY=1
diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig
index 989af92..455eea2 100644
--- a/configs/M5329AFEE_defconfig
+++ b/configs/M5329AFEE_defconfig
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_ENV_ADDR=0x4000
 CONFIG_TARGET_M5329EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0x00000400
 CONFIG_BOOTDELAY=1
diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig
index 7be2a27..0251444 100644
--- a/configs/M5329BFEE_defconfig
+++ b/configs/M5329BFEE_defconfig
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_ENV_ADDR=0x4000
 CONFIG_TARGET_M5329EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0x00000400
 CONFIG_BOOTDELAY=1
diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig
index 4b278a5..eec95da 100644
--- a/configs/M5373EVB_defconfig
+++ b/configs/M5373EVB_defconfig
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_ENV_ADDR=0x4000
 CONFIG_TARGET_M5373EVB=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0x00000400
 CONFIG_BOOTDELAY=1
diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig
index 6775379..e618ca0 100644
--- a/configs/amcore_defconfig
+++ b/configs/amcore_defconfig
@@ -9,8 +9,7 @@ CONFIG_SYS_PROMPT="amcore $ "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFFC1F000
 CONFIG_TARGET_AMCORE=y
-CONFIG_MCFTMR=y
-CONFIG_SYS_MONITOR_LEN=126976
+CONFIG_SYS_MONITOR_LEN=192512
 CONFIG_SYS_MONITOR_BASE=0xFFC00400
 CONFIG_BOOTDELAY=1
 CONFIG_USE_BOOTCOMMAND=y
@@ -18,6 +17,7 @@ CONFIG_BOOTCOMMAND="bootm ffc20000"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SYS_MALLOC_BOOTPARAMS=y
+CONFIG_SYS_BOOTPARAMS_LEN=65536
 # CONFIG_CMDLINE_EDITING is not set
 # CONFIG_SYS_LONGHELP is not set
 CONFIG_SYS_PBSIZE=282
diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index a1a2562..827ebfe 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="URMEL > "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0x1FF8000
 CONFIG_TARGET_ASTRO_MCF5373L=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_SYS_MONITOR_BASE=0x00000400
 CONFIG_BOOTDELAY=1
diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig
index 377781f..6d6380f 100644
--- a/configs/cobra5272_defconfig
+++ b/configs/cobra5272_defconfig
@@ -8,7 +8,6 @@ CONFIG_SYS_PROMPT="COBRA > "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFFE04000
 CONFIG_TARGET_COBRA5272=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_MONITOR_LEN=131072
 CONFIG_SYS_MONITOR_BASE=0xFFE00400
 CONFIG_BOOTDELAY=5
diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig
index 7304b49..6f0882f 100644
--- a/configs/eb_cpu5282_defconfig
+++ b/configs/eb_cpu5282_defconfig
@@ -7,7 +7,6 @@ CONFIG_SYS_PROMPT="\nEB+CPU5282> "
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFF040000
 CONFIG_TARGET_EB_CPU5282=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_BARGSIZE=1024
 CONFIG_SYS_MONITOR_LEN=131072
 CONFIG_SYS_MONITOR_BASE=0xFF000400
diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig
index 5ecdda4..5f4ec93 100644
--- a/configs/eb_cpu5282_internal_defconfig
+++ b/configs/eb_cpu5282_internal_defconfig
@@ -6,7 +6,6 @@ CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282_internal"
 CONFIG_SYS_LOAD_ADDR=0x20000
 CONFIG_ENV_ADDR=0xFF040000
 CONFIG_TARGET_EB_CPU5282=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_BARGSIZE=1024
 CONFIG_SYS_MONITOR_LEN=131072
 CONFIG_SYS_MONITOR_BASE=0xF0000418
diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig
index ae7a9cf..ee75709 100644
--- a/configs/stmark2_defconfig
+++ b/configs/stmark2_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE="stmark2"
 CONFIG_SYS_PROMPT="stmark2 $ "
 CONFIG_SYS_LOAD_ADDR=0x40010000
 CONFIG_TARGET_STMARK2=y
-CONFIG_MCFTMR=y
 CONFIG_SYS_BARGSIZE=256
 CONFIG_SYS_MONITOR_LEN=262144
 CONFIG_TIMESTAMP=y
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index 99c195b..1c6adc5 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -14,6 +14,7 @@
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/hardware.h>
 #include <asm/io.h>
+#include <dm/device-internal.h>
 #include <dm/lists.h>
 #include <dt-bindings/clock/rk3568-cru.h>
 
@@ -424,6 +425,9 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate)
 	case PCLK_PMU:
 		ret = rk3568_pmu_set_pmuclk(priv, rate);
 		break;
+	case CLK_PCIEPHY0_REF:
+	case CLK_PCIEPHY1_REF:
+		return 0;
 	default:
 		return -ENOENT;
 	}
@@ -2937,6 +2941,7 @@ static int rk3568_clk_bind(struct udevice *dev)
 						    glb_srst_fst);
 		priv->glb_srst_snd_value = offsetof(struct rk3568_cru,
 						    glb_srsr_snd);
+		dev_set_priv(sys_child, priv);
 	}
 
 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
index 5271d94..a7df553 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -1558,7 +1558,7 @@ static ulong rk3588_clk_get_rate(struct clk *clk)
 #ifndef CONFIG_SPL_BUILD
 	case CLK_AUX16M_0:
 	case CLK_AUX16M_1:
-		rk3588_aux16m_get_clk(priv, clk->id);
+		rate = rk3588_aux16m_get_clk(priv, clk->id);
 		break;
 	case ACLK_VOP_ROOT:
 	case ACLK_VOP:
@@ -1707,7 +1707,7 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate)
 #ifndef CONFIG_SPL_BUILD
 	case CLK_AUX16M_0:
 	case CLK_AUX16M_1:
-		rk3588_aux16m_set_clk(priv, clk->id, rate);
+		ret = rk3588_aux16m_set_clk(priv, clk->id, rate);
 		break;
 	case ACLK_VOP_ROOT:
 	case ACLK_VOP:
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 3661ce3..72c820e 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -52,7 +52,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
 	ret = clk_set_rate(&priv->clk, freq);
 	if (ret < 0) {
 		debug("%s: err=%d\n", __func__, ret);
-		return ret;
+		return 0;
 	}
 
 	return freq;
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 9608770..e1409dd 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -61,6 +61,7 @@
 #define DWCMSHC_EMMC_DLL_RXCLK		0x804
 #define DWCMSHC_EMMC_DLL_TXCLK		0x808
 #define DWCMSHC_EMMC_DLL_STRBIN		0x80c
+#define DECMSHC_EMMC_DLL_CMDOUT		0x810
 #define DWCMSHC_EMMC_DLL_STATUS0	0x840
 #define DWCMSHC_EMMC_DLL_STATUS1	0x844
 #define DWCMSHC_EMMC_DLL_START		BIT(0)
@@ -69,6 +70,7 @@
 #define DWCMSHC_EMMC_DLL_START_DEFAULT	5
 #define DWCMSHC_EMMC_DLL_INC_VALUE	2
 #define DWCMSHC_EMMC_DLL_INC		8
+#define DWCMSHC_EMMC_DLL_BYPASS		BIT(24)
 #define DWCMSHC_EMMC_DLL_DLYENA		BIT(27)
 #define DLL_TXCLK_TAPNUM_DEFAULT	0xA
 
@@ -83,6 +85,7 @@
 #define DWCMSHC_EMMC_DLL_TIMEOUT	BIT(9)
 #define DLL_RXCLK_NO_INVERTER		1
 #define DLL_RXCLK_INVERTER		0
+#define DLL_RXCLK_ORI_GATE		BIT(31)
 #define DWCMSHC_ENHANCED_STROBE		BIT(8)
 #define DLL_LOCK_WO_TMOUT(x) \
 	((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
@@ -348,10 +351,14 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo
 			DLL_STRBIN_TAPNUM_FROM_SW;
 		sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
 	} else {
-		/* reset the clock phase when the frequency is lower than 100MHz */
-		sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
-		extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
-		sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
+		/*
+		 * Disable DLL and reset both of sample and drive clock.
+		 * The bypass bit and start bit need to be set if DLL is not locked.
+		 */
+		sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START,
+			     DWCMSHC_EMMC_DLL_CTRL);
+		sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
+		sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
 		sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
 		/*
 		 * Before switching to hs400es mode, the driver will enable
diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c
index 62eacb9..e66c49a 100644
--- a/drivers/timer/rockchip_timer.c
+++ b/drivers/timer/rockchip_timer.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 struct rockchip_timer_plat {
-	struct dtd_rockchip_rk3368_timer dtd;
+	struct dtd_rockchip_rk3288_timer dtd;
 };
 #endif
 
@@ -152,14 +152,12 @@ static const struct timer_ops rockchip_timer_ops = {
 };
 
 static const struct udevice_id rockchip_timer_ids[] = {
-	{ .compatible = "rockchip,rk3188-timer" },
 	{ .compatible = "rockchip,rk3288-timer" },
-	{ .compatible = "rockchip,rk3368-timer" },
 	{}
 };
 
-U_BOOT_DRIVER(rockchip_rk3368_timer) = {
-	.name	= "rockchip_rk3368_timer",
+U_BOOT_DRIVER(rockchip_rk3288_timer) = {
+	.name	= "rockchip_rk3288_timer",
 	.id	= UCLASS_TIMER,
 	.of_match = rockchip_timer_ids,
 	.probe = rockchip_timer_probe,
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index a4fda55..4b89f31 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -111,4 +111,6 @@
 #define CFG_SYS_CS0_MASK		0x007F0001
 #define CFG_SYS_CS0_CTRL		0x00001FA0
 
+#define CFG_MCFTMR
+
 #endif				/* _M5208EVBE_H */
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 8939c8e..14d4617 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -130,4 +130,6 @@
 #	define CFG_SYS_CS0_CTRL	0x00001D80
 #endif
 
+#define CFG_MCFTMR
+
 #endif				/* _M5329EVB_H */
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index 4fd539c..b240423 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -120,4 +120,6 @@
 #define	CFG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
 #define CFG_SYS_GPIO1_LED		0x00400000	/* user led                     */
 
+#define CFG_MCFTMR
+
 #endif	/* M5249 */
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index a6349fc..008c725 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -132,4 +132,6 @@
 #define CFG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
 #define CFG_SYS_GPIO1_LED		0x00400000	/* user led */
 
+#define CFG_MCFTMR
+
 #endif				/* _M5253DEMO_H */
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 33c2fc0..49cf3e8 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -106,4 +106,7 @@
 #define CFG_SYS_PBDDR		0x0000
 #define CFG_SYS_PBDAT		0x0000
 #define CFG_SYS_PDCNT		0x00000000
+
+#define CFG_MCFTMR
+
 #endif				/* _M5272C3_H */
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 607c5de..965327d 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -116,4 +116,6 @@
 #define CFG_SYS_CS1_CTRL		0x00001900
 #define CFG_SYS_CS1_MASK		0x00070001
 
+#define CFG_MCFTMR
+
 #endif	/* _M5275EVB_H */
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 31699a4..f04d9b1 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -127,4 +127,6 @@
 #define CFG_SYS_DDRUA		0x05
 #define CFG_SYS_PJPAR		0xFF
 
+#define CFG_MCFTMR
+
 #endif				/* _CONFIG_M5282EVB_H */
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 6359915..04c456f 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -132,4 +132,6 @@
 #define CFG_SYS_CS1_MASK		0x00070001
 #define CFG_SYS_CS1_CTRL		0x00001FA0
 
+#define CFG_MCFTMR
+
 #endif				/* _M53017EVB_H */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 456135b..0aa1ffd 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -138,4 +138,6 @@
 #define CFG_SYS_CS2_CTRL		0x00001f60
 #endif
 
+#define CFG_MCFTMR
+
 #endif				/* _M5329EVB_H */
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 4e8dcb5..8b9e65d 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -136,4 +136,6 @@
 #define CFG_SYS_CS2_MASK		(16 << 20)
 #define CFG_SYS_CS2_CTRL		0x00001f60
 
+#define CFG_MCFTMR
+
 #endif				/* _M5373EVB_H */
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index 648d30a..ca8d17b 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -10,14 +10,18 @@
 
 #define CFG_SYS_UART_PORT		0
 
-#define CFG_EXTRA_ENV_SETTINGS				\
+#define CFG_MCFTMR
+#define CFG_SYS_UART_PORT		0
+#define CFG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_EXTRA_ENV_SETTINGS					\
 	"upgrade_uboot=loady; "					\
-		"protect off 0xffc00000 0xffc1ffff; "		\
-		"erase 0xffc00000 0xffc1ffff; "			\
+		"protect off 0xffc00000 0xffc2ffff; "		\
+		"erase 0xffc00000 0xffc2ffff; "			\
 		"cp.b 0x20000 0xffc00000 ${filesize}\0"		\
 	"upgrade_kernel=loady; "				\
-		"erase 0xffc20000 0xffefffff; "			\
-		"cp.b 0x20000 0xffc20000 ${filesize}\0"		\
+		"erase 0xffc30000 0xffefffff; "			\
+		"cp.b 0x20000 0xffc30000 ${filesize}\0"		\
 	"upgrade_jffs2=loady; "					\
 		"erase 0xfff00000 0xffffffff; "			\
 		"cp.b 0x20000 0xfff00000 ${filesize}\0"
@@ -37,7 +41,6 @@
 
 /* amcore design has flash data bytes wired swapped */
 #define CFG_SYS_WRITE_SWAPPED_DATA
-/* reserve 128-4KB */
 
 #define LDS_BOARD_TEXT \
 	. = DEFINED(env_offset) ? env_offset : .; \
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index 6522432..80f8c41 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -184,4 +184,6 @@
 #define CFG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
 					 CF_CACR_DCM_P)
 
+#define CFG_MCFTMR
+
 #endif	/* _CONFIG_ASTRO_MCF5373L_H */
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index cd50ffe..276ecc3 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -184,4 +184,6 @@ configuration */
 #define CFG_SYS_PBDAT		0x0000			/* PortB value reg. */
 #define CFG_SYS_PDCNT		0x00000000		/* PortD control reg. */
 
+#define CFG_MCFTMR
+
 #endif	/* _CONFIG_COBRA5272_H */
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index 26e4ade..9503ab6 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -138,5 +138,7 @@
 #define CFG_SYS_DDRUA		0x05
 #define CFG_SYS_PJPAR		0xFF
 
+#define CFG_MCFTMR
+
 #endif	/* _CONFIG_M5282EVB_H */
 /*---------------------------------------------------------------------*/
diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h
index cac613d..d10e5b1 100644
--- a/include/configs/evb_rk3328.h
+++ b/include/configs/evb_rk3328.h
@@ -8,6 +8,4 @@
 
 #include <configs/rk3328_common.h>
 
-#define SDRAM_BANK_SIZE			(2UL << 30)
-
 #endif
diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h
index b7e8503..70ab587 100644
--- a/include/configs/evb_rk3399.h
+++ b/include/configs/evb_rk3399.h
@@ -13,6 +13,4 @@
 
 #include <configs/rk3399_common.h>
 
-#define SDRAM_BANK_SIZE			(2UL << 30)
-
 #endif
diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h
index 241dc39..141ffcd 100644
--- a/include/configs/pinebook-pro-rk3399.h
+++ b/include/configs/pinebook-pro-rk3399.h
@@ -14,6 +14,4 @@
 
 #include <configs/rk3399_common.h>
 
-#define SDRAM_BANK_SIZE			(2UL << 30)
-
 #endif
diff --git a/include/configs/pinephone-pro-rk3399.h b/include/configs/pinephone-pro-rk3399.h
index 78017d6..9cd4447 100644
--- a/include/configs/pinephone-pro-rk3399.h
+++ b/include/configs/pinephone-pro-rk3399.h
@@ -14,6 +14,4 @@
 
 #include <configs/rk3399_common.h>
 
-#define SDRAM_BANK_SIZE			(2UL << 30)
-
 #endif
diff --git a/include/configs/puma_rk3399.h b/include/configs/puma_rk3399.h
index 23de326..969acc8 100644
--- a/include/configs/puma_rk3399.h
+++ b/include/configs/puma_rk3399.h
@@ -8,6 +8,4 @@
 
 #include <configs/rk3399_common.h>
 
-#define SDRAM_BANK_SIZE			(2UL << 30)
-
 #endif
diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h
index c0896e5..8df481b 100644
--- a/include/configs/px30_common.h
+++ b/include/configs/px30_common.h
@@ -15,7 +15,6 @@
 
 #define CFG_SYS_SDRAM_BASE		0
 #define SDRAM_MAX_SIZE			0xff000000
-#define SDRAM_BANK_SIZE			(2UL << 30)
 
 #define ENV_MEM_LAYOUT_SETTINGS \
 	"scriptaddr=0x00500000\0" \
diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
index 8aa17bf..8736b14 100644
--- a/include/configs/rk3128_common.h
+++ b/include/configs/rk3128_common.h
@@ -12,13 +12,9 @@
 
 #define CFG_IRAM_BASE		0x10080000
 
-/* RAW SD card / eMMC locations. */
-
 #define CFG_SYS_SDRAM_BASE		0x60000000
 #define SDRAM_MAX_SIZE			0x80000000
 
-/* usb mass storage */
-
 #define ENV_MEM_LAYOUT_SETTINGS \
 	"scriptaddr=0x60500000\0" \
 	"pxefile_addr_r=0x60600000\0" \
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index ac91956..fcb2745 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -11,15 +11,9 @@
 
 #define CFG_IRAM_BASE	0x10080000
 
-/* spl size 32kb sram - 2kb bootrom */
-
 #define CFG_SYS_SDRAM_BASE		0x60000000
-#define SDRAM_BANK_SIZE			(2UL << 30)
 #define SDRAM_MAX_SIZE			0x80000000
 
-/* usb otg */
-
-/* usb host support */
 #define ENV_MEM_LAYOUT_SETTINGS \
 	"scriptaddr=0x60000000\0" \
 	"pxefile_addr_r=0x60100000\0" \
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index fcaf9c5..39a40f4 100644
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -13,7 +13,6 @@
 #define CFG_IRAM_BASE		0x10080000
 
 #define CFG_SYS_SDRAM_BASE		0x60000000
-#define SDRAM_BANK_SIZE			(512UL << 20UL)
 #define SDRAM_MAX_SIZE			0x80000000
 
 #define ENV_MEM_LAYOUT_SETTINGS \
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 5f29432..71d2426 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -13,10 +13,7 @@
 
 #define CFG_IRAM_BASE		0xff700000
 
-/* RAW SD card / eMMC locations. */
-
 #define CFG_SYS_SDRAM_BASE		0
-#define SDRAM_BANK_SIZE			(2UL << 30)
 #define SDRAM_MAX_SIZE			0xfe000000
 
 #define ENV_MEM_LAYOUT_SETTINGS \
diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index 55a0dfe..ba9ee11 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -12,7 +12,6 @@
 
 #define CFG_SYS_SDRAM_BASE		0
 #define SDRAM_MAX_SIZE			0xff000000
-#define SDRAM_BANK_SIZE			(2UL << 30)
 
 #define ENV_MEM_LAYOUT_SETTINGS \
 	"scriptaddr=0x00500000\0" \
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index 24b21c0..e565ccf 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -10,7 +10,6 @@
 
 #define CFG_IRAM_BASE		0xff090000
 
-/* FAT sd card locations. */
 #define CFG_SYS_SDRAM_BASE		0
 #define SDRAM_MAX_SIZE			0xff000000
 
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 3ef9ffa..04dcbf2 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -10,7 +10,6 @@
 
 #define CFG_IRAM_BASE		0xff8c0000
 
-/* FAT sd card locations. */
 #define CFG_SYS_SDRAM_BASE		0
 #define SDRAM_MAX_SIZE			0xf8000000
 
diff --git a/include/configs/roc-pc-rk3399.h b/include/configs/roc-pc-rk3399.h
index 59fe222..f99871c 100644
--- a/include/configs/roc-pc-rk3399.h
+++ b/include/configs/roc-pc-rk3399.h
@@ -13,6 +13,4 @@
 
 #include <configs/rk3399_common.h>
 
-#define SDRAM_BANK_SIZE			(2UL << 30)
-
 #endif
diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h
index 6099d2f..b859781 100644
--- a/include/configs/rock960_rk3399.h
+++ b/include/configs/rock960_rk3399.h
@@ -13,5 +13,4 @@
 
 #include <configs/rk3399_common.h>
 
-#define SDRAM_BANK_SIZE			(2UL << 30)
 #endif
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
index b7c5c66..18544d7 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -11,8 +11,6 @@
 #define CFG_CPUID_OFFSET	0x7
 #endif
 
-/* ((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512) */
-
 #ifndef CONFIG_SPL_BUILD
 
 /* First try to boot from SD (index 1), then eMMC (index 0) */
diff --git a/include/configs/rockpro64_rk3399.h b/include/configs/rockpro64_rk3399.h
index 9195b9b..5381efa 100644
--- a/include/configs/rockpro64_rk3399.h
+++ b/include/configs/rockpro64_rk3399.h
@@ -13,5 +13,4 @@
 
 #include <configs/rk3399_common.h>
 
-#define SDRAM_BANK_SIZE			(2UL << 30)
 #endif
diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index 63551b4..050d37b 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -17,8 +17,6 @@
 
 #define CFG_SYS_SDRAM_BASE		0x60000000
 
-/* rockchip ohci host driver */
-
 #define ENV_MEM_LAYOUT_SETTINGS \
 	"scriptaddr=0x60000000\0" \
 	"fdt_addr_r=0x61f00000\0" \
diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
index 19589be..05de376 100644
--- a/include/configs/stmark2.h
+++ b/include/configs/stmark2.h
@@ -95,4 +95,6 @@
 #define CACR_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
 					CFG_SYS_INIT_RAM_SIZE - 12)
 
+#define CFG_MCFTMR
+
 #endif /* __STMARK2_CONFIG_H */
diff --git a/include/configs/tinker_rk3288.h b/include/configs/tinker_rk3288.h
index 269ec52..053c903 100644
--- a/include/configs/tinker_rk3288.h
+++ b/include/configs/tinker_rk3288.h
@@ -13,13 +13,4 @@
 
 #include <configs/rk3288_common.h>
 
-#undef BOOT_TARGET_DEVICES
-
-#define BOOT_TARGET_DEVICES(func) \
-	func(MMC, mmc, 0) \
-	func(MMC, mmc, 1) \
-	func(USB, usb, 0) \
-	func(PXE, pxe, na) \
-	func(DHCP, dchp, na)
-
 #endif
diff --git a/include/configs/vyasa-rk3288.h b/include/configs/vyasa-rk3288.h
index e8c1013..81ff61b 100644
--- a/include/configs/vyasa-rk3288.h
+++ b/include/configs/vyasa-rk3288.h
@@ -20,10 +20,4 @@
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 1) \
 
-#ifndef CONFIG_TPL_BUILD
-/* Falcon Mode */
-
-/* Falcon Mode - MMC support: args@16MB kernel@17MB */
-#endif
-
 #endif
diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
index f5ac155..d757076 100644
--- a/include/dt-bindings/clock/suniv-ccu-f1c100s.h
+++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
@@ -67,4 +67,6 @@
 #define CLK_CODEC		65
 #define CLK_AVS			66
 
+#define CLK_IR			67
+
 #endif