diff options
author | Tom Rini <trini@konsulko.com> | 2023-03-20 17:52:42 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2023-03-20 17:52:42 -0400 |
commit | 51321493ebf029a9c3b33c02104f20fd5cb3a9be (patch) | |
tree | f8e216759f6005bc9f2715232897cf1cd319fff4 | |
parent | 318af47668aa2347ca9bbf2114cb9af1d8739aca (diff) | |
parent | d35a1392c5d17e067d16b7b096565b16af495f34 (diff) | |
download | u-boot-WIP/20Mar2023.zip u-boot-WIP/20Mar2023.tar.gz u-boot-WIP/20Mar2023.tar.bz2 |
Merge tag 'u-boot-rockchip-20230319' of https://source.denx.de/u-boot/custodians/u-boot-rockchipWIP/20Mar2023
- Fix for rockchip timer driver;
- Fix for rk3568 and rk3588 boot device and clock driver;
- Fix for rk3568 reset handler;
- Fix for rk3568 sdhci DLL at 52MHz;
35 files changed, 304 insertions, 91 deletions
diff --git a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi index 9c9016d..de29959 100644 --- a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi +++ b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi @@ -52,7 +52,6 @@ }; &timer3 { - compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; clock-frequency = <24000000>; u-boot,dm-spl; }; diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi index a27a3ad..27735c4 100644 --- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi @@ -11,7 +11,7 @@ }; &uart0 { - bootph-all; + u-boot,dm-pre-reloc; clock-frequency = <24000000>; status = "okay"; }; diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi index 4e79173..5893325 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -13,6 +13,6 @@ &uart2 { clock-frequency = <24000000>; - bootph-all; + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index ed47efa..04bbb01 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -9,16 +9,20 @@ / { chosen { stdout-path = &uart2; - u-boot,spl-boot-order = "same-as-spl", &sdmmc0; + u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; }; }; -&sdmmc0 { - status = "okay"; +&sdmmc2 { + status = "disabled"; +}; + +&uart1 { + status = "disabled"; }; &uart2 { clock-frequency = <24000000>; - bootph-all; + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts index a2f2baa..917f5b2 100644 --- a/arch/arm/dts/rk3568-rock-3a.dts +++ b/arch/arm/dts/rk3568-rock-3a.dts @@ -1,22 +1,37 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2023 Akash Gajjar <gajjar04akash@gmail.com> - */ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "rk3568.dtsi" / { model = "Radxa ROCK3 Model A"; compatible = "radxa,rock3a", "rockchip,rk3568"; + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + chosen: chosen { stdout-path = "serial2:1500000n8"; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + gmac1_clkin: external-gmac1-clock { compatible = "fixed-clock"; clock-frequency = <125000000>; @@ -24,13 +39,93 @@ #clock-cells = <0>; }; + leds { + compatible = "gpio-leds"; + + led_user: led-0 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_user_en>; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + }; + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* pi6c pcie clock generator */ + vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pi6c_03"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; }; vcc3v3_sys: vcc3v3-sys-regulator { @@ -91,6 +186,7 @@ enable-active-high; gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; regulator-name = "vcc5v0_usb_otg"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -164,7 +260,43 @@ clock_in_out = "input"; phy-handle = <&rgmii_phy1>; phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_clkinout + &gmac1m1_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; pinctrl-names = "default"; + pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm1_cec>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { status = "okay"; }; @@ -441,6 +573,13 @@ }; &i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&i2s2_2ch { rockchip,trcm-sync-tx-only; status = "okay"; }; @@ -457,6 +596,27 @@ }; }; +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie30phy { + phy-supply = <&vcc3v3_pi6c_03>; + status = "okay"; +}; + +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2m1_pins>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + &pinctrl { cam { vcc_cam_en: vcc_cam_en { @@ -551,6 +711,78 @@ status = "okay"; }; +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc2 { + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + /* vddio comes from regulator on module, use IO bank voltage instead */ + }; +}; + &uart2 { status = "okay"; }; @@ -607,3 +839,20 @@ phy-supply = <&vcc5v0_usb_host>; status = "okay"; }; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 2331641..6eef99e 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -12,7 +12,7 @@ }; chosen { - u-boot,spl-boot-order = &sdhci, &sdmmc0; + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc0; }; dmc: dmc { @@ -34,11 +34,6 @@ }; }; -&combphy1 { - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-rates; -}; - &cru { u-boot,dm-pre-reloc; status = "okay"; diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi index 3235bd3..6129664 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi +++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi @@ -18,7 +18,7 @@ &sdmmc { bus-width = <4>; - bootph-all; + u-boot,dm-pre-reloc; u-boot,spl-fifo-mode; status = "okay"; }; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 1e225d7..f880f4a 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -8,12 +8,12 @@ / { dmc { compatible = "rockchip,rk3588-dmc"; - bootph-all; + u-boot,dm-pre-reloc; status = "okay"; }; pmu1_grf: syscon@fd58a000 { - bootph-all; + u-boot,dm-pre-reloc; compatible = "rockchip,rk3588-pmu1-grf", "syscon"; reg = <0x0 0xfd58a000 0x0 0x2000>; }; @@ -46,26 +46,26 @@ }; &xin24m { - bootph-all; + u-boot,dm-pre-reloc; status = "okay"; }; &cru { - bootph-pre-ram; + u-boot,dm-spl; status = "okay"; }; &sys_grf { - bootph-pre-ram; + u-boot,dm-spl; status = "okay"; }; &uart2 { clock-frequency = <24000000>; - bootph-pre-ram; + u-boot,dm-spl; status = "okay"; }; &ioc { - bootph-pre-ram; + u-boot,dm-spl; }; diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 4a08820a..69ef19c 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -82,7 +82,7 @@ static struct mm_region rk3568_mem_map[] = { }; const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000", + [BROM_BOOTSOURCE_EMMC] = "/mmc@fe310000", [BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000", }; diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index 2ee1db4..18e67b5 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -8,6 +8,7 @@ #include <spl.h> #include <asm/armv8/mmu.h> #include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/ioc_rk3588.h> @@ -36,6 +37,12 @@ DECLARE_GLOBAL_DATA_PTR; #define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c #define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60 +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e0000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b0000/flash@0", + [BROM_BOOTSOURCE_SD] = "/mmc@fe2c0000", +}; + static struct mm_region rk3588_mem_map[] = { { .virt = 0x0UL, diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 99c195b..1c6adc5 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -14,6 +14,7 @@ #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/hardware.h> #include <asm/io.h> +#include <dm/device-internal.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3568-cru.h> @@ -424,6 +425,9 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate) case PCLK_PMU: ret = rk3568_pmu_set_pmuclk(priv, rate); break; + case CLK_PCIEPHY0_REF: + case CLK_PCIEPHY1_REF: + return 0; default: return -ENOENT; } @@ -2937,6 +2941,7 @@ static int rk3568_clk_bind(struct udevice *dev) glb_srst_fst); priv->glb_srst_snd_value = offsetof(struct rk3568_cru, glb_srsr_snd); + dev_set_priv(sys_child, priv); } #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 5271d94..a7df553 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -1558,7 +1558,7 @@ static ulong rk3588_clk_get_rate(struct clk *clk) #ifndef CONFIG_SPL_BUILD case CLK_AUX16M_0: case CLK_AUX16M_1: - rk3588_aux16m_get_clk(priv, clk->id); + rate = rk3588_aux16m_get_clk(priv, clk->id); break; case ACLK_VOP_ROOT: case ACLK_VOP: @@ -1707,7 +1707,7 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate) #ifndef CONFIG_SPL_BUILD case CLK_AUX16M_0: case CLK_AUX16M_1: - rk3588_aux16m_set_clk(priv, clk->id, rate); + ret = rk3588_aux16m_set_clk(priv, clk->id, rate); break; case ACLK_VOP_ROOT: case ACLK_VOP: diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 3661ce3..72c820e 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -52,7 +52,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) ret = clk_set_rate(&priv->clk, freq); if (ret < 0) { debug("%s: err=%d\n", __func__, ret); - return ret; + return 0; } return freq; diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 9608770..e1409dd 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -61,6 +61,7 @@ #define DWCMSHC_EMMC_DLL_RXCLK 0x804 #define DWCMSHC_EMMC_DLL_TXCLK 0x808 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c +#define DECMSHC_EMMC_DLL_CMDOUT 0x810 #define DWCMSHC_EMMC_DLL_STATUS0 0x840 #define DWCMSHC_EMMC_DLL_STATUS1 0x844 #define DWCMSHC_EMMC_DLL_START BIT(0) @@ -69,6 +70,7 @@ #define DWCMSHC_EMMC_DLL_START_DEFAULT 5 #define DWCMSHC_EMMC_DLL_INC_VALUE 2 #define DWCMSHC_EMMC_DLL_INC 8 +#define DWCMSHC_EMMC_DLL_BYPASS BIT(24) #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) #define DLL_TXCLK_TAPNUM_DEFAULT 0xA @@ -83,6 +85,7 @@ #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) #define DLL_RXCLK_NO_INVERTER 1 #define DLL_RXCLK_INVERTER 0 +#define DLL_RXCLK_ORI_GATE BIT(31) #define DWCMSHC_ENHANCED_STROBE BIT(8) #define DLL_LOCK_WO_TMOUT(x) \ ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ @@ -348,10 +351,14 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo DLL_STRBIN_TAPNUM_FROM_SW; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); } else { - /* reset the clock phase when the frequency is lower than 100MHz */ - sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); - extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; - sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); + /* + * Disable DLL and reset both of sample and drive clock. + * The bypass bit and start bit need to be set if DLL is not locked. + */ + sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, + DWCMSHC_EMMC_DLL_CTRL); + sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK); + sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); /* * Before switching to hs400es mode, the driver will enable diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c index 62eacb9..e66c49a 100644 --- a/drivers/timer/rockchip_timer.c +++ b/drivers/timer/rockchip_timer.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rockchip_timer_plat { - struct dtd_rockchip_rk3368_timer dtd; + struct dtd_rockchip_rk3288_timer dtd; }; #endif @@ -152,14 +152,12 @@ static const struct timer_ops rockchip_timer_ops = { }; static const struct udevice_id rockchip_timer_ids[] = { - { .compatible = "rockchip,rk3188-timer" }, { .compatible = "rockchip,rk3288-timer" }, - { .compatible = "rockchip,rk3368-timer" }, {} }; -U_BOOT_DRIVER(rockchip_rk3368_timer) = { - .name = "rockchip_rk3368_timer", +U_BOOT_DRIVER(rockchip_rk3288_timer) = { + .name = "rockchip_rk3288_timer", .id = UCLASS_TIMER, .of_match = rockchip_timer_ids, .probe = rockchip_timer_probe, diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h index cac613d..d10e5b1 100644 --- a/include/configs/evb_rk3328.h +++ b/include/configs/evb_rk3328.h @@ -8,6 +8,4 @@ #include <configs/rk3328_common.h> -#define SDRAM_BANK_SIZE (2UL << 30) - #endif diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h index b7e8503..70ab587 100644 --- a/include/configs/evb_rk3399.h +++ b/include/configs/evb_rk3399.h @@ -13,6 +13,4 @@ #include <configs/rk3399_common.h> -#define SDRAM_BANK_SIZE (2UL << 30) - #endif diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h index 241dc39..141ffcd 100644 --- a/include/configs/pinebook-pro-rk3399.h +++ b/include/configs/pinebook-pro-rk3399.h @@ -14,6 +14,4 @@ #include <configs/rk3399_common.h> -#define SDRAM_BANK_SIZE (2UL << 30) - #endif diff --git a/include/configs/pinephone-pro-rk3399.h b/include/configs/pinephone-pro-rk3399.h index 78017d6..9cd4447 100644 --- a/include/configs/pinephone-pro-rk3399.h +++ b/include/configs/pinephone-pro-rk3399.h @@ -14,6 +14,4 @@ #include <configs/rk3399_common.h> -#define SDRAM_BANK_SIZE (2UL << 30) - #endif diff --git a/include/configs/puma_rk3399.h b/include/configs/puma_rk3399.h index 23de326..969acc8 100644 --- a/include/configs/puma_rk3399.h +++ b/include/configs/puma_rk3399.h @@ -8,6 +8,4 @@ #include <configs/rk3399_common.h> -#define SDRAM_BANK_SIZE (2UL << 30) - #endif diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index c0896e5..8df481b 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -15,7 +15,6 @@ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 -#define SDRAM_BANK_SIZE (2UL << 30) #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 8aa17bf..8736b14 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -12,13 +12,9 @@ #define CFG_IRAM_BASE 0x10080000 -/* RAW SD card / eMMC locations. */ - #define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_MAX_SIZE 0x80000000 -/* usb mass storage */ - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60500000\0" \ "pxefile_addr_r=0x60600000\0" \ diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index ac91956..fcb2745 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -11,15 +11,9 @@ #define CFG_IRAM_BASE 0x10080000 -/* spl size 32kb sram - 2kb bootrom */ - #define CFG_SYS_SDRAM_BASE 0x60000000 -#define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0x80000000 -/* usb otg */ - -/* usb host support */ #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "pxefile_addr_r=0x60100000\0" \ diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index fcaf9c5..39a40f4 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -13,7 +13,6 @@ #define CFG_IRAM_BASE 0x10080000 #define CFG_SYS_SDRAM_BASE 0x60000000 -#define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE 0x80000000 #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 5f29432..71d2426 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -13,10 +13,7 @@ #define CFG_IRAM_BASE 0xff700000 -/* RAW SD card / eMMC locations. */ - #define CFG_SYS_SDRAM_BASE 0 -#define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0xfe000000 #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 55a0dfe..ba9ee11 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -12,7 +12,6 @@ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 -#define SDRAM_BANK_SIZE (2UL << 30) #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 24b21c0..e565ccf 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -10,7 +10,6 @@ #define CFG_IRAM_BASE 0xff090000 -/* FAT sd card locations. */ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 3ef9ffa..04dcbf2 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -10,7 +10,6 @@ #define CFG_IRAM_BASE 0xff8c0000 -/* FAT sd card locations. */ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf8000000 diff --git a/include/configs/roc-pc-rk3399.h b/include/configs/roc-pc-rk3399.h index 59fe222..f99871c 100644 --- a/include/configs/roc-pc-rk3399.h +++ b/include/configs/roc-pc-rk3399.h @@ -13,6 +13,4 @@ #include <configs/rk3399_common.h> -#define SDRAM_BANK_SIZE (2UL << 30) - #endif diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h index 6099d2f..b859781 100644 --- a/include/configs/rock960_rk3399.h +++ b/include/configs/rock960_rk3399.h @@ -13,5 +13,4 @@ #include <configs/rk3399_common.h> -#define SDRAM_BANK_SIZE (2UL << 30) #endif diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index b7c5c66..18544d7 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -11,8 +11,6 @@ #define CFG_CPUID_OFFSET 0x7 #endif -/* ((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512) */ - #ifndef CONFIG_SPL_BUILD /* First try to boot from SD (index 1), then eMMC (index 0) */ diff --git a/include/configs/rockpro64_rk3399.h b/include/configs/rockpro64_rk3399.h index 9195b9b..5381efa 100644 --- a/include/configs/rockpro64_rk3399.h +++ b/include/configs/rockpro64_rk3399.h @@ -13,5 +13,4 @@ #include <configs/rk3399_common.h> -#define SDRAM_BANK_SIZE (2UL << 30) #endif diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 63551b4..050d37b 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -17,8 +17,6 @@ #define CFG_SYS_SDRAM_BASE 0x60000000 -/* rockchip ohci host driver */ - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x60000000\0" \ "fdt_addr_r=0x61f00000\0" \ diff --git a/include/configs/tinker_rk3288.h b/include/configs/tinker_rk3288.h index 269ec52..053c903 100644 --- a/include/configs/tinker_rk3288.h +++ b/include/configs/tinker_rk3288.h @@ -13,13 +13,4 @@ #include <configs/rk3288_common.h> -#undef BOOT_TARGET_DEVICES - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dchp, na) - #endif diff --git a/include/configs/vyasa-rk3288.h b/include/configs/vyasa-rk3288.h index e8c1013..81ff61b 100644 --- a/include/configs/vyasa-rk3288.h +++ b/include/configs/vyasa-rk3288.h @@ -20,10 +20,4 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ -#ifndef CONFIG_TPL_BUILD -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@16MB kernel@17MB */ -#endif - #endif |