diff options
| author | Fabio Estevam <festevam@gmail.com> | 2019-07-12 09:10:35 -0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-10-08 16:35:59 +0200 |
| commit | b8bffab76fcde37fba3a2d4afcb8dbaa7c5c08d8 (patch) | |
| tree | 77abbd9ff1aabce0acf610adb30627b7facf2387 | |
| parent | 033f6ea5fa5fce63d52c8c2b63d8284144415b88 (diff) | |
| download | u-boot-b8bffab76fcde37fba3a2d4afcb8dbaa7c5c08d8.zip u-boot-b8bffab76fcde37fba3a2d4afcb8dbaa7c5c08d8.tar.gz u-boot-b8bffab76fcde37fba3a2d4afcb8dbaa7c5c08d8.tar.bz2 | |
mx6: clock: Allow enable_ipu_clock() to be built for SPL code
Allow enable_ipu_clock() to be built for SPL code. This is done
in preparation for configuring the NoC registers on i.MX6QP in SPL.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| -rw-r--r-- | arch/arm/mach-imx/mx6/clock.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 366a4e3..5af1ae7 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1275,6 +1275,22 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return 0; } +#ifndef CONFIG_MX6SX +void enable_ipu_clock(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; + writel(reg, &mxc_ccm->CCGR3); + + if (is_mx6dqp()) { + setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); + } +} +#endif + #ifndef CONFIG_SPL_BUILD /* * Dump some core clockes. @@ -1311,22 +1327,6 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -#ifndef CONFIG_MX6SX -void enable_ipu_clock(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - int reg; - reg = readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; - writel(reg, &mxc_ccm->CCGR3); - - if (is_mx6dqp()) { - setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); - setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); - } -} -#endif - #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \ defined(CONFIG_MX6S) static void disable_ldb_di_clock_sources(void) |