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| author | Reid Tonking <reidt@ti.com> | 2023-12-07 10:52:11 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-12-19 10:15:54 -0500 |
| commit | 3d6cb0390557b7cbc90c5e548072f3c3497f3873 (patch) | |
| tree | 6f5523f4f65adeaffc2fcfdc8ff0cd797e7032e6 | |
| parent | 9fc5e19c2e6f9cc71c66faea67accaf77f0c13e8 (diff) | |
| download | u-boot-3d6cb0390557b7cbc90c5e548072f3c3497f3873.zip u-boot-3d6cb0390557b7cbc90c5e548072f3c3497f3873.tar.gz u-boot-3d6cb0390557b7cbc90c5e548072f3c3497f3873.tar.bz2 | |
arm: dts: k3-j7200-r5-common-proc-board: Set parent clock for clock ID 323
Previously, dynamic frequency scaling supported rates only through fixed
divison.
This virtual clock mux configuration enables more varied rates on A72
clock ID 202 by setting up the required register.
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
| -rw-r--r-- | arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index f0a7360..018faaa 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -24,7 +24,8 @@ <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; + assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>; + assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>; assigned-clock-rates = <2000000000>, <200000000>; ti,sci = <&dmsc>; ti,sci-proc-id = <32>; |