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| author | Andre Przywara <andre.przywara@arm.com> | 2021-04-12 01:04:51 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-04-20 07:31:12 -0400 |
| commit | 109552d773e7aeb0f6417d8245fb0ecf01599ef3 (patch) | |
| tree | 010a7fe67a4d74cd576341a854ff299d449c890a | |
| parent | 84b2cd74f370dabb707e2611bf57714a66d08622 (diff) | |
| download | u-boot-109552d773e7aeb0f6417d8245fb0ecf01599ef3.zip u-boot-109552d773e7aeb0f6417d8245fb0ecf01599ef3.tar.gz u-boot-109552d773e7aeb0f6417d8245fb0ecf01599ef3.tar.bz2 | |
arm: highbank: Enable OF_CONTROL
All Calxeda machines are actually a poster book example of device tree
usage: the DT is loaded from flash by the management processor into
DRAM, the memory node is populated with the detected DRAM size and this
DT is then handed over to the kernel.
So it's a shame that U-Boot didn't participate in this chain, but
fortunately this is easy to fix:
Define CONFIG_OF_CONTROL and CONFIG_OF_BOARD, and provide a trivial
function to tell U-Boot about the (fixed) location of the DTB in DRAM.
Then enable DM_SERIAL, to let the PL011 driver pick up the UART platform
data from the DT. Also define AHCI, to bring this driver into the driver
model world as well.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| -rw-r--r-- | arch/arm/Kconfig | 9 | ||||
| -rw-r--r-- | board/highbank/highbank.c | 10 | ||||
| -rw-r--r-- | configs/highbank_defconfig | 1 | ||||
| -rw-r--r-- | include/configs/highbank.h | 1 |
4 files changed, 19 insertions, 2 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 15b8454..3586426 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -711,7 +711,14 @@ config ARCH_S5PC1XX config ARCH_HIGHBANK bool "Calxeda Highbank" select CPU_V7A - select PL011_SERIAL + select PL01X_SERIAL + select DM + select DM_SERIAL + select OF_CONTROL + select OF_BOARD + select CLK + select CLK_CCF + select AHCI config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 906bd9b..2e2300a 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -119,6 +119,16 @@ int ft_board_setup(void *fdt, struct bd_info *bd) } #endif +void *board_fdt_blob_setup(void) +{ + /* + * The ECME management processor loads the DTB from NOR flash + * into DRAM (at 4KB), where it gets patched to contain the + * detected memory size. + */ + return (void *)0x1000; +} + static int is_highbank(void) { uint32_t midr; diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig index 369b65c..773ed7a 100644 --- a/configs/highbank_defconfig +++ b/configs/highbank_defconfig @@ -26,3 +26,4 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SCSI=y CONFIG_CONS_INDEX=0 CONFIG_OF_LIBFDT=y +CONFIG_OF_BOARD=y diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 5e3cc3a..7f37c81 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -18,7 +18,6 @@ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) #define CONFIG_PL011_CLOCK 150000000 -#define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) } #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ |