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| author | Marek Vasut <marex@denx.de> | 2024-01-19 17:07:54 +0100 |
|---|---|---|
| committer | Fabio Estevam <festevam@gmail.com> | 2024-01-22 08:38:48 -0300 |
| commit | 4dd80cb09ec333035a0cb812cae123dac568807c (patch) | |
| tree | 7865be0c53bbe5493463813a6347ac959bd7d589 | |
| parent | f8cebb4f789c9950caf55a0b73e88049e7a1c3a3 (diff) | |
| download | u-boot-4dd80cb09ec333035a0cb812cae123dac568807c.zip u-boot-4dd80cb09ec333035a0cb812cae123dac568807c.tar.gz u-boot-4dd80cb09ec333035a0cb812cae123dac568807c.tar.bz2 | |
ARM: imx: Enable SPL_BOARD_INIT on DH i.MX8M Plus DHCOM
The CONFIG_SPL_BOARD_INIT lets SPL common code call spl_board_init()
during the SPL start up. On this particular system, spl_board_init()
is used to reconfigure GIC clock parent to PLL2 500M, which is the
configuration expected by the Linux kernel. Enable SPL_BOARD_INIT .
Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not
allow to change it. Should set the clock after PMIC setting done.
Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for
ND VDD_SOC.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
| -rw-r--r-- | configs/imx8mp_dhcom_pdk2_defconfig | 1 | ||||
| -rw-r--r-- | configs/imx8mp_dhcom_pdk3_defconfig | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index 73e8421..cae5375 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -57,6 +57,7 @@ CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x96fc00 CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig index a3966fb..78f7b96 100644 --- a/configs/imx8mp_dhcom_pdk3_defconfig +++ b/configs/imx8mp_dhcom_pdk3_defconfig @@ -58,6 +58,7 @@ CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x96fc00 CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set |