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| author | Kever Yang <kever.yang@rock-chips.com> | 2017-04-20 17:03:46 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2017-05-10 13:37:21 -0600 |
| commit | fa1392a236dfebbe938a48f124c8332759aba8e5 (patch) | |
| tree | 20d3cfb0e657add5e6e97a1329249b9b884c1739 | |
| parent | 602778d3c7ea367bb55f73ec33e8ef8c2c1dcb12 (diff) | |
| download | u-boot-fa1392a236dfebbe938a48f124c8332759aba8e5.zip u-boot-fa1392a236dfebbe938a48f124c8332759aba8e5.tar.gz u-boot-fa1392a236dfebbe938a48f124c8332759aba8e5.tar.bz2 | |
rockchip: reserve memory for rk3399 ATF data
There are 3 regions used by rk3399 ATF:
- bl31 code, located at 0x10000;
- cortex-m0 code and data, located at 0xff8c0000;
- bl31 data, located at 0xff8c1000 ~ 0xff8c4000;
SPL_TEXT_BASE starts from 0xff8c2000, we need to reserve memory
for ATF data, or else there will be memory corrupt after SPL
loads the ATF image.
More detail about cortex-M0 code in ATF:
https://github.com/ARM-software/arm-trusted-firmware/commit/
8382e17c4c6bffd15119dfce1ee4372e3c1a7890
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/boot0.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/Kconfig | 8 |
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h index 8d7bc9a..7346876 100644 --- a/arch/arm/include/asm/arch-rockchip/boot0.h +++ b/arch/arm/include/asm/arch-rockchip/boot0.h @@ -16,3 +16,7 @@ .space 0x4 /* space for the 'RK33' */ #endif b reset + +#if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD) + .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */ +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 2b752ad..740dbdf 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -74,6 +74,14 @@ config ROCKCHIP_SPL_BACK_TO_BROM SPL will return to the boot rom, which will then load the U-Boot binary to keep going on. +config ROCKCHIP_SPL_RESERVE_IRAM + hex "Size of IRAM reserved in SPL" + default 0x4000 + help + SPL may need reserve memory for firmware loaded by SPL, whose load + address is in IRAM and may overlay with SPL text area if not + reserved. + config ROCKCHIP_BROM_HELPER bool |