Merge tag 'u-boot-rockchip-20190729' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

- Clean up and migrate to use common rockchip spl board file
- Clean up and migrate to use common rockchip board file
- Increase rk3288 CONFIG_SYS_BOOTM_LEN to 16MB

57 files changed, 978 insertions, 1913 deletions

diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts b/arch/arm/dts/rk3288-phycore-rdk.dts
index f2bb7b5..cc39210 100644
--- a/arch/arm/dts/rk3288-phycore-rdk.dts
+++ b/arch/arm/dts/rk3288-phycore-rdk.dts
@@ -55,11 +55,6 @@
 		stdout-path = &uart2;
 	};
 
-	config {
-		u-boot,dm-pre-reloc;
-		u-boot,boot0 = &emmc;
-	};
-
 	user_buttons: user-buttons {
 		compatible = "gpio-keys";
 		pinctrl-names = "default";
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index 916dd48..8754043 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -16,11 +16,7 @@
 
 	chosen {
 		stdout-path = &uart2;
-	};
-
-	config {
-		u-boot,dm-pre-reloc;
-		u-boot,boot0 = &spi_flash;
+		u-boot,spl-boot-order = &spi_flash;
 	};
 
 	firmware {
diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h
index d67f43f..0da78f3 100644
--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -52,9 +52,11 @@ enum {
 	BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB
 };
 
+extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1];
+
 /**
  * Locations of the boot-device identifier in SRAM
  */
-#define RK3399_BROM_BOOTSOURCE_ID_ADDR   0xff8c0010
+#define BROM_BOOTSOURCE_ID_ADDR   (CONFIG_IRAM_BASE + 0x10)
 
 #endif
diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h
index 905c774..de5a8f1 100644
--- a/arch/arm/include/asm/arch-rockchip/sys_proto.h
+++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h
@@ -6,8 +6,4 @@
 #ifndef _ASM_ARCH_SYS_PROTO_H
 #define _ASM_ARCH_SYS_PROTO_H
 
-
-/* provided to defeat compiler optimisation in board_init_f() */
-void gru_dummy_function(int i);
-
 #endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 17f31e8..e337d06 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -7,6 +7,7 @@ config ROCKCHIP_RK3036
 	select SPL
 	imply USB_FUNCTION_ROCKUSB
 	imply CMD_ROCKUSB
+	imply ROCKCHIP_COMMON_BOARD
 	help
 	  The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
 	  including NEON and GPU, Mali-400 graphics, several DDR3 options
@@ -16,6 +17,7 @@ config ROCKCHIP_RK3036
 config ROCKCHIP_RK3128
 	bool "Support Rockchip RK3128"
 	select CPU_V7A
+	imply ROCKCHIP_COMMON_BOARD
 	help
 	  The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
 	  including NEON and GPU, Mali-400 graphics, several DDR3 options
@@ -34,8 +36,10 @@ config ROCKCHIP_RK3188
 	select SPL_RAM
 	select SPL_DRIVERS_MISC_SUPPORT
 	select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
+	select SPL_ROCKCHIP_BACK_TO_BROM
 	select BOARD_LATE_INIT
-	select ROCKCHIP_BROM_HELPER
+	imply ROCKCHIP_COMMON_BOARD
+	imply SPL_ROCKCHIP_COMMON_BOARD
 	help
 	  The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
 	  including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
@@ -57,11 +61,11 @@ config ROCKCHIP_RK322X
 	select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
 	select TPL_NEEDS_SEPARATE_STACK if TPL
 	select SPL_DRIVERS_MISC_SUPPORT
+	imply ROCKCHIP_COMMON_BOARD
 	imply SPL_SERIAL_SUPPORT
+	imply SPL_ROCKCHIP_COMMON_BOARD
 	imply TPL_SERIAL_SUPPORT
-	imply TPL_BOOTROM_SUPPORT
 	imply TPL_ROCKCHIP_COMMON_BOARD
-	select ROCKCHIP_BROM_HELPER
 	select TPL_LIBCOMMON_SUPPORT
 	select TPL_LIBGENERIC_SUPPORT
 	help
@@ -73,11 +77,11 @@ config ROCKCHIP_RK322X
 config ROCKCHIP_RK3288
 	bool "Support Rockchip RK3288"
 	select CPU_V7A
-	select SPL_BOARD_INIT if SPL
 	select SUPPORT_SPL
 	select SPL
 	select SUPPORT_TPL
-	imply TPL_BOOTROM_SUPPORT
+	imply ROCKCHIP_COMMON_BOARD
+	imply SPL_ROCKCHIP_COMMON_BOARD
 	imply TPL_CLK
 	imply TPL_DM
 	imply TPL_DRIVERS_MISC_SUPPORT
@@ -106,6 +110,8 @@ config ROCKCHIP_RK3328
 	select ARM64
 	select SUPPORT_SPL
 	select SPL
+	imply ROCKCHIP_COMMON_BOARD
+	imply SPL_ROCKCHIP_COMMON_BOARD
 	imply SPL_SERIAL_SUPPORT
 	imply SPL_SEPARATE_BSS
 	select ENABLE_ARM_SOC_BOOT0_HOOK
@@ -125,6 +131,8 @@ config ROCKCHIP_RK3368
 	select SUPPORT_TPL
 	select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
 	select TPL_NEEDS_SEPARATE_STACK if TPL
+	imply ROCKCHIP_COMMON_BOARD
+	imply SPL_ROCKCHIP_COMMON_BOARD
 	imply SPL_SEPARATE_BSS
 	imply SPL_SERIAL_SUPPORT
 	imply TPL_SERIAL_SUPPORT
@@ -169,12 +177,12 @@ config ROCKCHIP_RK3399
 	select DM_PMIC
 	select DM_REGULATOR_FIXED
 	select BOARD_LATE_INIT
-	select ROCKCHIP_BROM_HELPER
+	imply ROCKCHIP_COMMON_BOARD
+	imply SPL_ROCKCHIP_COMMON_BOARD
 	imply TPL_SERIAL_SUPPORT
 	imply TPL_LIBCOMMON_SUPPORT
 	imply TPL_LIBGENERIC_SUPPORT
 	imply TPL_SYS_MALLOC_SIMPLE
-	imply TPL_BOOTROM_SUPPORT
 	imply TPL_DRIVERS_MISC_SUPPORT
 	imply TPL_OF_CONTROL
 	imply TPL_DM
@@ -195,6 +203,7 @@ config ROCKCHIP_RK3399
 config ROCKCHIP_RV1108
 	bool "Support Rockchip RV1108"
 	select CPU_V7A
+	imply ROCKCHIP_COMMON_BOARD
 	help
 	  The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
 	  and a DSP.
@@ -211,6 +220,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM
 	bool "SPL returns to bootrom"
 	default y if ROCKCHIP_RK3036
 	select ROCKCHIP_BROM_HELPER
+	select SPL_BOOTROM_SUPPORT
 	depends on SPL
 	help
 	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
@@ -221,12 +231,28 @@ config TPL_ROCKCHIP_BACK_TO_BROM
 	bool "TPL returns to bootrom"
 	default y
 	select ROCKCHIP_BROM_HELPER
+	select TPL_BOOTROM_SUPPORT
 	depends on TPL
 	help
 	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
           SPL will return to the boot rom, which will then load the U-Boot
           binary to keep going on.
 
+config ROCKCHIP_COMMON_BOARD
+	bool "Rockchip common board file"
+	help
+	  Rockchip SoCs have similar boot process, Common board file is mainly
+	  in charge of common process of board_init() and board_late_init() for
+	  U-Boot proper.
+
+config SPL_ROCKCHIP_COMMON_BOARD
+	bool "Rockchip SPL common board file"
+	depends on SPL
+	help
+	  Rockchip SoCs have similar boot process, SPL is mainly in charge of
+	  load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
+	  no TPL for the board.
+
 config TPL_ROCKCHIP_COMMON_BOARD
 	bool ""
 	depends on TPL
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index a12b8d4..aed379a 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -7,16 +7,11 @@
 # inaccessible/protected memory (and the bootrom-helper assumes that
 # the stack-pointer is valid before switching to the U-Boot stack).
 obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
+obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o
 obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
 obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o
 
 obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o spl-boot-order.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3328) += rk3328-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
 
 ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 
@@ -25,14 +20,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 # we can have the preprocessor correctly recognise both 0x0 and 0
 # meaning "turn it off".
 obj-y += boot_mode.o
-
-obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
-obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o
-obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
-obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
-obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
-obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o
-obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108-board.o
+obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
 endif
 
 obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/board.c
index c594c4d..b2a88e7 100644
--- a/arch/arm/mach-rockchip/rk3036-board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -1,19 +1,17 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
  */
-
 #include <common.h>
 #include <clk.h>
 #include <dm.h>
 #include <ram.h>
-#include <asm/gpio.h>
+#include <syscon.h>
 #include <asm/io.h>
+#include <asm/arch-rockchip/boot_mode.h>
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/periph.h>
-#include <asm/arch-rockchip/grf_rk3036.h>
-#include <asm/arch-rockchip/boot_mode.h>
-#include <asm/arch-rockchip/sdram_rk3036.h>
+#include <power/regulator.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -31,23 +29,18 @@ int board_late_init(void)
 
 int board_init(void)
 {
-	return 0;
-}
+	int ret;
 
-#if !CONFIG_IS_ENABLED(RAM)
-/*
- * When CONFIG_RAM is enabled, the dram_init() function is implemented
- * in sdram_common.c.
- */
-int dram_init(void)
-{
-	gd->ram_size = sdram_size();
+#ifdef CONFIG_DM_REGULATOR
+	ret = regulators_enable_boot_on(false);
+	if (ret)
+		debug("%s: Cannot enable boot on regulator\n", __func__);
+#endif
 
 	return 0;
 }
-#endif
 
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
 void enable_caches(void)
 {
 	/* Enable D-cache. I-cache is already enabled in start.S */
@@ -59,7 +52,7 @@ void enable_caches(void)
 #include <usb.h>
 #include <usb/dwc2_udc.h>
 
-static struct dwc2_plat_otg_data rk3036_otg_data = {
+static struct dwc2_plat_otg_data otg_data = {
 	.rx_fifo_sz	= 512,
 	.np_tx_fifo_sz	= 16,
 	.tx_fifo_sz	= 128,
@@ -73,8 +66,7 @@ int board_usb_init(int index, enum usb_init_type init)
 	const void *blob = gd->fdt_blob;
 
 	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3288-usb");
+	node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
 
 	while (node > 0) {
 		mode = fdt_getprop(blob, node, "dr_mode", NULL);
@@ -83,16 +75,15 @@ int board_usb_init(int index, enum usb_init_type init)
 			break;
 		}
 
-		node = fdt_node_offset_by_compatible(blob, node,
-					"rockchip,rk3288-usb");
+		node = fdt_node_offset_by_compatible(blob, node, "snps,dwc2");
 	}
 	if (!matched) {
 		debug("Not found usb_otg device\n");
 		return -ENODEV;
 	}
-	rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+	otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
 
-	return dwc2_udc_probe(&rk3036_otg_data);
+	return dwc2_udc_probe(&otg_data);
 }
 
 int board_usb_cleanup(int index, enum usb_init_type init)
@@ -100,3 +91,14 @@ int board_usb_cleanup(int index, enum usb_init_type init)
 	return 0;
 }
 #endif
+
+#if CONFIG_IS_ENABLED(FASTBOOT)
+int fastboot_set_reboot_flag(void)
+{
+	printf("Setting reboot to fastboot flag ...\n");
+	/* Set boot mode to fastboot */
+	writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/mach-rockchip/fit_spl_optee.its b/arch/arm/mach-rockchip/fit_spl_optee.its
index 9be4b3c..6ed5d48 100644
--- a/arch/arm/mach-rockchip/fit_spl_optee.its
+++ b/arch/arm/mach-rockchip/fit_spl_optee.its
@@ -11,7 +11,7 @@
 	#address-cells = <1>;
 
 	images {
-		uboot@1 {
+		uboot {
 			description = "U-Boot";
 			data = /incbin/("../../../u-boot-nodtb.bin");
 			type = "standalone";
@@ -20,7 +20,7 @@
 			compression = "none";
 			load = <0x61000000>;
 		};
-		optee@1 {
+		optee {
 			description = "OP-TEE";
 			data = /incbin/("../../../tee.bin");
 			type = "firmware";
@@ -30,7 +30,7 @@
 			load = <0x68400000>;
 			entry = <0x68400000>;
 		};
-		fdt@1 {
+		fdt {
 			description = "dtb";
 			data = /incbin/("../../../u-boot.dtb");
 			type = "flat_dt";
@@ -39,12 +39,12 @@
 	};
 
 	configurations {
-		default = "conf@1";
-		conf@1 {
+		default = "conf";
+		conf {
 			description = "Rockchip armv7 with OP-TEE";
-			firmware = "optee@1";
-			loadables = "uboot@1";
-			fdt = "fdt@1";
+			firmware = "optee";
+			loadables = "uboot";
+			fdt = "fdt";
 		};
 	};
 };
diff --git a/arch/arm/mach-rockchip/rk3036/rk3036.c b/arch/arm/mach-rockchip/rk3036/rk3036.c
index 481af8a..be458cf 100644
--- a/arch/arm/mach-rockchip/rk3036/rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/rk3036.c
@@ -5,6 +5,9 @@
 #include <asm/io.h>
 #include <asm/arch-rockchip/grf_rk3036.h>
 #include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/sdram_rk3036.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 void board_debug_uart_init(void)
@@ -36,3 +39,16 @@ void board_debug_uart_init(void)
 		     GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
 }
 #endif
+
+#if !CONFIG_IS_ENABLED(RAM)
+/*
+ * When CONFIG_RAM is enabled, the dram_init() function is implemented
+ * in sdram_common.c.
+ */
+int dram_init(void)
+{
+	gd->ram_size = sdram_size();
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c
deleted file mode 100644
index 0945829..0000000
--- a/arch/arm/mach-rockchip/rk3128-board.c
+++ /dev/null
@@ -1,123 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
- */
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/periph.h>
-#include <asm/arch-rockchip/grf_rk3128.h>
-#include <asm/arch-rockchip/boot_mode.h>
-#include <power/regulator.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
-	return 0;
-}
-
-int board_late_init(void)
-{
-	setup_boot_mode();
-
-	return rk_board_late_init();
-}
-
-int board_init(void)
-{
-	int ret = 0;
-
-	ret = regulators_enable_boot_on(false);
-	if (ret) {
-		debug("%s: Cannot enable boot on regulator\n", __func__);
-		return ret;
-	}
-
-	return 0;
-}
-
-int dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = 0x8400000;
-	/* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */
-	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
-				+ gd->bd->bi_dram[0].size + 0xe00000;
-	gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
-				+ gd->ram_size - gd->bd->bi_dram[1].start;
-
-	return 0;
-}
-
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3128_otg_data = {
-	.rx_fifo_sz	= 512,
-	.np_tx_fifo_sz	= 16,
-	.tx_fifo_sz	= 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	int node;
-	const char *mode;
-	bool matched = false;
-	const void *blob = gd->fdt_blob;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					     "rockchip,rk3128-usb");
-
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-						     "rockchip,rk3128-usb");
-	}
-	if (!matched) {
-		debug("Not found usb_otg device\n");
-		return -ENODEV;
-	}
-	rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-	return dwc2_udc_probe(&rk3128_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return 0;
-}
-#endif
-
-#if CONFIG_IS_ENABLED(FASTBOOT)
-int fastboot_set_reboot_flag(void)
-{
-	struct rk3128_grf *grf;
-
-	printf("Setting reboot to fastboot flag ...\n");
-	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-	/* Set boot mode to fastboot */
-	writel(BOOT_FASTBOOT, &grf->os_reg[0]);
-
-	return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3128/rk3128.c b/arch/arm/mach-rockchip/rk3128/rk3128.c
index 11bba14..ee176de 100644
--- a/arch/arm/mach-rockchip/rk3128/rk3128.c
+++ b/arch/arm/mach-rockchip/rk3128/rk3128.c
@@ -2,6 +2,9 @@
 /*
  * Copyright (c) 2017 Rockchip Electronics Co., Ltd
  */
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 int arch_cpu_init(void)
 {
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c
deleted file mode 100644
index c3efe0d..0000000
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ /dev/null
@@ -1,193 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Google, Inc
- */
-
-#include <clk.h>
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <led.h>
-#include <malloc.h>
-#include <ram.h>
-#include <spl.h>
-#include <syscon.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/grf_rk3188.h>
-#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch-rockchip/periph.h>
-#include <asm/arch-rockchip/pmu_rk3188.h>
-#include <asm/arch-rockchip/sdram.h>
-#include <dm/root.h>
-#include <dm/test.h>
-#include <dm/util.h>
-#include <power/regulator.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 spl_boot_device(void)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-	const void *blob = gd->fdt_blob;
-	struct udevice *dev;
-	const char *bootdev;
-	int node;
-	int ret;
-
-	bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
-	debug("Boot device %s\n", bootdev);
-	if (!bootdev)
-		goto fallback;
-
-	node = fdt_path_offset(blob, bootdev);
-	if (node < 0) {
-		debug("node=%d\n", node);
-		goto fallback;
-	}
-	ret = device_get_global_by_ofnode(offset_to_ofnode(node), &dev);
-	if (ret) {
-		debug("device at node %s/%d not found: %d\n", bootdev, node,
-		      ret);
-		goto fallback;
-	}
-	debug("Found device %s\n", dev->name);
-	switch (device_get_uclass_id(dev)) {
-	case UCLASS_SPI_FLASH:
-		return BOOT_DEVICE_SPI;
-	case UCLASS_MMC:
-		return BOOT_DEVICE_MMC1;
-	default:
-		debug("Booting from device uclass '%s' not supported\n",
-		      dev_get_uclass_name(dev));
-	}
-
-fallback:
-#endif
-	return BOOT_DEVICE_MMC1;
-}
-
-static int setup_arm_clock(void)
-{
-	struct udevice *dev;
-	struct clk clk;
-	int ret;
-
-	ret = rockchip_get_clk(&dev);
-	if (ret)
-		return ret;
-
-	clk.id = CLK_ARM;
-	ret = clk_request(dev, &clk);
-	if (ret < 0)
-		return ret;
-
-	ret = clk_set_rate(&clk, 600000000);
-
-	clk_free(&clk);
-	return ret;
-}
-
-void board_init_f(ulong dummy)
-{
-	struct udevice *dev;
-	int ret;
-
-#ifdef CONFIG_DEBUG_UART
-	/*
-	 * Debug UART can be used from here if required:
-	 *
-	 * debug_uart_init();
-	 * printch('a');
-	 * printhex8(0x1234);
-	 * printascii("string");
-	 */
-	debug_uart_init();
-	printascii("U-Boot SPL board init");
-#endif
-
-#ifdef CONFIG_ROCKCHIP_USB_UART
-	rk_clrsetreg(&grf->uoc0_con[0],
-		     SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK,
-		     1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT |
-		     1 << COMMON_ON_N_SHIFT);
-	rk_clrsetreg(&grf->uoc0_con[2],
-		     SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT);
-	rk_clrsetreg(&grf->uoc0_con[3],
-		     OPMODE_MASK | XCVRSELECT_MASK |
-		     TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK,
-		     OPMODE_NODRIVING << OPMODE_SHIFT |
-		     XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT |
-		     1 << TERMSEL_FULLSPEED_SHIFT |
-		     1 << SUSPENDN_SHIFT);
-	rk_clrsetreg(&grf->uoc0_con[0],
-		     BYPASSSEL_MASK | BYPASSDMEN_MASK,
-		     1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT);
-#endif
-
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	ret = rockchip_get_clk(&dev);
-	if (ret) {
-		debug("CLK init failed: %d\n", ret);
-		return;
-	}
-
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		debug("DRAM init failed: %d\n", ret);
-		return;
-	}
-
-	setup_arm_clock();
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-}
-
-static int setup_led(void)
-{
-#ifdef CONFIG_SPL_LED
-	struct udevice *dev;
-	char *led_name;
-	int ret;
-
-	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
-	if (!led_name)
-		return 0;
-	ret = led_get_by_label(led_name, &dev);
-	if (ret) {
-		debug("%s: get=%d\n", __func__, ret);
-		return ret;
-	}
-	ret = led_set_on(dev, 1);
-	if (ret)
-		return ret;
-#endif
-
-	return 0;
-}
-
-void spl_board_init(void)
-{
-	int ret;
-
-	ret = setup_led();
-	if (ret) {
-		debug("LED ret=%d\n", ret);
-		hang();
-	}
-
-	preloader_console_init();
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-	return;
-}
diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c
deleted file mode 100644
index 94fd6c0..0000000
--- a/arch/arm/mach-rockchip/rk3188-board.c
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Google, Inc
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/grf_rk3188.h>
-#include <asm/arch-rockchip/periph.h>
-#include <asm/arch-rockchip/pmu_rk3288.h>
-#include <asm/arch-rockchip/boot_mode.h>
-
-__weak int rk_board_late_init(void)
-{
-	return 0;
-}
-
-int board_late_init(void)
-{
-	struct rk3188_grf *grf;
-
-	setup_boot_mode();
-	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-	if (IS_ERR(grf)) {
-		pr_err("grf syscon returned %ld\n", PTR_ERR(grf));
-	} else {
-		/* enable noc remap to mimic legacy loaders */
-		rk_clrsetreg(&grf->soc_con0,
-			NOC_REMAP_MASK << NOC_REMAP_SHIFT,
-			NOC_REMAP_MASK << NOC_REMAP_SHIFT);
-	}
-
-	return rk_board_late_init();
-}
-
-int board_init(void)
-{
-	return 0;
-}
-
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c
index 933484e..95f0e3c 100644
--- a/arch/arm/mach-rockchip/rk3188/rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188/rk3188.c
@@ -3,15 +3,25 @@
  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
  */
 #include <common.h>
+#include <dm.h>
+#include <syscon.h>
 #include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/grf_rk3188.h>
 #include <asm/arch-rockchip/hardware.h>
 
+#define GRF_BASE	0x20008000
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "dwmmc@1021c000",
+	[BROM_BOOTSOURCE_SD] = "dwmmc@10214000",
+};
+
 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 void board_debug_uart_init(void)
 {
 	/* Enable early UART on the RK3188 */
-#define GRF_BASE	0x20008000
 	struct rk3188_grf * const grf = (void *)GRF_BASE;
 	enum {
 		GPIO1B1_SHIFT		= 2,
@@ -34,3 +44,77 @@ void board_debug_uart_init(void)
 		     GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
 }
 #endif
+
+#ifdef CONFIG_SPL_BUILD
+int arch_cpu_init(void)
+{
+	struct rk3188_grf *grf;
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (IS_ERR(grf)) {
+		pr_err("grf syscon returned %ld\n", PTR_ERR(grf));
+		return 0;
+	}
+#ifdef CONFIG_ROCKCHIP_USB_UART
+	rk_clrsetreg(&grf->uoc0_con[0],
+		     SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK,
+		     1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT |
+		     1 << COMMON_ON_N_SHIFT);
+	rk_clrsetreg(&grf->uoc0_con[2],
+		     SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT);
+	rk_clrsetreg(&grf->uoc0_con[3],
+		     OPMODE_MASK | XCVRSELECT_MASK |
+		     TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK,
+		     OPMODE_NODRIVING << OPMODE_SHIFT |
+		     XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT |
+		     1 << TERMSEL_FULLSPEED_SHIFT |
+		     1 << SUSPENDN_SHIFT);
+	rk_clrsetreg(&grf->uoc0_con[0],
+		     BYPASSSEL_MASK | BYPASSDMEN_MASK,
+		     1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT);
+#endif
+
+	/* enable noc remap to mimic legacy loaders */
+	rk_clrsetreg(&grf->soc_con0,
+		     NOC_REMAP_MASK << NOC_REMAP_SHIFT,
+		     NOC_REMAP_MASK << NOC_REMAP_SHIFT);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+static int setup_led(void)
+{
+#ifdef CONFIG_SPL_LED
+	struct udevice *dev;
+	char *led_name;
+	int ret;
+
+	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
+	if (!led_name)
+		return 0;
+	ret = led_get_by_label(led_name, &dev);
+	if (ret) {
+		debug("%s: get=%d\n", __func__, ret);
+		return ret;
+	}
+	ret = led_set_on(dev, 1);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	int ret;
+
+	ret = setup_led();
+	if (ret) {
+		debug("LED ret=%d\n", ret);
+		hang();
+	}
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c
deleted file mode 100644
index c825e31..0000000
--- a/arch/arm/mach-rockchip/rk322x-board-spl.c
+++ /dev/null
@@ -1,76 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <dm.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/hardware.h>
-
-u32 spl_boot_device(void)
-{
-	return BOOT_DEVICE_MMC1;
-}
-
-u32 spl_boot_mode(const u32 boot_device)
-{
-	return MMCSD_MODE_RAW;
-}
-
-#define TIMER_LOAD_COUNT_L	0x00
-#define TIMER_LOAD_COUNT_H	0x04
-#define TIMER_CONTROL_REG	0x10
-#define TIMER_EN	0x1
-#define	TIMER_FMODE	BIT(0)
-#define	TIMER_RMODE	BIT(1)
-
-void rockchip_stimer_init(void)
-{
-	/* If Timer already enabled, don't re-init it */
-	u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
-
-	if (reg & TIMER_EN)
-		return;
-
-	asm volatile("mcr p15, 0, %0, c14, c0, 0"
-		     : : "r"(COUNTER_FREQUENCY));
-
-	writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
-	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
-	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
-	writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
-	       TIMER_CONTROL_REG);
-}
-
-#define SGRF_DDR_CON0 0x10150000
-void board_init_f(ulong dummy)
-{
-	int ret;
-
-	ret = spl_early_init();
-	if (ret) {
-		printf("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-	preloader_console_init();
-
-	/* Init secure timer */
-	rockchip_stimer_init();
-	/* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
-	timer_init();
-
-	/* Disable the ddr secure region setting to make it non-secure */
-	rk_clrreg(SGRF_DDR_CON0, 0x4000);
-}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
-	/* Just empty function now - can't decide what to choose */
-	debug("%s: %s\n", __func__, name);
-
-	return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c
deleted file mode 100644
index e7a1e54..0000000
--- a/arch/arm/mach-rockchip/rk322x-board.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
- */
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/boot_mode.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/grf_rk322x.h>
-#include <asm/arch-rockchip/periph.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
-	return 0;
-}
-
-int board_late_init(void)
-{
-	setup_boot_mode();
-
-	return rk_board_late_init();
-}
-
-int board_init(void)
-{
-#include <asm/arch-rockchip/grf_rk322x.h>
-	/* Enable early UART2 channel 1 on the RK322x */
-#define GRF_BASE	0x11000000
-	static struct rk322x_grf * const grf = (void *)GRF_BASE;
-
-	/*
-	* The integrated macphy is enabled by default, disable it
-	* for saving power consuming.
-	*/
-	rk_clrsetreg(&grf->macphy_con[0],
-		     MACPHY_CFG_ENABLE_MASK,
-		     0 << MACPHY_CFG_ENABLE_SHIFT);
-
-	return 0;
-}
-
-int dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = 0x8400000;
-	/* Reserve 0x200000 for OPTEE */
-	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
-				+ gd->bd->bi_dram[0].size + 0x200000;
-	gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
-				+ gd->ram_size - gd->bd->bi_dram[1].start;
-
-	return 0;
-}
-
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk322x_otg_data = {
-	.rx_fifo_sz	= 512,
-	.np_tx_fifo_sz	= 16,
-	.tx_fifo_sz	= 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	int node;
-	const char *mode;
-	bool matched = false;
-	const void *blob = gd->fdt_blob;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3288-usb");
-
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-					"rockchip,rk3288-usb");
-	}
-	if (!matched) {
-		debug("Not found usb_otg device\n");
-		return -ENODEV;
-	}
-	rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-	return dwc2_udc_probe(&rk322x_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return 0;
-}
-#endif
-
-#if CONFIG_IS_ENABLED(FASTBOOT)
-int fastboot_set_reboot_flag(void)
-{
-	struct rk322x_grf *grf;
-
-	printf("Setting reboot to fastboot flag ...\n");
-	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-	/* Set boot mode to fastboot */
-	writel(BOOT_FASTBOOT, &grf->os_reg[0]);
-
-	return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c
index e5250bc..cd0bf8a 100644
--- a/arch/arm/mach-rockchip/rk322x/rk322x.c
+++ b/arch/arm/mach-rockchip/rk322x/rk322x.c
@@ -3,9 +3,15 @@
  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
  */
 #include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
 #include <asm/arch-rockchip/grf_rk322x.h>
 #include <asm/arch-rockchip/hardware.h>
 
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "dwmmc@30020000",
+	[BROM_BOOTSOURCE_SD] = "dwmmc@30000000",
+};
+
 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 void board_debug_uart_init(void)
 {
@@ -42,3 +48,26 @@ void board_debug_uart_init(void)
 		     CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
 }
 #endif
+
+int arch_cpu_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+#define SGRF_BASE	0x10150000
+	static struct rk322x_sgrf * const sgrf = (void *)SGRF_BASE;
+
+	/* Disable the ddr secure region setting to make it non-secure */
+	rk_clrreg(&sgrf->soc_con[0], 0x4000);
+#else
+#define GRF_BASE	0x11000000
+	static struct rk322x_grf * const grf = (void *)GRF_BASE;
+	/*
+	 * The integrated macphy is enabled by default, disable it
+	 * for saving power consuming.
+	 */
+	rk_clrsetreg(&grf->macphy_con[0],
+		     MACPHY_CFG_ENABLE_MASK,
+		     0 << MACPHY_CFG_ENABLE_SHIFT);
+
+#endif
+	return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
deleted file mode 100644
index c2e1681..0000000
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ /dev/null
@@ -1,249 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Google, Inc
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <i2c.h>
-#include <led.h>
-#include <malloc.h>
-#include <ram.h>
-#include <spl.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch-rockchip/periph.h>
-#include <asm/arch-rockchip/pmu_rk3288.h>
-#include <asm/arch-rockchip/sdram.h>
-#include <asm/arch-rockchip/sdram_common.h>
-#include <asm/arch-rockchip/sys_proto.h>
-#include <dm/root.h>
-#include <dm/test.h>
-#include <dm/util.h>
-#include <power/regulator.h>
-#include <power/rk8xx_pmic.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 spl_boot_device(void)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-	const void *blob = gd->fdt_blob;
-	struct udevice *dev;
-	const char *bootdev;
-	int node;
-	int ret;
-
-	bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
-	debug("Boot device %s\n", bootdev);
-	if (!bootdev)
-		goto fallback;
-
-	node = fdt_path_offset(blob, bootdev);
-	if (node < 0) {
-		debug("node=%d\n", node);
-		goto fallback;
-	}
-	ret = device_get_global_by_ofnode(offset_to_ofnode(node), &dev);
-	if (ret) {
-		debug("device at node %s/%d not found: %d\n", bootdev, node,
-		      ret);
-		goto fallback;
-	}
-	debug("Found device %s\n", dev->name);
-	switch (device_get_uclass_id(dev)) {
-	case UCLASS_SPI_FLASH:
-		return BOOT_DEVICE_SPI;
-	case UCLASS_MMC:
-		return BOOT_DEVICE_MMC1;
-	default:
-		debug("Booting from device uclass '%s' not supported\n",
-		      dev_get_uclass_name(dev));
-	}
-
-fallback:
-#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
-		defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
-		defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
-		defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY)
-	return BOOT_DEVICE_SPI;
-#endif
-	return BOOT_DEVICE_MMC1;
-}
-
-#if !defined(CONFIG_SPL_OF_PLATDATA)
-static int phycore_init(void)
-{
-	struct udevice *pmic;
-	int ret;
-
-	ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
-	if (ret)
-		return ret;
-
-#if defined(CONFIG_SPL_POWER_SUPPORT)
-	/* Increase USB input current to 2A */
-	ret = rk818_spl_configure_usb_input_current(pmic, 2000);
-	if (ret)
-		return ret;
-
-	/* Close charger when USB lower then 3.26V */
-	ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
-	if (ret)
-		return ret;
-#endif
-
-	return 0;
-}
-#endif
-
-__weak int arch_cpu_init(void)
-{
-	return 0;
-}
-
-#define TIMER_LOAD_COUNT_L	0x00
-#define TIMER_LOAD_COUNT_H	0x04
-#define TIMER_CONTROL_REG	0x10
-#define TIMER_EN	0x1
-#define	TIMER_FMODE	BIT(0)
-#define	TIMER_RMODE	BIT(1)
-
-void rockchip_stimer_init(void)
-{
-	/* If Timer already enabled, don't re-init it */
-	u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
-
-	if (reg & TIMER_EN)
-		return;
-
-	asm volatile("mcr p15, 0, %0, c14, c0, 0"
-		     : : "r"(COUNTER_FREQUENCY));
-
-	writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
-	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
-	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
-	writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
-	       TIMER_CONTROL_REG);
-}
-
-void board_init_f(ulong dummy)
-{
-	struct udevice *dev;
-	int ret;
-
-#ifdef CONFIG_DEBUG_UART
-	/*
-	 * Debug UART can be used from here if required:
-	 *
-	 * debug_uart_init();
-	 * printch('a');
-	 * printhex8(0x1234);
-	 * printascii("string");
-	 */
-	debug_uart_init();
-	debug("\nspl:debug uart enabled in %s\n", __func__);
-#endif
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	/* Init secure timer */
-	rockchip_stimer_init();
-	/* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
-	timer_init();
-
-	arch_cpu_init();
-
-	ret = rockchip_get_clk(&dev);
-	if (ret) {
-		debug("CLK init failed: %d\n", ret);
-		return;
-	}
-
-#if !defined(CONFIG_SPL_OF_PLATDATA)
-	if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
-		ret = phycore_init();
-		if (ret) {
-			debug("Failed to set up phycore power settings: %d\n",
-			      ret);
-			return;
-		}
-	}
-#endif
-
-#if !defined(CONFIG_SUPPORT_TPL)
-	debug("\nspl:init dram\n");
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		debug("DRAM init failed: %d\n", ret);
-		return;
-	}
-#endif
-
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-}
-
-static int setup_led(void)
-{
-#ifdef CONFIG_SPL_LED
-	struct udevice *dev;
-	char *led_name;
-	int ret;
-
-	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
-	if (!led_name)
-		return 0;
-	ret = led_get_by_label(led_name, &dev);
-	if (ret) {
-		debug("%s: get=%d\n", __func__, ret);
-		return ret;
-	}
-	ret = led_set_on(dev, 1);
-	if (ret)
-		return ret;
-#endif
-
-	return 0;
-}
-
-void spl_board_init(void)
-{
-	int ret;
-
-	ret = setup_led();
-	if (ret) {
-		debug("LED ret=%d\n", ret);
-		hang();
-	}
-
-	preloader_console_init();
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-	return;
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-
-#define PMU_BASE		0xff730000
-int dram_init_banksize(void)
-{
-	struct rk3288_pmu *const pmu = (void *)PMU_BASE;
-	size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]);
-
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = size;
-
-	return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
deleted file mode 100644
index a250d50..0000000
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ /dev/null
@@ -1,320 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Google, Inc
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3288.h>
-#include <asm/arch-rockchip/periph.h>
-#include <asm/arch-rockchip/pmu_rk3288.h>
-#include <asm/arch-rockchip/qos_rk3288.h>
-#include <asm/arch-rockchip/boot_mode.h>
-#include <asm/gpio.h>
-#include <dt-bindings/clock/rk3288-cru.h>
-#include <power/regulator.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
-	return 0;
-}
-
-int rk3288_qos_init(void)
-{
-	int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
-	/* set vop qos to higher priority */
-	writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
-	writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
-
-	if (!fdt_node_check_compatible(gd->fdt_blob, 0,
-				       "rockchip,rk3288-tinker"))
-	{
-		/* set isp qos to higher priority */
-		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
-		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
-		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
-	}
-	return 0;
-}
-
-static void rk3288_detect_reset_reason(void)
-{
-	struct rk3288_cru *cru = rockchip_get_cru();
-	const char *reason;
-
-	if (IS_ERR(cru))
-		return;
-
-	switch (cru->cru_glb_rst_st) {
-	case GLB_POR_RST:
-		reason = "POR";
-		break;
-	case FST_GLB_RST_ST:
-	case SND_GLB_RST_ST:
-		reason = "RST";
-		break;
-	case FST_GLB_TSADC_RST_ST:
-	case SND_GLB_TSADC_RST_ST:
-		reason = "THERMAL";
-		break;
-	case FST_GLB_WDT_RST_ST:
-	case SND_GLB_WDT_RST_ST:
-		reason = "WDOG";
-		break;
-	default:
-		reason = "unknown reset";
-	}
-
-	env_set("reset_reason", reason);
-
-	/*
-	 * Clear cru_glb_rst_st, so we can determine the last reset cause
-	 * for following resets.
-	 */
-	rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
-}
-
-int board_late_init(void)
-{
-	setup_boot_mode();
-	rk3288_qos_init();
-	rk3288_detect_reset_reason();
-
-	return rk_board_late_init();
-}
-
-#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-static int veyron_init(void)
-{
-	struct udevice *dev;
-	struct clk clk;
-	int ret;
-
-	ret = regulator_get_by_platname("vdd_arm", &dev);
-	if (ret) {
-		debug("Cannot set regulator name\n");
-		return ret;
-	}
-
-	/* Slowly raise to max CPU voltage to prevent overshoot */
-	ret = regulator_set_value(dev, 1200000);
-	if (ret)
-		return ret;
-	udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
-	ret = regulator_set_value(dev, 1400000);
-	if (ret)
-		return ret;
-	udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
-
-	ret = rockchip_get_clk(&clk.dev);
-	if (ret)
-		return ret;
-	clk.id = PLL_APLL;
-	ret = clk_set_rate(&clk, 1800000000);
-	if (IS_ERR_VALUE(ret))
-		return ret;
-
-	ret = regulator_get_by_platname("vcc33_sd", &dev);
-	if (ret) {
-		debug("Cannot get regulator name\n");
-		return ret;
-	}
-
-	ret = regulator_set_value(dev, 3300000);
-	if (ret)
-		return ret;
-
-	ret = regulators_enable_boot_on(false);
-	if (ret) {
-		debug("%s: Cannot enable boot on regulators\n", __func__);
-		return ret;
-	}
-
-	return 0;
-}
-#endif
-
-int board_init(void)
-{
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-	return 0;
-#else
-	int ret;
-
-	/* We do some SoC one time setting here */
-	if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
-		ret = veyron_init();
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-#endif
-}
-
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3288_otg_data = {
-	.rx_fifo_sz	= 512,
-	.np_tx_fifo_sz	= 16,
-	.tx_fifo_sz	= 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	int node, phy_node;
-	const char *mode;
-	bool matched = false;
-	const void *blob = gd->fdt_blob;
-	u32 grf_phy_offset;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3288-usb");
-
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-					"rockchip,rk3288-usb");
-	}
-	if (!matched) {
-		debug("Not found usb_otg device\n");
-		return -ENODEV;
-	}
-	rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-	node = fdtdec_lookup_phandle(blob, node, "phys");
-	if (node <= 0) {
-		debug("Not found usb phy device\n");
-		return -ENODEV;
-	}
-
-	phy_node = fdt_parent_offset(blob, node);
-	if (phy_node <= 0) {
-		debug("Not found usb phy device\n");
-		return -ENODEV;
-	}
-
-	rk3288_otg_data.phy_of_node = phy_node;
-	grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
-
-	/* find the grf node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3288-grf");
-	if (node <= 0) {
-		debug("Not found grf device\n");
-		return -ENODEV;
-	}
-	rk3288_otg_data.regs_phy = grf_phy_offset +
-				fdtdec_get_addr(blob, node, "reg");
-
-	return dwc2_udc_probe(&rk3288_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return 0;
-}
-#endif
-
-static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
-		       char * const argv[])
-{
-	static const struct {
-		char *name;
-		int id;
-	} clks[] = {
-		{ "osc", CLK_OSC },
-		{ "apll", CLK_ARM },
-		{ "dpll", CLK_DDR },
-		{ "cpll", CLK_CODEC },
-		{ "gpll", CLK_GENERAL },
-#ifdef CONFIG_ROCKCHIP_RK3036
-		{ "mpll", CLK_NEW },
-#else
-		{ "npll", CLK_NEW },
-#endif
-	};
-	int ret, i;
-	struct udevice *dev;
-
-	ret = rockchip_get_clk(&dev);
-	if (ret) {
-		printf("clk-uclass not found\n");
-		return 0;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(clks); i++) {
-		struct clk clk;
-		ulong rate;
-
-		clk.id = clks[i].id;
-		ret = clk_request(dev, &clk);
-		if (ret < 0)
-			continue;
-
-		rate = clk_get_rate(&clk);
-		printf("%s: %lu\n", clks[i].name, rate);
-
-		clk_free(&clk);
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	clock, 2, 1, do_clock,
-	"display information about clocks",
-	""
-);
-
-int board_early_init_f(void)
-{
-	const uintptr_t GRF_SOC_CON0 = 0xff770244;
-	const uintptr_t GRF_SOC_CON2 = 0xff77024c;
-	struct udevice *dev;
-	int ret;
-
-	/*
-	 * This init is done in SPL, but when chain-loading U-Boot SPL will
-	 * have been skipped. Allow the clock driver to check if it needs
-	 * setting up.
-	 */
-	ret = rockchip_get_clk(&dev);
-	if (ret) {
-		debug("CLK init failed: %d\n", ret);
-		return ret;
-	}
-
-	rk_setreg(GRF_SOC_CON2, 1 << 0);
-
-	/*
-	 * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
-	 * cleared
-	 */
-	rk_clrreg(GRF_SOC_CON0, 1 << 12);
-
-	return 0;
-}
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index de8d9c2..87d0786 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -66,6 +66,7 @@ config TARGET_FENNEC_RK3288
 config TARGET_FIREFLY_RK3288
 	bool "Firefly-RK3288"
 	select BOARD_LATE_INIT
+	select SPL_BOARD_INIT if SPL
 	help
 	  Firefly is a RK3288-based development board with 2 USB ports,
 	  HDMI, VGA, micro-SD card, audio, WiFi  and Gigabit Ethernet, It
@@ -84,6 +85,7 @@ config TARGET_MIQI_RK3288
 config TARGET_PHYCORE_RK3288
 	bool "phyCORE-RK3288"
         select BOARD_LATE_INIT
+	select SPL_BOARD_INIT if SPL
 	help
 	  Add basic support for the PCM-947 carrier board, a RK3288 based
 	  development board made by PHYTEC. This board works in a combination
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
index 7552472..b462c09 100644
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -2,13 +2,29 @@
 /*
  * Copyright (c) 2016 Rockchip Electronics Co., Ltd
  */
+#include <common.h>
+#include <dm.h>
+#include <clk.h>
 #include <asm/armv7.h>
 #include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3288.h>
 #include <asm/arch-rockchip/hardware.h>
 #include <asm/arch-rockchip/grf_rk3288.h>
+#include <asm/arch-rockchip/pmu_rk3288.h>
+#include <asm/arch-rockchip/qos_rk3288.h>
+#include <asm/arch-rockchip/sdram_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #define GRF_BASE	0xff770000
 
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "dwmmc@ff0f0000",
+	[BROM_BOOTSOURCE_SD] = "dwmmc@ff0c0000",
+};
+
 #ifdef CONFIG_SPL_BUILD
 static void configure_l2ctlr(void)
 {
@@ -30,6 +46,24 @@ static void configure_l2ctlr(void)
 }
 #endif
 
+int rk3288_qos_init(void)
+{
+	int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
+	/* set vop qos to higher priority */
+	writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
+	writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
+
+	if (!fdt_node_check_compatible(gd->fdt_blob, 0,
+				       "rockchip,rk3288-tinker")) {
+		/* set isp qos to higher priority */
+		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
+		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
+		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
+	}
+
+	return 0;
+}
+
 int arch_cpu_init(void)
 {
 #ifdef CONFIG_SPL_BUILD
@@ -40,6 +74,14 @@ int arch_cpu_init(void)
 
 	/* Use rkpwm by default */
 	rk_setreg(&grf->soc_con2, 1 << 0);
+
+	/*
+	 * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
+	 * cleared
+	 */
+	rk_clrreg(&grf->soc_con0, 1 << 12);
+
+	rk3288_qos_init();
 #endif
 
 	return 0;
@@ -57,3 +99,103 @@ void board_debug_uart_init(void)
 		     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
 }
 #endif
+
+static void rk3288_detect_reset_reason(void)
+{
+	struct rk3288_cru *cru = rockchip_get_cru();
+	const char *reason;
+
+	if (IS_ERR(cru))
+		return;
+
+	switch (cru->cru_glb_rst_st) {
+	case GLB_POR_RST:
+		reason = "POR";
+		break;
+	case FST_GLB_RST_ST:
+	case SND_GLB_RST_ST:
+		reason = "RST";
+		break;
+	case FST_GLB_TSADC_RST_ST:
+	case SND_GLB_TSADC_RST_ST:
+		reason = "THERMAL";
+		break;
+	case FST_GLB_WDT_RST_ST:
+	case SND_GLB_WDT_RST_ST:
+		reason = "WDOG";
+		break;
+	default:
+		reason = "unknown reset";
+	}
+
+	env_set("reset_reason", reason);
+
+	/*
+	 * Clear cru_glb_rst_st, so we can determine the last reset cause
+	 * for following resets.
+	 */
+	rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
+}
+
+__weak int rk3288_board_late_init(void)
+{
+	return 0;
+}
+
+int rk_board_late_init(void)
+{
+	rk3288_detect_reset_reason();
+
+	return rk3288_board_late_init();
+}
+
+static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	static const struct {
+		char *name;
+		int id;
+	} clks[] = {
+		{ "osc", CLK_OSC },
+		{ "apll", CLK_ARM },
+		{ "dpll", CLK_DDR },
+		{ "cpll", CLK_CODEC },
+		{ "gpll", CLK_GENERAL },
+#ifdef CONFIG_ROCKCHIP_RK3036
+		{ "mpll", CLK_NEW },
+#else
+		{ "npll", CLK_NEW },
+#endif
+	};
+	int ret, i;
+	struct udevice *dev;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret) {
+		printf("clk-uclass not found\n");
+		return 0;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(clks); i++) {
+		struct clk clk;
+		ulong rate;
+
+		clk.id = clks[i].id;
+		ret = clk_request(dev, &clk);
+		if (ret < 0)
+			continue;
+
+		rate = clk_get_rate(&clk);
+		printf("%s: %lu\n", clks[i].name, rate);
+
+		clk_free(&clk);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	clock, 2, 1, do_clock,
+	"display information about clocks",
+	""
+);
diff --git a/arch/arm/mach-rockchip/rk3328-board-spl.c b/arch/arm/mach-rockchip/rk3328-board-spl.c
deleted file mode 100644
index f24fd89..0000000
--- a/arch/arm/mach-rockchip/rk3328-board-spl.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <ram.h>
-#include <spl.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_debug_uart_init(void)
-{
-}
-
-void board_init_f(ulong dummy)
-{
-	struct udevice *dev;
-	int ret;
-
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	preloader_console_init();
-
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		debug("DRAM init failed: %d\n", ret);
-		return;
-	}
-}
-
-u32 spl_boot_mode(const u32 boot_device)
-{
-	return MMCSD_MODE_RAW;
-}
-
-u32 spl_boot_device(void)
-{
-	return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
-	/* Just empty function now - can't decide what to choose */
-	debug("%s: %s\n", __func__, name);
-
-	return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c
index 1cf829d..592f287 100644
--- a/arch/arm/mach-rockchip/rk3328/rk3328.c
+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
@@ -4,12 +4,24 @@
  */
 
 #include <common.h>
+#include <asm/arch-rockchip/bootrom.h>
 #include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/grf_rk3328.h>
+#include <asm/arch-rockchip/uart.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define CRU_BASE		0xFF440000
+#define GRF_BASE		0xFF100000
+#define UART2_BASE		0xFF130000
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "rksdmmc@ff520000",
+	[BROM_BOOTSOURCE_SD] = "rksdmmc@ff500000",
+};
+
 static struct mm_region rk3328_mem_map[] = {
 	{
 		.virt = 0x0UL,
@@ -32,20 +44,52 @@ static struct mm_region rk3328_mem_map[] = {
 
 struct mm_region *mem_map = rk3328_mem_map;
 
-int dram_init_banksize(void)
+int arch_cpu_init(void)
 {
-	size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
-
-	/* Reserve 0x200000 for ATF bl31 */
-	gd->bd->bi_dram[0].start = 0x200000;
-	gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
+	/* We do some SoC one time setting here. */
 
 	return 0;
 }
 
-int arch_cpu_init(void)
+void board_debug_uart_init(void)
 {
-	/* We do some SoC one time setting here. */
+	struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
+	struct rk_uart * const uart = (void *)UART2_BASE;
+	enum{
+		GPIO2A0_SEL_SHIFT       = 0,
+		GPIO2A0_SEL_MASK        = 3 << GPIO2A0_SEL_SHIFT,
+		GPIO2A0_UART2_TX_M1     = 1,
 
-	return 0;
+		GPIO2A1_SEL_SHIFT       = 2,
+		GPIO2A1_SEL_MASK        = 3 << GPIO2A1_SEL_SHIFT,
+		GPIO2A1_UART2_RX_M1     = 1,
+	};
+	enum {
+		IOMUX_SEL_UART2_SHIFT   = 0,
+		IOMUX_SEL_UART2_MASK    = 3 << IOMUX_SEL_UART2_SHIFT,
+		IOMUX_SEL_UART2_M0      = 0,
+		IOMUX_SEL_UART2_M1,
+	};
+
+	/* uart_sel_clk default select 24MHz */
+	writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148);
+
+	/* init uart baud rate 1500000 */
+	writel(0x83, &uart->lcr);
+	writel(0x1, &uart->rbr);
+	writel(0x3, &uart->lcr);
+
+	/* Enable early UART2 */
+	rk_clrsetreg(&grf->com_iomux,
+		     IOMUX_SEL_UART2_MASK,
+		     IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT);
+	rk_clrsetreg(&grf->gpio2a_iomux,
+		     GPIO2A0_SEL_MASK,
+		     GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT);
+	rk_clrsetreg(&grf->gpio2a_iomux,
+		     GPIO2A1_SEL_MASK,
+		     GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
+
+	/* enable FIFO */
+	writel(0x1, &uart->sfe);
 }
diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c
deleted file mode 100644
index 6ba106c..0000000
--- a/arch/arm/mach-rockchip/rk3368-board-spl.c
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <ram.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/periph.h>
-
-__weak int arch_cpu_init(void)
-{
-	return 0;
-}
-
-#define TIMER_LOAD_COUNT_L	0x00
-#define TIMER_LOAD_COUNT_H	0x04
-#define TIMER_CONTROL_REG	0x10
-#define TIMER_EN	0x1
-#define	TIMER_FMODE	BIT(0)
-#define	TIMER_RMODE	BIT(1)
-
-void rockchip_stimer_init(void)
-{
-	/* If Timer already enabled, don't re-init it */
-	u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
-
-	if (reg & TIMER_EN)
-		return;
-
-	writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
-	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
-	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
-	writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
-	       TIMER_CONTROL_REG);
-}
-
-void board_init_f(ulong dummy)
-{
-	struct udevice *dev;
-	int ret;
-
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	/* Init secure timer */
-	rockchip_stimer_init();
-	/* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
-	timer_init();
-
-	arch_cpu_init();
-	preloader_console_init();
-
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		debug("DRAM init failed: %d\n", ret);
-		return;
-	}
-}
-
-u32 spl_boot_device(void)
-{
-	return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
-	/* Just empty function now - can't decide what to choose */
-	debug("%s: %s\n", __func__, name);
-
-	return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c
index 47786f5..7ccd417 100644
--- a/arch/arm/mach-rockchip/rk3368/rk3368.c
+++ b/arch/arm/mach-rockchip/rk3368/rk3368.c
@@ -8,6 +8,7 @@
 #include <syscon.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/cru_rk3368.h>
 #include <asm/arch-rockchip/grf_rk3368.h>
@@ -52,16 +53,10 @@ static struct mm_region rk3368_mem_map[] = {
 
 struct mm_region *mem_map = rk3368_mem_map;
 
-int dram_init_banksize(void)
-{
-	size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
-
-	/* Reserve 0x200000 for ATF bl31 */
-	gd->bd->bi_dram[0].start = 0x200000;
-	gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
-
-	return 0;
-}
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "dwmmc@ff0f0000",
+	[BROM_BOOTSOURCE_SD] = "dwmmc@ff0c0000",
+};
 
 #ifdef CONFIG_ARCH_EARLY_INIT_R
 static int mcu_init(void)
diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
deleted file mode 100644
index 7154d8e..0000000
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ /dev/null
@@ -1,251 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <ram.h>
-#include <spl.h>
-#include <spl_gpio.h>
-#include <syscon.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3399.h>
-#include <asm/arch-rockchip/grf_rk3399.h>
-#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch-rockchip/periph.h>
-#include <asm/arch-rockchip/sys_proto.h>
-#include <power/regulator.h>
-
-void board_return_to_bootrom(void)
-{
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-}
-
-static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
-	[BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
-	[BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
-	[BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
-};
-
-const char *board_spl_was_booted_from(void)
-{
-	u32  bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR);
-	const char *bootdevice_ofpath = NULL;
-
-	if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
-		bootdevice_ofpath = boot_devices[bootdevice_brom_id];
-
-	if (bootdevice_ofpath)
-		debug("%s: brom_bootdevice_id %x maps to '%s'\n",
-		      __func__, bootdevice_brom_id, bootdevice_ofpath);
-	else
-		debug("%s: failed to resolve brom_bootdevice_id %x\n",
-		      __func__, bootdevice_brom_id);
-
-	return bootdevice_ofpath;
-}
-
-u32 spl_boot_device(void)
-{
-	u32 boot_device = BOOT_DEVICE_MMC1;
-
-	if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
-		return BOOT_DEVICE_BOOTROM;
-
-	return boot_device;
-}
-
-const char *spl_decode_boot_device(u32 boot_device)
-{
-	int i;
-	static const struct {
-		u32 boot_device;
-		const char *ofpath;
-	} spl_boot_devices_tbl[] = {
-		{ BOOT_DEVICE_MMC1, "/dwmmc@fe320000" },
-		{ BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
-		{ BOOT_DEVICE_SPI, "/spi@ff1d0000" },
-	};
-
-	for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
-		if (spl_boot_devices_tbl[i].boot_device == boot_device)
-			return spl_boot_devices_tbl[i].ofpath;
-
-	return NULL;
-}
-
-void spl_perform_fixups(struct spl_image_info *spl_image)
-{
-	void *blob = spl_image->fdt_addr;
-	const char *boot_ofpath;
-	int chosen;
-
-	/*
-	 * Inject the ofpath of the device the full U-Boot (or Linux in
-	 * Falcon-mode) was booted from into the FDT, if a FDT has been
-	 * loaded at the same time.
-	 */
-	if (!blob)
-		return;
-
-	boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
-	if (!boot_ofpath) {
-		pr_err("%s: could not map boot_device to ofpath\n", __func__);
-		return;
-	}
-
-	chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
-	if (chosen < 0) {
-		pr_err("%s: could not find/create '/chosen'\n", __func__);
-		return;
-	}
-	fdt_setprop_string(blob, chosen,
-			   "u-boot,spl-boot-device", boot_ofpath);
-}
-
-__weak void rockchip_stimer_init(void)
-{
-}
-
-void board_init_f(ulong dummy)
-{
-	struct udevice *dev;
-	struct rk3399_pmusgrf_regs *sgrf;
-	struct rk3399_grf_regs *grf;
-	int ret;
-
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-
-# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
-	int sum, i;
-
-	/*
-	 * Add a delay and ensure that the compiler does not optimise this out.
-	 * This is needed since the power rails tail a while to turn on, and
-	 * we get garbage serial output otherwise.
-	 */
-	sum = 0;
-	for (i = 0; i < 150000; i++)
-		sum += i;
-	gru_dummy_function(sum);
-#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
-
-	/*
-	 * Debug UART can be used from here if required:
-	 *
-	 * debug_uart_init();
-	 * printch('a');
-	 * printhex8(0x1234);
-	 * printascii("string");
-	 */
-	debug("U-Boot SPL board init\n");
-#endif
-
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	/*
-	 * Disable DDR and SRAM security regions.
-	 *
-	 * As we are entered from the BootROM, the region from
-	 * 0x0 through 0xfffff (i.e. the first MB of memory) will
-	 * be protected. This will cause issues with the DW_MMC
-	 * driver, which tries to DMA from/to the stack (likely)
-	 * located in this range.
-	 */
-	sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
-	rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
-	rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
-
-	/*  eMMC clock generator: disable the clock multipilier */
-	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-	rk_clrreg(&grf->emmccore_con[11], 0x0ff);
-
-	rockchip_stimer_init();
-
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		pr_err("DRAM init failed: %d\n", ret);
-		return;
-	}
-}
-
-#if defined(SPL_GPIO_SUPPORT)
-static void rk3399_force_power_on_reset(void)
-{
-	ofnode node;
-	struct gpio_desc sysreset_gpio;
-
-	debug("%s: trying to force a power-on reset\n", __func__);
-
-	node = ofnode_path("/config");
-	if (!ofnode_valid(node)) {
-		debug("%s: no /config node?\n", __func__);
-		return;
-	}
-
-	if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
-				       &sysreset_gpio, GPIOD_IS_OUT)) {
-		debug("%s: could not find a /config/sysreset-gpio\n", __func__);
-		return;
-	}
-
-	dm_gpio_set_value(&sysreset_gpio, 1);
-}
-#endif
-
-void spl_board_init(void)
-{
-#if defined(SPL_GPIO_SUPPORT)
-	struct rk3399_cru *cru = rockchip_get_cru();
-
-	/*
-	 * The RK3399 resets only 'almost all logic' (see also in the TRM
-	 * "3.9.4 Global software reset"), when issuing a software reset.
-	 * This may cause issues during boot-up for some configurations of
-	 * the application software stack.
-	 *
-	 * To work around this, we test whether the last reset reason was
-	 * a power-on reset and (if not) issue an overtemp-reset to reset
-	 * the entire module.
-	 *
-	 * While this was previously fixed by modifying the various places
-	 * that could generate a software reset (e.g. U-Boot's sysreset
-	 * driver, the ATF or Linux), we now have it here to ensure that
-	 * we no longer have to track this through the various components.
-	 */
-	if (cru->glb_rst_st != 0)
-		rk3399_force_power_on_reset();
-#endif
-
-#if defined(SPL_DM_REGULATOR)
-	/*
-	 * Turning the eMMC and SPI back on (if disabled via the Qseven
-	 * BIOS_ENABLE) signal is done through a always-on regulator).
-	 */
-	if (regulators_enable_boot_on(false))
-		debug("%s: Cannot enable boot on regulator\n", __func__);
-#endif
-
-	preloader_console_init();
-}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
-	/* Just empty function now - can't decide what to choose */
-	debug("%s: %s\n", __func__, name);
-
-	return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3399-board.c b/arch/arm/mach-rockchip/rk3399-board.c
deleted file mode 100644
index 443c87c..0000000
--- a/arch/arm/mach-rockchip/rk3399-board.c
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2017 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <asm/arch-rockchip/boot_mode.h>
-
-int board_late_init(void)
-{
-	setup_boot_mode();
-	return 0;
-}
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index 0f09ea5..863024d 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -4,18 +4,29 @@
  */
 
 #include <common.h>
+#include <spl.h>
 #include <spl_gpio.h>
+#include <syscon.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/gpio.h>
 #include <asm/arch-rockchip/grf_rk3399.h>
 #include <asm/arch-rockchip/hardware.h>
+#include <power/regulator.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #define GRF_EMMCCORE_CON11 0xff77f02c
 #define GRF_BASE	0xff770000
 
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
+	[BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
+	[BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
+};
+
 static struct mm_region rk3399_mem_map[] = {
 	{
 		.virt = 0x0UL,
@@ -67,24 +78,30 @@ void rockchip_stimer_init(void)
 }
 #endif
 
-int dram_init_banksize(void)
+int arch_cpu_init(void)
 {
-	size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
-
-	/* Reserve 0x200000 for ATF bl31 */
-	gd->bd->bi_dram[0].start = 0x200000;
-	gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
 
-	return 0;
-}
+#ifdef CONFIG_SPL_BUILD
+	struct rk3399_pmusgrf_regs *sgrf;
+	struct rk3399_grf_regs *grf;
 
-int arch_cpu_init(void)
-{
-	/* We do some SoC one time setting here. */
-	struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
+	/*
+	 * Disable DDR and SRAM security regions.
+	 *
+	 * As we are entered from the BootROM, the region from
+	 * 0x0 through 0xfffff (i.e. the first MB of memory) will
+	 * be protected. This will cause issues with the DW_MMC
+	 * driver, which tries to DMA from/to the stack (likely)
+	 * located in this range.
+	 */
+	sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
+	rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
+	rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
 
-	/* Emmc clock generator: disable the clock multipilier */
+	/*  eMMC clock generator: disable the clock multipilier */
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 	rk_clrreg(&grf->emmccore_con[11], 0x0ff);
+#endif
 
 	return 0;
 }
@@ -146,3 +163,111 @@ void board_debug_uart_init(void)
 #endif
 }
 #endif
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+const char *spl_decode_boot_device(u32 boot_device)
+{
+	int i;
+	static const struct {
+		u32 boot_device;
+		const char *ofpath;
+	} spl_boot_devices_tbl[] = {
+		{ BOOT_DEVICE_MMC1, "/dwmmc@fe320000" },
+		{ BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
+		{ BOOT_DEVICE_SPI, "/spi@ff1d0000" },
+	};
+
+	for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
+		if (spl_boot_devices_tbl[i].boot_device == boot_device)
+			return spl_boot_devices_tbl[i].ofpath;
+
+	return NULL;
+}
+
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	void *blob = spl_image->fdt_addr;
+	const char *boot_ofpath;
+	int chosen;
+
+	/*
+	 * Inject the ofpath of the device the full U-Boot (or Linux in
+	 * Falcon-mode) was booted from into the FDT, if a FDT has been
+	 * loaded at the same time.
+	 */
+	if (!blob)
+		return;
+
+	boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
+	if (!boot_ofpath) {
+		pr_err("%s: could not map boot_device to ofpath\n", __func__);
+		return;
+	}
+
+	chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
+	if (chosen < 0) {
+		pr_err("%s: could not find/create '/chosen'\n", __func__);
+		return;
+	}
+	fdt_setprop_string(blob, chosen,
+			   "u-boot,spl-boot-device", boot_ofpath);
+}
+
+#if defined(SPL_GPIO_SUPPORT)
+static void rk3399_force_power_on_reset(void)
+{
+	ofnode node;
+	struct gpio_desc sysreset_gpio;
+
+	debug("%s: trying to force a power-on reset\n", __func__);
+
+	node = ofnode_path("/config");
+	if (!ofnode_valid(node)) {
+		debug("%s: no /config node?\n", __func__);
+		return;
+	}
+
+	if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
+				       &sysreset_gpio, GPIOD_IS_OUT)) {
+		debug("%s: could not find a /config/sysreset-gpio\n", __func__);
+		return;
+	}
+
+	dm_gpio_set_value(&sysreset_gpio, 1);
+}
+#endif
+
+void spl_board_init(void)
+{
+#if defined(SPL_GPIO_SUPPORT)
+	struct rk3399_cru *cru = rockchip_get_cru();
+
+	/*
+	 * The RK3399 resets only 'almost all logic' (see also in the TRM
+	 * "3.9.4 Global software reset"), when issuing a software reset.
+	 * This may cause issues during boot-up for some configurations of
+	 * the application software stack.
+	 *
+	 * To work around this, we test whether the last reset reason was
+	 * a power-on reset and (if not) issue an overtemp-reset to reset
+	 * the entire module.
+	 *
+	 * While this was previously fixed by modifying the various places
+	 * that could generate a software reset (e.g. U-Boot's sysreset
+	 * driver, the ATF or Linux), we now have it here to ensure that
+	 * we no longer have to track this through the various components.
+	 */
+	if (cru->glb_rst_st != 0)
+		rk3399_force_power_on_reset();
+#endif
+
+#if defined(SPL_DM_REGULATOR)
+	/*
+	 * Turning the eMMC and SPI back on (if disabled via the Qseven
+	 * BIOS_ENABLE) signal is done through a always-on regulator).
+	 */
+	if (regulators_enable_boot_on(false))
+		debug("%s: Cannot enable boot on regulator\n", __func__);
+#endif
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rv1108-board.c b/arch/arm/mach-rockchip/rv1108-board.c
deleted file mode 100644
index 3412f2c..0000000
--- a/arch/arm/mach-rockchip/rv1108-board.c
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Google, Inc
- */
-
-#include <common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rv1108_otg_data = {
-	.rx_fifo_sz	= 512,
-	.np_tx_fifo_sz	= 16,
-	.tx_fifo_sz	= 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	const void *blob = gd->fdt_blob;
-	bool matched = false;
-	int node, phy_node;
-	u32 grf_phy_offset;
-	const char *mode;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1, "rockchip,rk3066-usb");
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-						     "rockchip,rk3066-usb");
-	}
-
-	if (!matched) {
-		debug("usb_otg device not found\n");
-		return -ENODEV;
-	}
-
-	rv1108_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-	node = fdtdec_lookup_phandle(blob, node, "phys");
-	if (node <= 0) {
-		debug("phys node not found\n");
-		return -ENODEV;
-	}
-
-	phy_node = fdt_parent_offset(blob, node);
-	if (phy_node <= 0) {
-		debug("usb phy node not found\n");
-		return -ENODEV;
-	}
-
-	rv1108_otg_data.phy_of_node = phy_node;
-	grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
-
-	/* find the grf node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					     "rockchip,rv1108-grf");
-	if (node <= 0) {
-		debug("grf node not found\n");
-		return -ENODEV;
-	}
-
-	rv1108_otg_data.regs_phy = grf_phy_offset + fdtdec_get_addr(blob, node,
-								    "reg");
-
-	return dwc2_udc_probe(&rv1108_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c b/arch/arm/mach-rockchip/rv1108/rv1108.c
index 66aeb3f..6362af9 100644
--- a/arch/arm/mach-rockchip/rv1108/rv1108.c
+++ b/arch/arm/mach-rockchip/rv1108/rv1108.c
@@ -3,13 +3,3 @@
  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  * Author: Andy Yan <andy.yan@rock-chips.com>
  */
-
-#include <common.h>
-
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c
index 8684dbd..22a4aca 100644
--- a/arch/arm/mach-rockchip/sdram_common.c
+++ b/arch/arm/mach-rockchip/sdram_common.c
@@ -11,6 +11,69 @@
 #include <dm/uclass-internal.h>
 
 DECLARE_GLOBAL_DATA_PTR;
+
+#define TRUST_PARAMETER_OFFSET    (34 * 1024 * 1024)
+
+struct tos_parameter_t {
+	u32 version;
+	u32 checksum;
+	struct {
+		char name[8];
+		s64 phy_addr;
+		u32 size;
+		u32 flags;
+	} tee_mem;
+	struct {
+		char name[8];
+		s64 phy_addr;
+		u32 size;
+		u32 flags;
+	} drm_mem;
+	s64 reserve[8];
+};
+
+int dram_init_banksize(void)
+{
+	size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
+			 gd->ram_top);
+
+#ifdef CONFIG_ARM64
+	/* Reserve 0x200000 for ATF bl31 */
+	gd->bd->bi_dram[0].start = 0x200000;
+	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+#else
+#ifdef CONFIG_SPL_OPTEE
+	struct tos_parameter_t *tos_parameter;
+
+	tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
+			TRUST_PARAMETER_OFFSET);
+
+	if (tos_parameter->tee_mem.flags == 1) {
+		gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+		gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
+					- CONFIG_SYS_SDRAM_BASE;
+		gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
+					tos_parameter->tee_mem.size;
+		gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+					+ top - gd->bd->bi_dram[1].start;
+	} else {
+		gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+		gd->bd->bi_dram[0].size = 0x8400000;
+		/* Reserve 32M for OPTEE with TA */
+		gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+					+ gd->bd->bi_dram[0].size + 0x2000000;
+		gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+					+ top - gd->bd->bi_dram[1].start;
+	}
+#else
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+#endif
+#endif
+
+	return 0;
+}
+
 size_t rockchip_sdram_size(phys_addr_t reg)
 {
 	u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
new file mode 100644
index 0000000..33137cc
--- /dev/null
+++ b/arch/arm/mach-rockchip/spl.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/sdram.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_return_to_bootrom(void)
+{
+	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
+}
+
+__weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+};
+
+const char *board_spl_was_booted_from(void)
+{
+	u32  bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
+	const char *bootdevice_ofpath = NULL;
+
+	if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
+		bootdevice_ofpath = boot_devices[bootdevice_brom_id];
+
+	if (bootdevice_ofpath)
+		debug("%s: brom_bootdevice_id %x maps to '%s'\n",
+		      __func__, bootdevice_brom_id, bootdevice_ofpath);
+	else
+		debug("%s: failed to resolve brom_bootdevice_id %x\n",
+		      __func__, bootdevice_brom_id);
+
+	return bootdevice_ofpath;
+}
+
+u32 spl_boot_device(void)
+{
+	u32 boot_device = BOOT_DEVICE_MMC1;
+
+#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
+		defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
+		defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
+	return BOOT_DEVICE_SPI;
+#endif
+	if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
+		return BOOT_DEVICE_BOOTROM;
+
+	return boot_device;
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+	return MMCSD_MODE_RAW;
+}
+
+#if !defined(CONFIG_ROCKCHIP_RK3188)
+#define TIMER_LOAD_COUNT_L	0x00
+#define TIMER_LOAD_COUNT_H	0x04
+#define TIMER_CONTROL_REG	0x10
+#define TIMER_EN	0x1
+#define	TIMER_FMODE	BIT(0)
+#define	TIMER_RMODE	BIT(1)
+
+__weak void rockchip_stimer_init(void)
+{
+	/* If Timer already enabled, don't re-init it */
+	u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+
+	if (reg & TIMER_EN)
+		return;
+#ifndef CONFIG_ARM64
+	asm volatile("mcr p15, 0, %0, c14, c0, 0"
+		     : : "r"(COUNTER_FREQUENCY));
+#endif
+	writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
+	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
+	writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
+	       TIMER_CONTROL_REG);
+}
+#endif
+
+__weak int board_early_init_f(void)
+{
+	return 0;
+}
+
+__weak int arch_cpu_init(void)
+{
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+#if !defined(CONFIG_SUPPORT_TPL) || defined(CONFIG_SPL_OS_BOOT)
+	struct udevice *dev;
+#endif
+
+#ifdef CONFIG_DEBUG_UART
+	/*
+	 * Debug UART can be used from here if required:
+	 *
+	 * debug_uart_init();
+	 * printch('a');
+	 * printhex8(0x1234);
+	 * printascii("string");
+	 */
+	debug_uart_init();
+	debug("\nspl:debug uart enabled in %s\n", __func__);
+#endif
+
+	board_early_init_f();
+
+	ret = spl_early_init();
+	if (ret) {
+		printf("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+	arch_cpu_init();
+#if !defined(CONFIG_SUPPORT_TPL) || defined(CONFIG_SPL_OS_BOOT)
+	debug("\nspl:init dram\n");
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		printf("DRAM init failed: %d\n", ret);
+		return;
+	}
+#endif
+#if !defined(CONFIG_ROCKCHIP_RK3188)
+	rockchip_stimer_init();
+#endif
+#ifdef CONFIG_SYS_ARCH_TIMER
+	/* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
+	timer_init();
+#endif
+	preloader_console_init();
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
diff --git a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
index 9ba1fbd..47b921a 100644
--- a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
+++ b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
@@ -8,7 +8,7 @@
 
 #define GPIO7A3_HUB_RST	227
 
-int rk_board_late_init(void)
+int rk3288_board_late_init(void)
 {
 	int ret;
 
diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c
index 0de1f42..607667a 100644
--- a/board/elgin/elgin_rv1108/elgin_rv1108.c
+++ b/board/elgin/elgin_rv1108/elgin_rv1108.c
@@ -50,7 +50,7 @@ int mach_cpu_init(void)
 
 #define MODEM_ENABLE_GPIO 111
 
-int board_init(void)
+int board_early_init_f(void)
 {
 	gpio_request(MODEM_ENABLE_GPIO, "modem_enable");
 	gpio_direction_output(MODEM_ENABLE_GPIO, 0);
diff --git a/board/firefly/firefly-rk3288/firefly-rk3288.c b/board/firefly/firefly-rk3288/firefly-rk3288.c
index bdc02a6..a3f784f 100644
--- a/board/firefly/firefly-rk3288/firefly-rk3288.c
+++ b/board/firefly/firefly-rk3288/firefly-rk3288.c
@@ -4,3 +4,39 @@
  */
 
 #include <common.h>
+
+#ifdef CONFIG_SPL_BUILD
+static int setup_led(void)
+{
+#ifdef CONFIG_SPL_LED
+	struct udevice *dev;
+	char *led_name;
+	int ret;
+
+	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
+	if (!led_name)
+		return 0;
+	ret = led_get_by_label(led_name, &dev);
+	if (ret) {
+		debug("%s: get=%d\n", __func__, ret);
+		return ret;
+	}
+	ret = led_set_on(dev, 1);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	int ret;
+
+	ret = setup_led();
+	if (ret) {
+		debug("LED ret=%d\n", ret);
+		hang();
+	}
+}
+#endif
diff --git a/board/geekbuying/geekbox/geekbox.c b/board/geekbuying/geekbox/geekbox.c
index 10b04a1..b0f9a5f 100644
--- a/board/geekbuying/geekbox/geekbox.c
+++ b/board/geekbuying/geekbox/geekbox.c
@@ -4,8 +4,3 @@
  */
 
 #include <common.h>
-
-int board_init(void)
-{
-	return 0;
-}
diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c
index b116b1a..b6b4f19 100644
--- a/board/google/gru/gru.c
+++ b/board/google/gru/gru.c
@@ -5,12 +5,28 @@
 
 #include <common.h>
 
-int board_init(void)
+#ifdef CONFIG_SPL_BUILD
+/* provided to defeat compiler optimisation in board_init_f() */
+void gru_dummy_function(int i)
 {
-	return 0;
 }
 
-/* provided to defeat compiler optimisation in board_init_f() */
-void gru_dummy_function(int i)
+int board_early_init_f(void)
 {
+# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
+	int sum, i;
+
+	/*
+	 * Add a delay and ensure that the compiler does not optimise this out.
+	 * This is needed since the power rails tail a while to turn on, and
+	 * we get garbage serial output otherwise.
+	 */
+	sum = 0;
+	for (i = 0; i < 150000; i++)
+		sum += i;
+	gru_dummy_function(sum);
+#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
+
+	return 0;
 }
+#endif
diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c
index 19edb18..dd2c014 100644
--- a/board/google/veyron/veyron.c
+++ b/board/google/veyron/veyron.c
@@ -3,10 +3,93 @@
  * (C) Copyright 2015 Google, Inc
  */
 
+#include <clk.h>
 #include <common.h>
+#include <dm.h>
+#include <asm/arch-rockchip/clock.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include <power/regulator.h>
 
 /*
  * We should increase the DDR voltage to 1.2V using the PWM regulator.
  * There is a U-Boot driver for this but it may need to add support for the
  * 'voltage-table' property.
  */
+#ifndef CONFIG_SPL_BUILD
+#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
+static int veyron_init(void)
+{
+	struct udevice *dev;
+	struct clk clk;
+	int ret;
+
+	ret = regulator_get_by_platname("vdd_arm", &dev);
+	if (ret) {
+		debug("Cannot set regulator name\n");
+		return ret;
+	}
+
+	/* Slowly raise to max CPU voltage to prevent overshoot */
+	ret = regulator_set_value(dev, 1200000);
+	if (ret)
+		return ret;
+	udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
+	ret = regulator_set_value(dev, 1400000);
+	if (ret)
+		return ret;
+	udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
+
+	ret = rockchip_get_clk(&clk.dev);
+	if (ret)
+		return ret;
+	clk.id = PLL_APLL;
+	ret = clk_set_rate(&clk, 1800000000);
+	if (IS_ERR_VALUE(ret))
+		return ret;
+
+	ret = regulator_get_by_platname("vcc33_sd", &dev);
+	if (ret) {
+		debug("Cannot get regulator name\n");
+		return ret;
+	}
+
+	ret = regulator_set_value(dev, 3300000);
+	if (ret)
+		return ret;
+
+	ret = regulators_enable_boot_on(false);
+	if (ret) {
+		debug("%s: Cannot enable boot on regulators\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	struct udevice *dev;
+	int ret;
+
+#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
+	if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
+		ret = veyron_init();
+		if (ret)
+			return ret;
+	}
+#endif
+	/*
+	 * This init is done in SPL, but when chain-loading U-Boot SPL will
+	 * have been skipped. Allow the clock driver to check if it needs
+	 * setting up.
+	 */
+	ret = rockchip_get_clk(&dev);
+	if (ret) {
+		debug("CLK init failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+#endif
diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c
index ffe1833..92f3bd2 100644
--- a/board/phytec/phycore_rk3288/phycore-rk3288.c
+++ b/board/phytec/phycore_rk3288/phycore-rk3288.c
@@ -8,10 +8,13 @@
 #include <common.h>
 #include <dm.h>
 #include <environment.h>
+#include <fdtdec.h>
 #include <i2c.h>
 #include <i2c_eeprom.h>
 #include <netdev.h>
 #include "som.h"
+#include <power/regulator.h>
+#include <power/rk8xx_pmic.h>
 
 static int valid_rk3288_som(struct rk3288_som *som)
 {
@@ -27,7 +30,7 @@ static int valid_rk3288_som(struct rk3288_som *som)
 	return hw == som->bs;
 }
 
-int rk_board_late_init(void)
+int rk3288_board_late_init(void)
 {
 	int ret;
 	struct udevice *dev;
@@ -68,3 +71,47 @@ int rk_board_late_init(void)
 
 	return 0;
 }
+
+#ifdef CONFIG_SPL_BUILD
+#if !defined(CONFIG_SPL_OF_PLATDATA)
+static int phycore_init(void)
+{
+	struct udevice *pmic;
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
+	if (ret)
+		return ret;
+
+#if defined(CONFIG_SPL_POWER_SUPPORT)
+	/* Increase USB input current to 2A */
+	ret = rk818_spl_configure_usb_input_current(pmic, 2000);
+	if (ret)
+		return ret;
+
+	/* Close charger when USB lower then 3.26V */
+	ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+#if !defined(CONFIG_SPL_OF_PLATDATA)
+	int ret;
+
+	if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
+		ret = phycore_init();
+		if (ret) {
+			debug("Failed to set up phycore power settings: %d\n",
+			      ret);
+			return;
+		}
+	}
+#endif
+}
+#endif
diff --git a/board/rockchip/evb_px5/evb-px5.c b/board/rockchip/evb_px5/evb-px5.c
index 53e753f..b81f970 100644
--- a/board/rockchip/evb_px5/evb-px5.c
+++ b/board/rockchip/evb_px5/evb-px5.c
@@ -2,9 +2,3 @@
 /*
  * Copyright (c) 2017 Andy Yan
  */
-#include <common.h>
-
-int board_init(void)
-{
-	return 0;
-}
diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c
index bc9ef5e..779bc64 100644
--- a/board/rockchip/evb_rk3328/evb-rk3328.c
+++ b/board/rockchip/evb_rk3328/evb-rk3328.c
@@ -3,68 +3,3 @@
  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  */
 
-#include <common.h>
-#include <asm/armv8/mmu.h>
-#include <dwc3-uboot.h>
-#include <power/regulator.h>
-#include <usb.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-	int ret;
-
-	ret = regulators_enable_boot_on(false);
-	if (ret)
-		debug("%s: Cannot enable boot on regulator\n", __func__);
-
-	return ret;
-}
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3328_otg_data = {
-	.rx_fifo_sz	= 512,
-	.np_tx_fifo_sz	= 16,
-	.tx_fifo_sz	= 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	int node;
-	const char *mode;
-	bool matched = false;
-	const void *blob = gd->fdt_blob;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3328-usb");
-
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-					"rockchip,rk3328-usb");
-	}
-	if (!matched) {
-		debug("Not found usb_otg device\n");
-		return -ENODEV;
-	}
-
-	rk3328_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-	return dwc2_udc_probe(&rk3328_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return 0;
-}
-#endif
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c
index eb1b832..b9049ab 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -5,19 +5,15 @@
 
 #include <common.h>
 #include <dm.h>
-#include <dm/pinctrl.h>
 #include <asm/arch-rockchip/periph.h>
 #include <power/regulator.h>
 
-int board_init(void)
+#ifndef CONFIG_SPL_BUILD
+int board_early_init_f(void)
 {
 	struct udevice *regulator;
 	int ret;
 
-	ret = regulators_enable_boot_on(false);
-	if (ret)
-		debug("%s: Cannot enable boot on regulator\n", __func__);
-
 	ret = regulator_get_by_platname("vcc5v0_host", &regulator);
 	if (ret) {
 		debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
@@ -25,11 +21,10 @@ int board_init(void)
 	}
 
 	ret = regulator_set_enable(regulator, true);
-	if (ret) {
-		debug("%s vcc5v0-host-en set fail!\n", __func__);
-		goto out;
-	}
+	if (ret)
+		debug("%s vcc5v0-host-en set fail! ret %d\n", __func__, ret);
 
 out:
 	return 0;
 }
+#endif
diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c
index 457b110..733f293 100644
--- a/board/rockchip/evb_rv1108/evb_rv1108.c
+++ b/board/rockchip/evb_rv1108/evb_rv1108.c
@@ -47,23 +47,9 @@ int mach_cpu_init(void)
 	return 0;
 }
 
-
-int board_init(void)
-{
-	return 0;
-}
-
 int dram_init(void)
 {
 	gd->ram_size = 0x8000000;
 
 	return 0;
 }
-
-int dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = 0x60000000;
-	gd->bd->bi_dram[0].size = 0x8000000;
-
-	return 0;
-}
diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c
index 9bb93c7..b81f970 100644
--- a/board/rockchip/sheep_rk3368/sheep_rk3368.c
+++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c
@@ -2,18 +2,3 @@
 /*
  * Copyright (c) 2017 Andy Yan
  */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/grf_rk3368.h>
-#include <syscon.h>
-
-int mach_cpu_init(void)
-{
-	return 0;
-}
-
-int board_init(void)
-{
-	return 0;
-}
diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c b/board/rockchip/tinker_rk3288/tinker-rk3288.c
index 44f1318..e6b018d 100644
--- a/board/rockchip/tinker_rk3288/tinker-rk3288.c
+++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c
@@ -21,7 +21,7 @@ static int get_ethaddr_from_eeprom(u8 *addr)
 	return i2c_eeprom_read(dev, 0, addr, 6);
 }
 
-int rk_board_late_init(void)
+int rk3288_board_late_init(void)
 {
 	u8 ethaddr[6];
 
diff --git a/board/theobroma-systems/lion_rk3368/lion_rk3368.c b/board/theobroma-systems/lion_rk3368/lion_rk3368.c
index 6cd5a5f..1b0d504 100644
--- a/board/theobroma-systems/lion_rk3368/lion_rk3368.c
+++ b/board/theobroma-systems/lion_rk3368/lion_rk3368.c
@@ -2,21 +2,3 @@
 /*
  * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
  */
-#include <common.h>
-#include <dm.h>
-#include <ram.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/grf_rk3368.h>
-#include <asm/arch-rockchip/timer.h>
-#include <syscon.h>
-
-int mach_cpu_init(void)
-{
-	return 0;
-}
-
-int board_init(void)
-{
-	return 0;
-}
diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
index 251cd2d..a7e7f02 100644
--- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
+++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
@@ -21,21 +21,6 @@
 #include <power/regulator.h>
 #include <u-boot/sha256.h>
 
-int board_init(void)
-{
-	int ret;
-
-	/*
-	 * We need to call into regulators_enable_boot_on() again, as the call
-	 * during SPL may have not included all regulators.
-	 */
-	ret = regulators_enable_boot_on(false);
-	if (ret)
-		debug("%s: Cannot enable boot on regulator\n", __func__);
-
-	return 0;
-}
-
 static void setup_macaddr(void)
 {
 #if CONFIG_IS_ENABLED(CMD_NET)
diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c
index 2eb7120..68a127b 100644
--- a/board/vamrs/rock960_rk3399/rock960-rk3399.c
+++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c
@@ -2,18 +2,3 @@
 /*
  * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  */
-
-#include <common.h>
-#include <dm.h>
-#include <power/regulator.h>
-
-int board_init(void)
-{
-	int ret;
-
-	ret = regulators_enable_boot_on(false);
-	if (ret)
-		debug("%s: Cannot enable boot on regulator\n", __func__);
-
-	return 0;
-}
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index 9bb9959..dda686c 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -562,6 +562,9 @@ static int rk3188_clk_probe(struct udevice *dev)
 #endif
 
 	rkclk_init(priv->cru, priv->grf, priv->has_bwadj);
+
+	/* Init CPU frequency */
+	rkclk_configure_cpu(priv->cru, priv->grf, APLL_HZ, priv->has_bwadj);
 #endif
 
 	return 0;
diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
index 20d6243..d12696d 100644
--- a/include/configs/rk3128_common.h
+++ b/include/configs/rk3128_common.h
@@ -19,6 +19,8 @@
 #define CONFIG_SYS_ARCH_TIMER
 #define CONFIG_SYS_HZ_CLOCK		24000000
 
+#define CONFIG_IRAM_BASE		0x10080000
+
 #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
 #define CONFIG_SYS_LOAD_ADDR		0x60800800
 
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index 1d41702..92524b0 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -15,8 +15,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
 /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
 #endif
@@ -25,6 +23,7 @@
 
 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE	(0x8000 - 0x800)
 #define CONFIG_ROCKCHIP_CHIP_TAG	"RK31"
+#define CONFIG_IRAM_BASE	0x10080000
 
 /* spl size 32kb sram - 2kb bootrom */
 #define CONFIG_SPL_MAX_SIZE		(0x8000 - 0x800)
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index cc08699..9582cdf 100644
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -24,6 +24,7 @@
 
 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE	(28 << 10)
 #define CONFIG_ROCKCHIP_CHIP_TAG	"RK32"
+#define CONFIG_IRAM_BASE		0x10080000
 
 #define CONFIG_SYS_SDRAM_BASE		0x60000000
 #define SDRAM_BANK_SIZE			(512UL << 20UL)
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 5472a90..da10e29 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -9,6 +9,8 @@
 #include <asm/arch-rockchip/hardware.h>
 #include "rockchip-common.h"
 
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* 16MB */
+
 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
@@ -25,6 +27,8 @@
 #define CONFIG_SYS_LOAD_ADDR		0x00800800
 #define CONFIG_SPL_STACK		0xff718000
 
+#define CONFIG_IRAM_BASE		0xff700000
+
 /* RAW SD card / eMMC locations. */
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	(128 << 10)
 
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index 2a81c80..6ed7525 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -8,12 +8,14 @@
 
 #include "rockchip-common.h"
 
+#define CONFIG_IRAM_BASE		0xff090000
+
+#define CONFIG_ROCKCHIP_STIMER_BASE    0xff1d0020
+
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
 #define CONFIG_SYS_LOAD_ADDR		0x00800800
 #define CONFIG_SPL_STACK		0x00400000
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index 8a1e311..340413d 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -23,7 +23,7 @@
 #define CONFIG_ROCKCHIP_STIMER_BASE	0xff830020
 #define COUNTER_FREQUENCY		24000000
 
-#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_IRAM_BASE		0xff8c0000
 
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
 #define CONFIG_SYS_LOAD_ADDR		0x00280000
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 8df0180..12ad60d 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -15,7 +15,7 @@
 #define COUNTER_FREQUENCY               24000000
 #define CONFIG_ROCKCHIP_STIMER_BASE	0xff8680a0
 
-#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_IRAM_BASE		0xff8c0000
 
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
 #define CONFIG_SYS_LOAD_ADDR		0x00800800
diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index 6f61f01..691aa51 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -8,6 +8,8 @@
 #include <asm/arch-rockchip/hardware.h>
 #include "rockchip-common.h"
 
+#define CONFIG_IRAM_BASE		0x10080000
+
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT