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| author | Pali Rohár <pali@kernel.org> | 2022-05-01 17:45:58 +0200 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2022-06-20 09:18:26 +0800 |
| commit | 02c8fbdb8d41cfa81e2df990da8151ea93bb2f7e (patch) | |
| tree | e221b329001355911829a3541a43ec146760e1f0 | |
| parent | 20fb58fc5a1c83ee0085b2e9f7ecda8b761a5592 (diff) | |
| download | u-boot-02c8fbdb8d41cfa81e2df990da8151ea93bb2f7e.zip u-boot-02c8fbdb8d41cfa81e2df990da8151ea93bb2f7e.tar.gz u-boot-02c8fbdb8d41cfa81e2df990da8151ea93bb2f7e.tar.bz2 | |
powerpc: fsl_law: Add definition for first PCIe target interface
Header file asm/fsl_law.h already provides correct definition for second
and third PCIe controller (LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3). But
is missing definition for the first PCIe controller (LAW_TRGT_IF_PCIE_1).
Note that existing definition for LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3
are slightly complicated, but are really correct for P2020 platform.
Signed-off-by: Pali Rohár <pali@kernel.org>
| -rw-r--r-- | arch/powerpc/include/asm/fsl_law.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 39fbc04..9e2f2d5 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -78,6 +78,7 @@ enum law_trgt_if { enum law_trgt_if { LAW_TRGT_IF_PCI = 0x00, LAW_TRGT_IF_PCI_2 = 0x01, + LAW_TRGT_IF_PCIE_1 = 0x02, #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) LAW_TRGT_IF_OCN_DSP = 0x03, #else |