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| author | Tom Rini <trini@konsulko.com> | 2023-04-05 19:48:55 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-04-25 15:31:27 -0400 |
| commit | b5fc9f99d0d5324b6159b3a1da7bb679cf5fc901 (patch) | |
| tree | 6200bba7c82ba8084a8a271051cc19fe5b0f7974 | |
| parent | a27c8ea7f7fc269c2bf40468568a387d9e8db976 (diff) | |
| download | u-boot-b5fc9f99d0d5324b6159b3a1da7bb679cf5fc901.zip u-boot-b5fc9f99d0d5324b6159b3a1da7bb679cf5fc901.tar.gz u-boot-b5fc9f99d0d5324b6159b3a1da7bb679cf5fc901.tar.bz2 | |
armv7: Use isb/dsb directly in start.S
Toolchains which do not directly support using "isb" and "dsb" directly
are no longer functionally supported in U-Boot. Furthermore, clang has
for a long time warned about using the alternate form that we were.
Update the code.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7d7aac0..69e281b 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -134,8 +134,8 @@ ENTRY(c_runtime_cpu_setup) */ #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) mcr p15, 0, r0, c7, c5, 0 @ invalidate icache - mcr p15, 0, r0, c7, c10, 4 @ DSB - mcr p15, 0, r0, c7, c5, 4 @ ISB + dsb + isb #endif bx lr @@ -188,8 +188,8 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs mcr p15, 0, r0, c7, c5, 0 @ invalidate icache mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array - mcr p15, 0, r0, c7, c10, 4 @ DSB - mcr p15, 0, r0, c7, c5, 4 @ ISB + dsb + isb /* * disable MMU stuff and caches |