diff options
author | Tom Rini <trini@konsulko.com> | 2023-02-17 09:03:35 -0500 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2023-02-17 09:03:35 -0500 |
commit | 0aa9470fdf8386c18ade43506d5541a515318b76 (patch) | |
tree | 11c69dcbeb37cf5f268169d6beac1b685f98b28c | |
parent | faac9dee8e0629326dc122f4624fc4897e3f38b0 (diff) | |
parent | 7574b6476afc1fd76816be6567458f6ca4f44234 (diff) | |
download | u-boot-0aa9470fdf8386c18ade43506d5541a515318b76.zip u-boot-0aa9470fdf8386c18ade43506d5541a515318b76.tar.gz u-boot-0aa9470fdf8386c18ade43506d5541a515318b76.tar.bz2 |
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- binman: Add help message if opensbi is absent when building u-boot SPL
- AndesTech: rename cpu and board name to 'andesv5' and 'ae350'
- Clean up cache operation for Andes ae350 platform
32 files changed, 331 insertions, 321 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ebc4bef..48ca4ff 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -8,8 +8,8 @@ choice prompt "Target select" optional -config TARGET_AX25_AE350 - bool "Support ax25-ae350" +config TARGET_AE350 + bool "Support ae350" config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" @@ -58,7 +58,7 @@ config SPL_SYS_DCACHE_OFF Do not enable data cache in SPL. # board-specific options below -source "board/AndesTech/ax25-ae350/Kconfig" +source "board/AndesTech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" @@ -67,7 +67,7 @@ source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" # platform-specific options below -source "arch/riscv/cpu/ax25/Kconfig" +source "arch/riscv/cpu/andesv5/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/andesv5/Kconfig index 4a7295d..82bb5a2 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/andesv5/Kconfig @@ -6,19 +6,10 @@ config RISCV_NDS imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE) + imply V5L2_CACHE imply SPL_CPU imply SPL_OPENSBI imply SPL_LOAD_FIT help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. - -if RISCV_NDS - -config RISCV_NDS_CACHE - bool "AndeStar V5 families specific cache support" - depends on RISCV_MMODE || SPL_RISCV_MMODE - help - Provide Andes Technology AndeStar V5 families specific cache support. - -endif diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/andesv5/Makefile index 35a1a2f..35a1a2f 100644 --- a/arch/riscv/cpu/ax25/Makefile +++ b/arch/riscv/cpu/andesv5/Makefile diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andesv5/cache.c new file mode 100644 index 0000000..40d77f6 --- /dev/null +++ b/arch/riscv/cpu/andesv5/cache.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <rick@andestech.com> + */ + +#include <asm/csr.h> +#include <asm/asm.h> +#include <common.h> +#include <cache.h> +#include <cpu_func.h> +#include <dm.h> +#include <dm/uclass-internal.h> +#include <asm/arch-andes/csr.h> + +#ifdef CONFIG_V5L2_CACHE +void enable_caches(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CACHE, + DM_DRIVER_GET(v5l2_cache), + &dev); + if (ret) { + log_debug("Cannot enable v5l2 cache\n"); + } else { + ret = cache_enable(dev); + if (ret) + log_debug("v5l2 cache enable failed\n"); + } +} + +static void cache_ops(int (*ops)(struct udevice *dev)) +{ + struct udevice *dev = NULL; + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + ops(dev); +} +#endif + +void flush_dcache_all(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); +#endif +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + +void icache_enable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrsi %0, 0x1" :: "i"(CSR_MCACHE_CTL)); +#endif +} + +void icache_disable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrci %0, 0x1" :: "i"(CSR_MCACHE_CTL)); +#endif +} + +void dcache_enable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL)); +#endif + +#ifdef CONFIG_V5L2_CACHE + cache_ops(cache_enable); +#endif +} + +void dcache_disable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL)); +#endif + +#ifdef CONFIG_V5L2_CACHE + cache_ops(cache_disable); +#endif +} + +int icache_status(void) +{ + int ret = 0; + +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile ( + "csrr t1, %1\n\t" + "andi %0, t1, 0x01\n\t" + : "=r" (ret) + : "i"(CSR_MCACHE_CTL) + : "memory" + ); +#endif + + return !!ret; +} + +int dcache_status(void) +{ + int ret = 0; + +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile ( + "csrr t1, %1\n\t" + "andi %0, t1, 0x02\n\t" + : "=r" (ret) + : "i" (CSR_MCACHE_CTL) + : "memory" + ); +#endif + + return !!ret; +} diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c new file mode 100644 index 0000000..06e379b --- /dev/null +++ b/arch/riscv/cpu/andesv5/cpu.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <rick@andestech.com> + */ + +/* CPU specific code */ +#include <common.h> +#include <cpu_func.h> +#include <irq_func.h> +#include <asm/cache.h> +#include <asm/csr.h> +#include <asm/arch-andes/csr.h> + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + cache_flush(); + + return 0; +} + +void harts_early_init(void) +{ + /* Enable I/D-cache in SPL */ + if (CONFIG_IS_ENABLED(RISCV_MMODE)) { + unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + + mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN | + MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN); + + csr_write(CSR_MCACHE_CTL, mcache_ctl_val); + + /* + * Check mcache_ctl.DC_COHEN, we assume this platform does + * not support CM if the bit is hard-wired to 0. + */ + if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { + /* Wait for DC_COHSTA bit to be set */ + while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); + } + } +} diff --git a/arch/riscv/cpu/ax25/spl.c b/arch/riscv/cpu/andesv5/spl.c index 4138490..4138490 100644 --- a/arch/riscv/cpu/ax25/spl.c +++ b/arch/riscv/cpu/andesv5/spl.c diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c deleted file mode 100644 index 35f23c7..0000000 --- a/arch/riscv/cpu/ax25/cache.c +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation <rick@andestech.com> - */ - -#include <common.h> -#include <cpu_func.h> -#include <dm.h> -#include <asm/cache.h> -#include <dm/uclass-internal.h> -#include <cache.h> -#include <asm/csr.h> - -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) -/* mcctlcommand */ -#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc - -/* D-cache operation */ -#define CCTL_L1D_WBINVAL_ALL 6 -#endif -#endif - -#ifdef CONFIG_V5L2_CACHE -static void _cache_enable(void) -{ - struct udevice *dev = NULL; - - uclass_find_first_device(UCLASS_CACHE, &dev); - - if (dev) - cache_enable(dev); -} - -static void _cache_disable(void) -{ - struct udevice *dev = NULL; - - uclass_find_first_device(UCLASS_CACHE, &dev); - - if (dev) - cache_disable(dev); -} -#endif - -void flush_dcache_all(void) -{ -#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); -#endif -#endif -#endif -} - -void flush_dcache_range(unsigned long start, unsigned long end) -{ - flush_dcache_all(); -} - -void invalidate_dcache_range(unsigned long start, unsigned long end) -{ - flush_dcache_all(); -} - -void icache_enable(void) -{ -#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "ori t0, t1, 0x1\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#endif -#endif -} - -void icache_disable(void) -{ -#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "fence.i\n\t" - "csrr t1, mcache_ctl\n\t" - "andi t0, t1, ~0x1\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#endif -#endif -} - -void dcache_enable(void) -{ -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "ori t0, t1, 0x2\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#ifdef CONFIG_V5L2_CACHE - _cache_enable(); -#endif -#endif -#endif -} - -void dcache_disable(void) -{ -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "andi t0, t1, ~0x2\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#ifdef CONFIG_V5L2_CACHE - _cache_disable(); -#endif -#endif -#endif -} - -int icache_status(void) -{ - int ret = 0; - -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "andi %0, t1, 0x01\n\t" - : "=r" (ret) - : - : "memory" - ); -#endif -#endif - - return ret; -} - -int dcache_status(void) -{ - int ret = 0; - -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "andi %0, t1, 0x02\n\t" - : "=r" (ret) - : - : "memory" - ); -#endif -#endif - - return ret; -} diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c deleted file mode 100644 index a46674f..0000000 --- a/arch/riscv/cpu/ax25/cpu.c +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation <rick@andestech.com> - */ - -/* CPU specific code */ -#include <common.h> -#include <cpu_func.h> -#include <irq_func.h> -#include <asm/cache.h> -#include <asm/csr.h> - -#define CSR_MCACHE_CTL 0x7ca -#define CSR_MMISC_CTL 0x7d0 -#define CSR_MARCHID 0xf12 - -#define V5_MCACHE_CTL_IC_EN_OFFSET 0 -#define V5_MCACHE_CTL_DC_EN_OFFSET 1 -#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8 -#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19 -#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20 - -#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET) -#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET) -#define V5_MCACHE_CTL_CCTL_SUEN BIT(V5_MCACHE_CTL_CCTL_SUEN_OFFSET) -#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET) -#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET) - - -/* - * cleanup_before_linux() is called just before we call linux - * it prepares the processor for linux - * - * we disable interrupt and caches. - */ -int cleanup_before_linux(void) -{ - disable_interrupts(); - - /* turn off I/D-cache */ - cache_flush(); - icache_disable(); - dcache_disable(); - - return 0; -} - -void harts_early_init(void) -{ - if (CONFIG_IS_ENABLED(RISCV_MMODE)) { - unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); - - if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) - mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN; - if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN)) - mcache_ctl_val |= V5_MCACHE_CTL_IC_EN; - if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN)) - mcache_ctl_val |= V5_MCACHE_CTL_DC_EN; - if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN)) - mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN; - csr_write(CSR_MCACHE_CTL, mcache_ctl_val); - - /* - * Check DC_COHEN_EN, if cannot write to mcache_ctl, - * we assume this bitmap not support L2 CM - */ - mcache_ctl_val = csr_read(CSR_MCACHE_CTL); - if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) { - /* Wait for DC_COHSTA bit be set */ - while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN)) - mcache_ctl_val = csr_read(CSR_MCACHE_CTL); - } - } -} diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 5c15a0f..c576c55 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 96ef8bd..61af6d5 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -112,7 +112,7 @@ }; L2: l2-cache@e0500000 { - compatible = "v5l2cache"; + compatible = "cache"; cache-level = <2>; cache-size = <0x40000>; reg = <0xe0500000 0x40000>; diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index cddbaec..8c7db29 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -112,7 +112,7 @@ }; L2: l2-cache@e0500000 { - compatible = "v5l2cache"; + compatible = "cache"; cache-level = <2>; cache-size = <0x40000>; reg = <0x0 0xe0500000 0x0 0x40000>; diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index b8fc8f7..156cb00 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -45,6 +45,7 @@ opensbi_blob: opensbi { filename = "fw_dynamic.bin"; + missing-msg = "opensbi"; }; }; diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h new file mode 100644 index 0000000..c7ed920 --- /dev/null +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + */ + +#ifndef _ASM_ANDES_CSR_H +#define _ASM_ANDES_CSR_H + +#include <asm/asm.h> +#include <linux/const.h> + +#define CSR_MCACHE_CTL 0x7ca +#define CSR_MMISC_CTL 0x7d0 +#define CSR_MARCHID 0xf12 +#define CSR_MCCTLCOMMAND 0x7cc + +#define MCACHE_CTL_IC_EN_OFFSET 0 +#define MCACHE_CTL_DC_EN_OFFSET 1 +#define MCACHE_CTL_CCTL_SUEN_OFFSET 8 +#define MCACHE_CTL_DC_COHEN_OFFSET 19 +#define MCACHE_CTL_DC_COHSTA_OFFSET 20 + +#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET) +#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET) +#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET) +#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET) +#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET) + +#define CCTL_L1D_WBINVAL_ALL 6 + +#endif /* _ASM_ANDES_CSR_H */ diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 6fdc86d..31ba726 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -22,7 +22,7 @@ struct arch_global_data { void __iomem *clint; /* clint base address */ #endif #ifdef CONFIG_ANDES_PLICSW - void __iomem *plicsw; /* plic base address */ + void __iomem *plicsw; /* andes plicsw base address */ #endif #if CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS]; diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ae350/Kconfig index 4bb33b0..75815bf 100644 --- a/board/AndesTech/ax25-ae350/Kconfig +++ b/board/AndesTech/ae350/Kconfig @@ -1,10 +1,10 @@ -if TARGET_AX25_AE350 +if TARGET_AE350 config SYS_CPU - default "ax25" + default "andesv5" config SYS_BOARD - default "ax25-ae350" + default "ae350" config SYS_VENDOR default "AndesTech" @@ -13,7 +13,7 @@ config SYS_SOC default "ae350" config SYS_CONFIG_NAME - default "ax25-ae350" + default "ae350" config ENV_SIZE default 0x2000 if ENV_IS_IN_SPI_FLASH diff --git a/board/AndesTech/ax25-ae350/MAINTAINERS b/board/AndesTech/ae350/MAINTAINERS index eebee16..ead8e0e 100644 --- a/board/AndesTech/ax25-ae350/MAINTAINERS +++ b/board/AndesTech/ae350/MAINTAINERS @@ -1,8 +1,8 @@ -AX25-AE350 BOARD +AE350 BOARD M: Rick Chen <rick@andestech.com> S: Maintained -F: board/AndesTech/ax25-ae350/ -F: include/configs/ax25-ae350.h +F: board/AndesTech/ae350/ +F: include/configs/ae350.h F: configs/ae350_rv32_defconfig F: configs/ae350_rv64_defconfig F: configs/ae350_rv32_xip_defconfig diff --git a/board/AndesTech/ax25-ae350/Makefile b/board/AndesTech/ae350/Makefile index 0e4ba8d..705ae43 100644 --- a/board/AndesTech/ax25-ae350/Makefile +++ b/board/AndesTech/ae350/Makefile @@ -3,4 +3,4 @@ # Copyright (C) 2017 Andes Technology Corporation. # Rick Chen, Andes Technology Corporation <rick@andestech.com> -obj-y := ax25-ae350.o +obj-y := ae350.o diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ae350/ae350.c index 63a966e..1c2288b 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ae350/ae350.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <cpu_func.h> #include <flash.h> #include <image.h> #include <init.h> @@ -72,6 +73,14 @@ void *board_fdt_blob_setup(int *err) return NULL; } +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init() +{ + /* enable v5l2 cache */ + enable_caches(); +} +#endif + int smc_init(void) { int node = -1; @@ -96,18 +105,10 @@ int smc_init(void) return 0; } -static void v5l2_init(void) -{ - struct udevice *dev; - - uclass_get_device(UCLASS_CACHE, 0, &dev); -} - #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { smc_init(); - v5l2_init(); return 0; } diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index e5c8358..953cd07 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80 @@ -14,6 +14,8 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 @@ -26,6 +28,7 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index a66db65..61475d1 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -1,27 +1,31 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x01200000 +CONFIG_TEXT_BASE=0x01800000 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00 CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y @@ -32,6 +36,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 606962c..b505cec 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -1,7 +1,9 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x01200000 +CONFIG_TEXT_BASE=0x01800000 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SPL_TEXT_BASE=0x80000000 @@ -9,20 +11,22 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00 CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y @@ -33,6 +37,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index 069a9d3..9266321 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_XIP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -15,6 +15,8 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 @@ -27,6 +29,7 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index c373b99..3c18562 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_ARCH_RV64I=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -14,6 +14,8 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 @@ -26,6 +28,7 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index f235db7..36a6d04 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -1,27 +1,31 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x01200000 +CONFIG_TEXT_BASE=0x01800000 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y @@ -32,6 +36,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 4cbfd52..0b70e85 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -1,7 +1,9 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x01200000 +CONFIG_TEXT_BASE=0x01800000 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_TEXT_BASE=0x80000000 @@ -9,20 +11,22 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y @@ -33,6 +37,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index 4fed2ea..0d467b9 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_ARCH_RV64I=y CONFIG_XIP=y CONFIG_DISTRO_DEFAULTS=y @@ -15,6 +15,8 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 @@ -27,6 +29,7 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/doc/board/AndesTech/ax25-ae350.rst b/doc/board/AndesTech/ae350.rst index b46f427..42a2b4d 100644 --- a/doc/board/AndesTech/ax25-ae350.rst +++ b/doc/board/AndesTech/ae350.rst @@ -1,20 +1,20 @@ .. SPDX-License-Identifier: GPL-2.0+ -AX25-AE350 -========== +AE350 +====== -AE350 is the mainline SoC produced by Andes Technology using AX25 CPU core -base on RISC-V architecture. +AE350 is the mainline SoC produced by Andes Technology using AndesV5 CPU core +based on RISC-V architecture. AE350 has integrated both AHB and APB bus and many periphals for application and product development. -AX25-AE350 is the SoC with AE350 hardcore CPU. +AndesV5 is Andes CPU IP family that adopts RISC-V architecture. -AX25 is Andes CPU IP to adopt RISC-V architecture. +AndesV5 family includes 25, 27, 45 series. -AX25 Features -------------- +25-Series Features +------------------ CPU Core - 5-stage in-order execution pipeline diff --git a/doc/board/AndesTech/index.rst b/doc/board/AndesTech/index.rst index d8f7d15..cacc579 100644 --- a/doc/board/AndesTech/index.rst +++ b/doc/board/AndesTech/index.rst @@ -7,4 +7,4 @@ Andes Tech :maxdepth: 2 adp-ag101p - ax25-ae350 + ae350 diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 40f41a8..6cb8c3e 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -25,7 +25,6 @@ config L2X0_CACHE config V5L2_CACHE bool "Andes V5L2 cache driver" select CACHE - depends on RISCV_NDS_CACHE help Support Andes V5L2 cache controller in AE350 platform. It will configure tag and data ram timing control from the diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c index bbdb76b..eda07d3 100644 --- a/drivers/cache/cache-v5l2.c +++ b/drivers/cache/cache-v5l2.c @@ -34,6 +34,14 @@ struct l2cache { volatile u64 cctl_status; }; +/* Configuration register */ +#define MEM_MAP_OFF 20 +#define MEM_MAP_MSK BIT(MEM_MAP_OFF) +/* offset of v0 memory map (Gen1) */ +static u32 cmd_stride = 0x10; +static u32 status_stride = 0x0; +static u32 status_bit_offset = 0x4; + /* Control Register */ #define L2_ENABLE 0x1 /* prefetch */ @@ -53,14 +61,15 @@ struct l2cache { #define DRAMICTL_MSK BIT(DRAMICTL_OFF) /* CCTL Command Register */ -#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10) +#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * (cmd_stride)) #define L2_WBINVAL_ALL 0x12 /* CCTL Status Register */ -#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4)) -#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4)) -#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4)) -#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4)) +#define CCTL_STATUS_REG(base, hart) ((ulong)(base) + 0x80 + (hart) * (status_stride)) +#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * (status_bit_offset))) +#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * (status_bit_offset))) +#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * (status_bit_offset))) +#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * (status_bit_offset))) DECLARE_GLOBAL_DATA_PTR; @@ -110,7 +119,7 @@ static int v5l2_of_to_plat(struct udevice *dev) struct v5l2_plat *plat = dev_get_plat(dev); struct l2cache *regs; - regs = (struct l2cache *)dev_read_addr(dev); + regs = (struct l2cache *)(uintptr_t)dev_read_addr(dev); plat->regs = regs; plat->iprefetch = -EINVAL; @@ -133,12 +142,19 @@ static int v5l2_probe(struct udevice *dev) { struct v5l2_plat *plat = dev_get_plat(dev); struct l2cache *regs = plat->regs; - u32 ctl_val; + u32 cfg_val, ctl_val; + cfg_val = readl(®s->configure); ctl_val = readl(®s->control); - if (!(ctl_val & L2_ENABLE)) - ctl_val |= L2_ENABLE; + /* If true, v1 memory map (Gen2) */ + if (cfg_val & MEM_MAP_MSK) { + cmd_stride = 0x1000; + status_stride = 0x1000; + status_bit_offset = 0x0; + } + + ctl_val |= L2_ENABLE; if (plat->iprefetch != -EINVAL) { ctl_val &= ~(IPREPETCH_MSK); @@ -168,7 +184,7 @@ static int v5l2_probe(struct udevice *dev) } static const struct udevice_id v5l2_cache_ids[] = { - { .compatible = "v5l2cache" }, + { .compatible = "cache" }, {} }; diff --git a/include/configs/ax25-ae350.h b/include/configs/ae350.h index b566ecf..b566ecf 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ae350.h diff --git a/tools/binman/missing-blob-help b/tools/binman/missing-blob-help index c61ca02..4448ac9 100644 --- a/tools/binman/missing-blob-help +++ b/tools/binman/missing-blob-help @@ -37,3 +37,9 @@ https://github.com/siemens/k3-rti-wdt. tee-os: See the documentation for your board. You may need to build Open Portable Trusted Execution Environment (OP-TEE) with TEE=/path/to/tee.bin + +opensbi: +See the documentation for your board. The OpenSBI git repo is at +https://github.com/riscv/opensbi.git +You may need to build fw_dynamic.bin first and re-build u-boot with +OPENSBI=/path/to/fw_dynamic.bin |