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authorTim Harvey <tharvey@gateworks.com>2022-11-17 13:27:09 -0800
committerTom Rini <trini@konsulko.com>2022-11-28 10:59:20 -0500
commit3cf8d6d4e8285f9ab7634415ab7f4d37c3cfb2b7 (patch)
treeb9806260783a1172716ddedb0e6ec34d32d42ce6
parentefcb8e8c6313e79c0d781bf58134c8e6dee85742 (diff)
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phy: add driver for Intel XWAY PHYWIP/2022-11-28-networking-updates-and-improvements
Add a driver for the Intel XWAY GbE PHY: - configure RGMII using dt phy-mode and standard delay properties - use genphy_config Signed-off-by: Tim Harvey <tharvey@gateworks.com>
-rw-r--r--drivers/net/phy/Kconfig5
-rw-r--r--drivers/net/phy/Makefile1
-rw-r--r--drivers/net/phy/intel_xway.c48
-rw-r--r--drivers/net/phy/phy.c3
-rw-r--r--include/phy.h1
5 files changed, 58 insertions, 0 deletions
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 52ce08b..86e6981 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -321,6 +321,11 @@ config PHY_XILINX_GMII2RGMII
as bridge between MAC connected over GMII and external phy that
is connected over RGMII interface.
+config PHY_XWAY
+ bool "Intel XWAY PHY support"
+ help
+ This adds support for the Intel XWAY (formerly Lantiq) Gbe PHYs.
+
config PHY_ETHERNET_ID
bool "Read ethernet PHY id"
depends on DM_GPIO
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 9d87eb2..d38e99e 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_PHY_TI_DP83867) += dp83867.o
obj-$(CONFIG_PHY_TI_DP83869) += dp83869.o
obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o
obj-$(CONFIG_PHY_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o
+obj-$(CONFIG_PHY_XWAY) += intel_xway.o
obj-$(CONFIG_PHY_ETHERNET_ID) += ethernet_id.o
obj-$(CONFIG_PHY_VITESSE) += vitesse.o
obj-$(CONFIG_PHY_MSCC) += mscc.o
diff --git a/drivers/net/phy/intel_xway.c b/drivers/net/phy/intel_xway.c
new file mode 100644
index 0000000..dfce3f8
--- /dev/null
+++ b/drivers/net/phy/intel_xway.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <common.h>
+#include <phy.h>
+#include <linux/bitfield.h>
+
+#define XWAY_MDIO_MIICTRL 0x17 /* mii control */
+
+#define XWAY_MDIO_MIICTRL_RXSKEW_MASK GENMASK(14, 12)
+#define XWAY_MDIO_MIICTRL_TXSKEW_MASK GENMASK(10, 8)
+
+static int xway_config(struct phy_device *phydev)
+{
+ ofnode node = phy_get_ofnode(phydev);
+ u32 val = 0;
+
+ if (ofnode_valid(node)) {
+ u32 rx_delay, tx_delay;
+
+ rx_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", 2000);
+ tx_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", 2000);
+ val |= FIELD_PREP(XWAY_MDIO_MIICTRL_TXSKEW_MASK, rx_delay / 500);
+ val |= FIELD_PREP(XWAY_MDIO_MIICTRL_RXSKEW_MASK, tx_delay / 500);
+ phy_modify(phydev, MDIO_DEVAD_NONE, XWAY_MDIO_MIICTRL,
+ XWAY_MDIO_MIICTRL_TXSKEW_MASK |
+ XWAY_MDIO_MIICTRL_RXSKEW_MASK, val);
+ }
+
+ genphy_config_aneg(phydev);
+
+ return 0;
+}
+
+static struct phy_driver XWAY_driver = {
+ .name = "XWAY",
+ .uid = 0xD565A400,
+ .mask = 0xffffff00,
+ .features = PHY_GBIT_FEATURES,
+ .config = xway_config,
+ .startup = genphy_startup,
+ .shutdown = genphy_shutdown,
+};
+
+int phy_xway_init(void)
+{
+ phy_register(&XWAY_driver);
+
+ return 0;
+}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 9087663..92143cf 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -556,6 +556,9 @@ int phy_init(void)
#ifdef CONFIG_PHY_XILINX
phy_xilinx_init();
#endif
+#ifdef CONFIG_PHY_XWAY
+ phy_xway_init();
+#endif
#ifdef CONFIG_PHY_MSCC
phy_mscc_init();
#endif
diff --git a/include/phy.h b/include/phy.h
index 0737c4e..ff69536 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -380,6 +380,7 @@ int phy_teranetics_init(void);
int phy_ti_init(void);
int phy_vitesse_init(void);
int phy_xilinx_init(void);
+int phy_xway_init(void);
int phy_mscc_init(void);
int phy_fixed_init(void);
int phy_ncsi_init(void);