imx6sll: synchronise device tree with linux

Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

4 files changed, 551 insertions, 795 deletions

diff --git a/arch/arm/dts/imx6sll-evk.dts b/arch/arm/dts/imx6sll-evk.dts
index b4af007..32b3d82 100644
--- a/arch/arm/dts/imx6sll-evk.dts
+++ b/arch/arm/dts/imx6sll-evk.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 /dts-v1/;
@@ -16,11 +15,16 @@
 	model = "Freescale i.MX6SLL EVK Board";
 	compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
 
-	memory {
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
 		reg = <0x80000000 0x80000000>;
 	};
 
-	backlight {
+	backlight_display: backlight-display {
 		compatible = "pwm-backlight";
 		pwms = <&pwm1 0 5000000>;
 		brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -28,108 +32,114 @@
 		status = "okay";
 	};
 
-	battery: max8903@0 {
-		compatible = "fsl,max8903-charger";
+	leds {
+		compatible = "gpio-leds";
 		pinctrl-names = "default";
-		dok_input = <&gpio4 13 1>;
-		uok_input = <&gpio4 13 1>;
-		chg_input = <&gpio4 15 1>;
-		flt_input = <&gpio4 14 1>;
-		fsl,dcm_always_high;
-		fsl,dc_valid;
-		fsl,adc_disable;
-		status = "okay";
+		pinctrl-0 = <&pinctrl_led>;
+
+		user {
+			label = "debug";
+			gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
 	};
 
-	pxp_v4l2_out {
-		compatible = "fsl,imx6sl-pxp-v4l2";
-		status = "okay";
+	reg_usb_otg1_vbus: regulator-otg1-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
+		regulator-name = "usb_otg1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
 	};
 
-	regulators {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
+	reg_usb_otg2_vbus: regulator-otg2-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb_otg2_vbus>;
+		regulator-name = "usb_otg2_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
 
-		reg_usb_otg1_vbus: regulator@0 {
-			compatible = "regulator-fixed";
-			reg = <0>;
-			regulator-name = "usb_otg1_vbus";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
-			enable-active-high;
-		};
+	reg_aud3v: regulator-aud3v {
+		compatible = "regulator-fixed";
+		regulator-name = "wm8962-supply-3v15";
+		regulator-min-microvolt = <3150000>;
+		regulator-max-microvolt = <3150000>;
+		regulator-boot-on;
+	};
 
-		reg_usb_otg2_vbus: regulator@1 {
-			compatible = "regulator-fixed";
-			reg = <1>;
-			regulator-name = "usb_otg2_vbus";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
-			enable-active-high;
-		};
+	reg_aud4v: regulator-aud4v {
+		compatible = "regulator-fixed";
+		regulator-name = "wm8962-supply-4v2";
+		regulator-min-microvolt = <4325000>;
+		regulator-max-microvolt = <4325000>;
+		regulator-boot-on;
+	};
 
-		reg_aud3v: regulator@2 {
-			compatible = "regulator-fixed";
-			reg = <2>;
-			regulator-name = "wm8962-supply-3v15";
-			regulator-min-microvolt = <3150000>;
-			regulator-max-microvolt = <3150000>;
-			regulator-boot-on;
-		};
+	reg_lcd_3v3: regulator-lcd-3v3 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
+		regulator-name = "lcd-3v3";
+		gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
 
-		reg_aud4v: regulator@3 {
-			compatible = "regulator-fixed";
-			reg = <3>;
-			regulator-name = "wm8962-supply-4v2";
-			regulator-min-microvolt = <4325000>;
-			regulator-max-microvolt = <4325000>;
-			regulator-boot-on;
-		};
+	reg_lcd_5v: regulator-lcd-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "lcd-5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
 
-		reg_lcd: regulator@4 {
-			compatible = "regulator-fixed";
-			reg = <4>;
-			regulator-name = "lcd-pwr";
-			gpio = <&gpio4 8 0>;
-			enable-active-high;
-		};
+	reg_sd1_vmmc: regulator-sd1-vmmc {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_sd1_vmmc>;
+		regulator-name = "SD1_SPWR";
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+		gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
 
-		reg_sd1_vmmc: sd1_vmmc {
-			compatible = "regulator-fixed";
-			regulator-name = "SD1_SPWR";
-			regulator-min-microvolt = <3000000>;
-			regulator-max-microvolt = <3000000>;
-			gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
-			enable-active-high;
-		};
+	reg_sd3_vmmc: regulator-sd3-vmmc {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_sd3_vmmc>;
+		regulator-name = "SD3_WIFI";
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+		gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
 
-		reg_sd2_vmmc: sd2_vmmc {
-			compatible = "regulator-fixed";
-			regulator-name = "eMMC-VCCQ";
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <1800000>;
-			regulator-boot-on;
-		};
+	panel {
+		compatible = "sii,43wvf1g";
+		backlight = <&backlight_display>;
+		dvdd-supply = <&reg_lcd_3v3>;
+		avdd-supply = <&reg_lcd_5v>;
 
-		reg_sd3_vmmc: sd3_vmmc {
-			compatible = "regulator-fixed";
-			regulator-name = "SD3_WIFI";
-			regulator-min-microvolt = <3000000>;
-			regulator-max-microvolt = <3000000>;
-			gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
-			enable-active-high;
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&display_out>;
+			};
 		};
-
 	};
 
 	sound {
 		compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_hp>;
 		model = "wm8962-audio";
-		cpu-dai = <&ssi2>;
-		audio-codec = <&codec>;
+		audio-cpu = <&ssi2>;
+		audio-codec = <&wm8962>;
 		audio-routing =
 			"Headphone Jack", "HPOUTL",
 			"Headphone Jack", "HPOUTR",
@@ -139,8 +149,7 @@
 			"IN3R", "AMIC";
 		mux-int-port = <2>;
 		mux-ext-port = <3>;
-		codec-master;
-		hp-det-gpios = <&gpio4 24 1>;
+		hp-det-gpio = <&gpio4 24 GPIO_ACTIVE_LOW>;
 	};
 };
 
@@ -150,11 +159,6 @@
 	status = "okay";
 };
 
-&clks {
-	assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
-	assigned-clock-rates = <393216000>;
-};
-
 &cpu0 {
 	arm-supply = <&sw1a_reg>;
 	soc-supply = <&sw1c_reg>;
@@ -166,7 +170,7 @@
 	pinctrl-0 = <&pinctrl_i2c1>;
 	status = "okay";
 
-	pmic: pfuze100@08 {
+	pfuze100: pmic@8 {
 		compatible = "fsl,pfuze100";
 		reg = <0x08>;
 
@@ -211,6 +215,7 @@
 			sw4_reg: sw4 {
 				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
 			};
 
 			swbst_reg: swbst {
@@ -265,76 +270,6 @@
 			};
 		};
 	};
-
-	max17135: max17135@48 {
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_max17135>;
-		compatible = "maxim,max17135";
-		reg = <0x48>;
-		status = "okay";
-
-		vneg_pwrup = <1>;
-		gvee_pwrup = <2>;
-		vpos_pwrup = <10>;
-		gvdd_pwrup = <12>;
-		gvdd_pwrdn = <1>;
-		vpos_pwrdn = <2>;
-		gvee_pwrdn = <8>;
-		vneg_pwrdn = <10>;
-		gpio_pmic_pwrgood = <&gpio2 13 0>;
-		gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
-		gpio_pmic_wakeup = <&gpio2 14 0>;
-		gpio_pmic_v3p3 = <&gpio2 7 0>;
-		gpio_pmic_intr = <&gpio2 12 0>;
-
-		regulators {
-			DISPLAY_reg: DISPLAY {
-				regulator-name = "DISPLAY";
-			};
-
-			GVDD_reg: GVDD {
-				/* 20v */
-				regulator-name = "GVDD";
-			};
-
-			GVEE_reg: GVEE {
-				/* -22v */
-				regulator-name = "GVEE";
-			};
-
-			HVINN_reg: HVINN {
-				/* -22v */
-				regulator-name = "HVINN";
-			};
-
-			HVINP_reg: HVINP {
-				/* 20v */
-				regulator-name = "HVINP";
-			};
-
-			VCOM_reg: VCOM {
-				regulator-name = "VCOM";
-				/* 2's-compliment, -4325000 */
-				regulator-min-microvolt = <0xffbe0178>;
-				/* 2's-compliment, -500000 */
-				regulator-max-microvolt = <0xfff85ee0>;
-			};
-
-			VNEG_reg: VNEG {
-				/* -15v */
-				regulator-name = "VNEG";
-			};
-
-			VPOS_reg: VPOS {
-				/* 15v */
-				regulator-name = "VPOS";
-			};
-
-			V3P3_reg: V3P3 {
-				regulator-name = "V3P3";
-			};
-		};
-	};
 };
 
 &i2c3 {
@@ -343,7 +278,7 @@
 	pinctrl-0 = <&pinctrl_i2c3>;
 	status = "okay";
 
-	codec: wm8962@1a {
+	wm8962: audio-codec@1a {
 		compatible = "wlf,wm8962";
 		reg = <0x1a>;
 		clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>;
@@ -355,365 +290,37 @@
 		PLLVDD-supply = <&vgen3_reg>;
 		SPKVDD1-supply = <&reg_aud4v>;
 		SPKVDD2-supply = <&reg_aud4v>;
-		amic-mono;
 	};
 };
 
-&gpc {
-	fsl,ldo-bypass = <1>;
-};
-
-&iomuxc {
+&lcdif {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_hog>;
-
-	imx6sll-evk {
-		pinctrl_hog: hoggrp {
-			fsl,pins = <
-				MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
-				MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059
-				MX6SLL_PAD_KEY_COL3__GPIO3_IO30	0x17059
-				/*
-				 * Must set the LVE of pad SD2_RESET, otherwise current
-				 * leakage through eMMC chip will pull high the VCCQ to
-				 * 2.6v, which will impact SD1 and SD3 SD3.0 voltage switch.
-				 */
-				MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059
-				MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
-				MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */
-				MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */
-				MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
-				MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
-				/* CHG_FLT, CHG_UOK/DOK, CHG_STATUS */
-				MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
-				MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
-				MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15  0x17000
-			>;
-		};
-
-		pinctrl_audmux3: audmux3grp {
-			fsl,pins = <
-				MX6SLL_PAD_AUD_TXC__AUD3_TXC		0x4130b0
-				MX6SLL_PAD_AUD_TXFS__AUD3_TXFS		0x4130b0
-				MX6SLL_PAD_AUD_TXD__AUD3_TXD		0x4110b0
-				MX6SLL_PAD_AUD_RXD__AUD3_RXD		0x4130b0
-				MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT	0x4130b0
-			>;
-		};
-
-		pinctrl_csi1: csi1grp {
-			fsl,pins = <
-				MX6SLL_PAD_EPDC_GDRL__CSI_MCLK		0x1b088
-				MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK	0x1b088
-				MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC		0x1b088
-				MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC		0x1b088
-				MX6SLL_PAD_EPDC_DATA02__CSI_DATA02	0x1b088
-				MX6SLL_PAD_EPDC_DATA03__CSI_DATA03	0x1b088
-				MX6SLL_PAD_EPDC_DATA04__CSI_DATA04	0x1b088
-				MX6SLL_PAD_EPDC_DATA05__CSI_DATA05	0x1b088
-				MX6SLL_PAD_EPDC_DATA06__CSI_DATA06	0x1b088
-				MX6SLL_PAD_EPDC_DATA07__CSI_DATA07	0x1b088
-				MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08	0x1b088
-				MX6SLL_PAD_EPDC_SDLE__CSI_DATA09	0x1b088
-				MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26	0x80000000
-				MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25	0x80000000
-			>;
-		};
-
-                pinctrl_epdc0: epdcgrp0 {
-                        fsl,pins = <
-				MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00	0x100b1
-				MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01	0x100b1
-				MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02	0x100b1
-				MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03	0x100b1
-				MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04	0x100b1
-				MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05	0x100b1
-				MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06	0x100b1
-				MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07	0x100b1
-				MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08	0x100b1
-				MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09	0x100b1
-				MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10	0x100b1
-				MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11	0x100b1
-				MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12	0x100b1
-				MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13	0x100b1
-				MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14	0x100b1
-				MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15	0x100b1
-				MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P	0x100b1
-				MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE		0x100b1
-				MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE		0x100b1
-				MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR	0x100b1
-				MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0	0x100b1
-				MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK	0x100b1
-				MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE		0x100b1
-				MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL		0x100b1
-				MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP		0x100b1
-                       >;
-                };
-
-		pinctrl_lcdif_dat: lcdifdatgrp {
-			fsl,pins = <
-				MX6SLL_PAD_LCD_DATA00__LCD_DATA00	0x79
-				MX6SLL_PAD_LCD_DATA01__LCD_DATA01	0x79
-				MX6SLL_PAD_LCD_DATA02__LCD_DATA02	0x79
-				MX6SLL_PAD_LCD_DATA03__LCD_DATA03	0x79
-				MX6SLL_PAD_LCD_DATA04__LCD_DATA04	0x79
-				MX6SLL_PAD_LCD_DATA05__LCD_DATA05	0x79
-				MX6SLL_PAD_LCD_DATA06__LCD_DATA06	0x79
-				MX6SLL_PAD_LCD_DATA07__LCD_DATA07	0x79
-				MX6SLL_PAD_LCD_DATA08__LCD_DATA08	0x79
-				MX6SLL_PAD_LCD_DATA09__LCD_DATA09	0x79
-				MX6SLL_PAD_LCD_DATA10__LCD_DATA10	0x79
-				MX6SLL_PAD_LCD_DATA11__LCD_DATA11	0x79
-				MX6SLL_PAD_LCD_DATA12__LCD_DATA12	0x79
-				MX6SLL_PAD_LCD_DATA13__LCD_DATA13	0x79
-				MX6SLL_PAD_LCD_DATA14__LCD_DATA14	0x79
-				MX6SLL_PAD_LCD_DATA15__LCD_DATA15	0x79
-				MX6SLL_PAD_LCD_DATA16__LCD_DATA16	0x79
-				MX6SLL_PAD_LCD_DATA17__LCD_DATA17	0x79
-				MX6SLL_PAD_LCD_DATA18__LCD_DATA18	0x79
-				MX6SLL_PAD_LCD_DATA19__LCD_DATA19	0x79
-				MX6SLL_PAD_LCD_DATA20__LCD_DATA20	0x79
-				MX6SLL_PAD_LCD_DATA21__LCD_DATA21	0x79
-				MX6SLL_PAD_LCD_DATA22__LCD_DATA22	0x79
-				MX6SLL_PAD_LCD_DATA23__LCD_DATA23	0x79
-			>;
-		};
-
-		pinctrl_lcdif_ctrl: lcdifctrlgrp {
-			fsl,pins = <
-				MX6SLL_PAD_LCD_CLK__LCD_CLK		0x79
-				MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE	0x79
-				MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC		0x79
-				MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC		0x79
-				MX6SLL_PAD_LCD_RESET__LCD_RESET		0x79
-				MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08	0x79
-			>;
-		};
-
-		pinctrl_max17135: max17135grp-1 {
-			fsl,pins = <
-				MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13	0x80000000  /* pwrgood */
-				MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03	0x80000000  /* vcom_ctrl */
-				MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14	0x80000000  /* wakeup */
-				MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07	0x80000000  /* v3p3 */
-				MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12	0x80000000  /* pwr int */
-			>;
-		};
-
-		pinctrl_spdif: spdifgrp {
-			fsl,pins = <
-				MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x4130b0
-			>;
-		};
-
-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
-				MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
-			>;
-		};
-
-		pinctrl_uart5: uart5grp {
-			fsl,pins = <
-				MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x1b0b1  /* bt reg on */
-				MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x1b0b1
-				MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x1b0b1
-				MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x1b0b1
-				MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x1b0b1
-			>;
-		};
-
-		pinctrl_uart5dte: uart5dtegrp {
-			fsl,pins = <
-				MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x1b0b1
-				MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x1b0b1
-				MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x1b0b1
-				MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x1b0b1
-			>;
-		};
-
-		pinctrl_usdhc1: usdhc1grp {
-			fsl,pins = <
-				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x17059
-				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x13059
-				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x17059
-				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x17059
-				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x17059
-				MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x17059
-			>;
-		};
-
-		pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
-			fsl,pins = <
-				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170b9
-				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x130b9
-				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170b9
-				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170b9
-				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170b9
-				MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170b9
-			>;
-		};
-
-		pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
-			fsl,pins = <
-				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170f9
-				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x130f9
-				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170f9
-				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170f9
-				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170f9
-				MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170f9
-			>;
-		};
-
-		pinctrl_usdhc2: usdhc2grp {
-			fsl,pins = <
-				MX6SLL_PAD_SD2_CMD__SD2_CMD		0x17059
-				MX6SLL_PAD_SD2_CLK__SD2_CLK		0x13059
-				MX6SLL_PAD_SD2_DATA0__SD2_DATA0 	0x17059
-				MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x17059
-				MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x17059
-				MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x17059
-				MX6SLL_PAD_SD2_DATA4__SD2_DATA4		0x17059
-				MX6SLL_PAD_SD2_DATA5__SD2_DATA5		0x17059
-				MX6SLL_PAD_SD2_DATA6__SD2_DATA6		0x17059
-				MX6SLL_PAD_SD2_DATA7__SD2_DATA7		0x17059
-				MX6SLL_PAD_GPIO4_IO21__SD2_STROBE	0x413059
-			>;
-		};
-
-		pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
-			fsl,pins = <
-				MX6SLL_PAD_SD2_CMD__SD2_CMD		0x170b9
-				MX6SLL_PAD_SD2_CLK__SD2_CLK		0x130b9
-				MX6SLL_PAD_SD2_DATA0__SD2_DATA0 	0x170b9
-				MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x170b9
-				MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x170b9
-				MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x170b9
-				MX6SLL_PAD_SD2_DATA4__SD2_DATA4		0x170b9
-				MX6SLL_PAD_SD2_DATA5__SD2_DATA5		0x170b9
-				MX6SLL_PAD_SD2_DATA6__SD2_DATA6		0x170b9
-				MX6SLL_PAD_SD2_DATA7__SD2_DATA7		0x170b9
-				MX6SLL_PAD_GPIO4_IO21__SD2_STROBE	0x4130b9
-			>;
-		};
-
-		pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
-			fsl,pins = <
-				MX6SLL_PAD_SD2_CMD__SD2_CMD		0x170f9
-				MX6SLL_PAD_SD2_CLK__SD2_CLK		0x130f9
-				MX6SLL_PAD_SD2_DATA0__SD2_DATA0 	0x170f9
-				MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x170f9
-				MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x170f9
-				MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x170f9
-				MX6SLL_PAD_SD2_DATA4__SD2_DATA4		0x170f9
-				MX6SLL_PAD_SD2_DATA5__SD2_DATA5		0x170f9
-				MX6SLL_PAD_SD2_DATA6__SD2_DATA6		0x170f9
-				MX6SLL_PAD_SD2_DATA7__SD2_DATA7		0x170f9
-				MX6SLL_PAD_GPIO4_IO21__SD2_STROBE	0x4130f9
-			>;
-		};
-
-		pinctrl_usdhc3: usdhc3grp {
-			fsl,pins = <
-				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x17059
-				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x13059
-				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x17059
-				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x17059
-				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x17059
-				MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x17059
-			>;
-		};
-
-		pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
-			fsl,pins = <
-				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170b9
-				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x130b9
-				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170b9
-				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170b9
-				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170b9
-				MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170b9
-			>;
-		};
-
-		pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
-			fsl,pins = <
-				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170f9
-				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x130f9
-				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170f9
-				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170f9
-				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170f9
-				MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170f9
-			>;
-		};
-
-		pinctrl_usbotg1: usbotg1grp {
-			fsl,pins = <
-				MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
-			>;
-		};
-
-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX6SLL_PAD_I2C1_SCL__I2C1_SCL	 0x4001b8b1
-				MX6SLL_PAD_I2C1_SDA__I2C1_SDA	 0x4001b8b1
-			>;
-		};
-
-		pinctrl_i2c3: i2c3grp {
-			fsl,pins = <
-				MX6SLL_PAD_AUD_RXFS__I2C3_SCL  0x4041b8b1
-				MX6SLL_PAD_AUD_RXC__I2C3_SDA   0x4041b8b1
-			>;
-		};
+	pinctrl-0 = <&pinctrl_lcd>;
+	status = "okay";
 
-		pinctrl_pwm1: pmw1grp {
-			fsl,pins = <
-				MX6SLL_PAD_PWM1__PWM1_OUT   0x110b0
-			>;
+	port {
+		display_out: endpoint {
+			remote-endpoint = <&panel_in>;
 		};
 	};
 };
 
-&lcdif {
+&pwm1 {
+	#pwm-cells = <2>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lcdif_dat
-		     &pinctrl_lcdif_ctrl>;
-	lcd-supply = <&reg_lcd>;
-	display = <&display>;
+	pinctrl-0 = <&pinctrl_pwm1>;
 	status = "okay";
+};
 
-	display: display {
-		bits-per-pixel = <16>;
-		bus-width = <24>;
-
-		display-timings {
-			native-mode = <&timing0>;
-			timing0: timing0 {
-				clock-frequency = <33500000>;
-				hactive = <800>;
-				vactive = <480>;
-				hback-porch = <89>;
-				hfront-porch = <164>;
-				vback-porch = <23>;
-				vfront-porch = <10>;
-				hsync-len = <10>;
-				vsync-len = <10>;
-				hsync-active = <0>;
-				vsync-active = <0>;
-				de-active = <1>;
-				pixelclk-active = <0>;
-			};
-		};
-	};
+&snvs_poweroff {
+	status = "okay";
 };
 
-&pxp {
+&snvs_pwrkey {
 	status = "okay";
 };
 
-&pwm1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm1>;
+&ssi2 {
 	status = "okay";
 };
 
@@ -723,16 +330,6 @@
 	status = "okay";
 };
 
-&uart5 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart5>;
-	fsl,uart-has-rtscts;
-	/* for DTE mode, add below change */
-	/* fsl,dte-mode; */
-	/* pinctrl-0 = <&pinctrl_uart5dte>; */
-	status = "disabled";
-};
-
 &usdhc1 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc1>;
@@ -741,34 +338,11 @@
 	cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
 	keep-power-in-suspend;
-	enable-sdio-wakeup;
+	wakeup-source;
 	vmmc-supply = <&reg_sd1_vmmc>;
 	status = "okay";
 };
 
-&usdhc2 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
-	vqmmc-supply = <&reg_sd2_vmmc>;
-	bus-width = <8>;
-	no-removable;
-	status = "okay";
-};
-
-&usdhc3 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc3>;
-	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
-	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
-	keep-power-in-suspend;
-	enable-sdio-wakeup;
-	vmmc-supply = <&reg_sd3_vmmc>;
-	status = "okay";
-};
-
 &usbotg1 {
 	vbus-supply = <&reg_usb_otg1_vbus>;
 	pinctrl-names = "default";
@@ -787,15 +361,216 @@
 	status = "okay";
 };
 
-&epdc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_epdc0>;
-	V3P3-supply = <&V3P3_reg>;
-	VCOM-supply = <&VCOM_reg>;
-	DISPLAY-supply = <&DISPLAY_reg>;
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
+	keep-power-in-suspend;
+	wakeup-source;
+	vmmc-supply = <&reg_sd3_vmmc>;
 	status = "okay";
 };
 
-&ssi2 {
-	status = "okay";
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog1>;
+	fsl,ext-reset-output;
+};
+
+&iomuxc {
+	pinctrl_audmux3: audmux3grp {
+		fsl,pins = <
+			MX6SLL_PAD_AUD_TXC__AUD3_TXC		0x4130b0
+			MX6SLL_PAD_AUD_TXFS__AUD3_TXFS		0x4130b0
+			MX6SLL_PAD_AUD_TXD__AUD3_TXD		0x4110b0
+			MX6SLL_PAD_AUD_RXD__AUD3_RXD		0x4130b0
+			MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT	0x4130b0
+		>;
+	};
+
+	pinctrl_hp: hpgrp {
+		fsl,pins = <
+			MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
+		>;
+	};
+
+	pinctrl_reg_sd3_vmmc: sd3vmmcgrp {
+		fsl,pins = <
+			MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059
+		>;
+	};
+
+	pinctrl_usb_otg1_vbus: vbus1grp {
+		fsl,pins = <
+			MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
+		>;
+	};
+
+	pinctrl_usb_otg2_vbus: vbus2grp {
+		fsl,pins = <
+			MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
+		>;
+	};
+
+	pinctrl_reg_lcd_3v3: reglcd3v3grp {
+		fsl,pins = <
+			MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x17059
+		>;
+	};
+
+	pinctrl_reg_sd1_vmmc: sd1vmmcgrp {
+		fsl,pins = <
+			MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
+			MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6SLL_PAD_SD1_CMD__SD1_CMD	0x17059
+			MX6SLL_PAD_SD1_CLK__SD1_CLK	0x13059
+			MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x17059
+			MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x17059
+			MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x17059
+			MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x17059
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+		fsl,pins = <
+			MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170b9
+			MX6SLL_PAD_SD1_CLK__SD1_CLK	0x130b9
+			MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170b9
+			MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170b9
+			MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170b9
+			MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170b9
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+		fsl,pins = <
+			MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170f9
+			MX6SLL_PAD_SD1_CLK__SD1_CLK	0x130f9
+			MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170f9
+			MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170f9
+			MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170f9
+			MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170f9
+		>;
+	};
+
+	pinctrl_usbotg1: usbotg1grp {
+		fsl,pins = <
+			MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6SLL_PAD_SD3_CMD__SD3_CMD		0x17061
+			MX6SLL_PAD_SD3_CLK__SD3_CLK		0x13061
+			MX6SLL_PAD_SD3_DATA0__SD3_DATA0		0x17061
+			MX6SLL_PAD_SD3_DATA1__SD3_DATA1		0x17061
+			MX6SLL_PAD_SD3_DATA2__SD3_DATA2		0x17061
+			MX6SLL_PAD_SD3_DATA3__SD3_DATA3		0x17061
+			MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22	0x17059
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+		fsl,pins = <
+			MX6SLL_PAD_SD3_CMD__SD3_CMD		0x170a1
+			MX6SLL_PAD_SD3_CLK__SD3_CLK		0x130a1
+			MX6SLL_PAD_SD3_DATA0__SD3_DATA0		0x170a1
+			MX6SLL_PAD_SD3_DATA1__SD3_DATA1		0x170a1
+			MX6SLL_PAD_SD3_DATA2__SD3_DATA2		0x170a1
+			MX6SLL_PAD_SD3_DATA3__SD3_DATA3		0x170a1
+			MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22	0x17059
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+		fsl,pins = <
+			MX6SLL_PAD_SD3_CMD__SD3_CMD		0x170e9
+			MX6SLL_PAD_SD3_CLK__SD3_CLK		0x130f9
+			MX6SLL_PAD_SD3_DATA0__SD3_DATA0		0x170e9
+			MX6SLL_PAD_SD3_DATA1__SD3_DATA1		0x170e9
+			MX6SLL_PAD_SD3_DATA2__SD3_DATA2		0x170e9
+			MX6SLL_PAD_SD3_DATA3__SD3_DATA3		0x170e9
+			MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22	0x17059
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6SLL_PAD_I2C1_SCL__I2C1_SCL	 0x4001b8b1
+			MX6SLL_PAD_I2C1_SDA__I2C1_SDA	 0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6SLL_PAD_AUD_RXFS__I2C3_SCL  0x4041b8b1
+			MX6SLL_PAD_AUD_RXC__I2C3_SDA   0x4041b8b1
+		>;
+	};
+
+	pinctrl_lcd: lcdgrp {
+		fsl,pins = <
+			MX6SLL_PAD_LCD_DATA00__LCD_DATA00	0x79
+			MX6SLL_PAD_LCD_DATA01__LCD_DATA01	0x79
+			MX6SLL_PAD_LCD_DATA02__LCD_DATA02	0x79
+			MX6SLL_PAD_LCD_DATA03__LCD_DATA03	0x79
+			MX6SLL_PAD_LCD_DATA04__LCD_DATA04	0x79
+			MX6SLL_PAD_LCD_DATA05__LCD_DATA05	0x79
+			MX6SLL_PAD_LCD_DATA06__LCD_DATA06	0x79
+			MX6SLL_PAD_LCD_DATA07__LCD_DATA07	0x79
+			MX6SLL_PAD_LCD_DATA08__LCD_DATA08	0x79
+			MX6SLL_PAD_LCD_DATA09__LCD_DATA09	0x79
+			MX6SLL_PAD_LCD_DATA10__LCD_DATA10	0x79
+			MX6SLL_PAD_LCD_DATA11__LCD_DATA11	0x79
+			MX6SLL_PAD_LCD_DATA12__LCD_DATA12	0x79
+			MX6SLL_PAD_LCD_DATA13__LCD_DATA13	0x79
+			MX6SLL_PAD_LCD_DATA14__LCD_DATA14	0x79
+			MX6SLL_PAD_LCD_DATA15__LCD_DATA15	0x79
+			MX6SLL_PAD_LCD_DATA16__LCD_DATA16	0x79
+			MX6SLL_PAD_LCD_DATA17__LCD_DATA17	0x79
+			MX6SLL_PAD_LCD_DATA18__LCD_DATA18	0x79
+			MX6SLL_PAD_LCD_DATA19__LCD_DATA19	0x79
+			MX6SLL_PAD_LCD_DATA20__LCD_DATA20	0x79
+			MX6SLL_PAD_LCD_DATA21__LCD_DATA21	0x79
+			MX6SLL_PAD_LCD_DATA22__LCD_DATA22	0x79
+			MX6SLL_PAD_LCD_DATA23__LCD_DATA23	0x79
+			MX6SLL_PAD_LCD_CLK__LCD_CLK		0x79
+			MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE	0x79
+			MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC		0x79
+			MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC		0x79
+			MX6SLL_PAD_LCD_RESET__LCD_RESET		0x79
+		>;
+	};
+
+	pinctrl_led: ledgrp {
+		fsl,pins = <
+			MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04	0x17059
+		>;
+	};
+
+	pinctrl_pwm1: pmw1grp {
+		fsl,pins = <
+			MX6SLL_PAD_PWM1__PWM1_OUT   0x110b0
+		>;
+	};
+
+	pinctrl_wdog1: wdog1grp	{
+		fsl,pins = <
+			MX6SLL_PAD_WDOG_B__WDOG1_B   0x170b0
+		>;
+	};
 };
diff --git a/arch/arm/dts/imx6sll-pinfunc.h b/arch/arm/dts/imx6sll-pinfunc.h
index 5a3700b..713a346 100644
--- a/arch/arm/dts/imx6sll-pinfunc.h
+++ b/arch/arm/dts/imx6sll-pinfunc.h
@@ -1,9 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright 2017-2018 NXP.
  *
  */
 
diff --git a/arch/arm/dts/imx6sll.dtsi b/arch/arm/dts/imx6sll.dtsi
index ebc6d9d..d4a000c 100644
--- a/arch/arm/dts/imx6sll.dtsi
+++ b/arch/arm/dts/imx6sll.dtsi
@@ -1,18 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include <dt-bindings/clock/imx6sll-clock.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "imx6sll-pinfunc.h"
-#include "skeleton.dtsi"
 
 / {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
 	aliases {
 		gpio0 = &gpio1;
 		gpio1 = &gpio2;
@@ -35,6 +36,8 @@
 		spi1 = &ecspi2;
 		spi3 = &ecspi3;
 		spi4 = &ecspi4;
+		usb0 = &usbotg1;
+		usb1 = &usbotg2;
 		usbphy0 = &usbphy1;
 		usbphy1 = &usbphy2;
 	};
@@ -48,80 +51,58 @@
 			device_type = "cpu";
 			reg = <0>;
 			next-level-cache = <&L2>;
-			operating-points = <
+			operating-points =
 				/* kHz    uV */
-				996000  1225000
-				792000  1175000
-				396000  1075000
-				198000	975000
-			>;
-			fsl,soc-operating-points = <
+				<996000  1275000>,
+				<792000  1175000>,
+				<396000  1075000>,
+				<198000	  975000>;
+			fsl,soc-operating-points =
 				/* ARM kHz      SOC-PU uV */
-				996000          1225000
-				792000          1175000
-				396000          1175000
-				198000		1175000
-			>;
+				<996000         1175000>,
+				<792000         1175000>,
+				<396000         1175000>,
+				<198000		1175000>;
 			clock-latency = <61036>; /* two CLK32 periods */
-			fsl,low-power-run;
+			#cooling-cells = <2>;
 			clocks = <&clks IMX6SLL_CLK_ARM>,
 				 <&clks IMX6SLL_CLK_PLL2_PFD2>,
 				 <&clks IMX6SLL_CLK_STEP>,
 				 <&clks IMX6SLL_CLK_PLL1_SW>,
-				 <&clks IMX6SLL_CLK_PLL1_SYS>,
-				 <&clks IMX6SLL_CLK_PLL1>,
-				 <&clks IMX6SLL_PLL1_BYPASS>,
-				 <&clks IMX6SLL_PLL1_BYPASS_SRC>;
+				 <&clks IMX6SLL_CLK_PLL1_SYS>;
 			clock-names = "arm", "pll2_pfd2_396m", "step",
-				      "pll1_sw", "pll1_sys", "pll1", "pll1_bypass",
-				      "pll1_bypass_src";
+				      "pll1_sw", "pll1_sys";
+			nvmem-cells = <&cpu_speed_grade>;
+			nvmem-cell-names = "speed_grade";
 		};
 	};
 
-	intc: interrupt-controller@00a01000 {
-		compatible = "arm,cortex-a9-gic";
-		#interrupt-cells = <3>;
-		interrupt-controller;
-		reg = <0x00a01000 0x1000>,
-		      <0x00a00100 0x100>;
-		interrupt-parent = <&intc>;
+	ckil: clock-ckil {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "ckil";
 	};
 
-	clocks {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ckil: clock@0 {
-			compatible = "fixed-clock";
-			reg = <0>;
-			#clock-cells = <0>;
-			clock-frequency = <32768>;
-			clock-output-names = "ckil";
-		};
-
-		osc: clock@1 {
-			compatible = "fixed-clock";
-			reg = <1>;
-			#clock-cells = <0>;
-			clock-frequency = <24000000>;
-			clock-output-names = "osc";
-		};
+	osc: clock-osc-24m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "osc";
+	};
 
-		ipp_di0: clock@2 {
-			compatible = "fixed-clock";
-			reg = <2>;
-			#clock-cells = <0>;
-			clock-frequency = <0>;
-			clock-output-names = "ipp_di0";
-		};
+	ipp_di0: clock-ipp-di0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+		clock-output-names = "ipp_di0";
+	};
 
-		ipp_di1: clock@3 {
-			compatible = "fixed-clock";
-			reg = <3>;
-			#clock-cells = <0>;
-			clock-frequency = <0>;
-			clock-output-names = "ipp_di1";
-		};
+	ipp_di1: clock-ipp-di1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+		clock-output-names = "ipp_di1";
 	};
 
 	soc {
@@ -131,42 +112,21 @@
 		interrupt-parent = <&gpc>;
 		ranges;
 
-		busfreq {
-			compatible = "fsl,imx_busfreq";
-			clocks = <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_PLL2_198M>,
-				 <&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>,
-				 <&clks IMX6SLL_CLK_PLL3_USB_OTG>, <&clks IMX6SLL_CLK_PERIPH>,
-				 <&clks IMX6SLL_CLK_PERIPH_PRE>, <&clks IMX6SLL_CLK_PERIPH_CLK2>,
-				 <&clks IMX6SLL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SLL_CLK_OSC>,
-				 <&clks IMX6SLL_CLK_AHB>, <&clks IMX6SLL_CLK_AXI_PODF>,
-				 <&clks IMX6SLL_CLK_PERIPH2>, <&clks IMX6SLL_CLK_PERIPH2_PRE>,
-				 <&clks IMX6SLL_CLK_PERIPH2_CLK2>, <&clks IMX6SLL_CLK_PERIPH2_CLK2_SEL>,
-				 <&clks IMX6SLL_CLK_STEP>, <&clks IMX6SLL_CLK_MMDC_P0_FAST>, <&clks IMX6SLL_PLL1_BYPASS_SRC>,
-				 <&clks IMX6SLL_PLL1_BYPASS>, <&clks IMX6SLL_CLK_PLL1_SYS>, <&clks IMX6SLL_CLK_PLL1_SW>,
-				 <&clks IMX6SLL_CLK_PLL1>;
-			clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
-				      "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
-				      "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
-				      "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1";
-			fsl,max_ddr_freq = <400000000>;
-		};
-
-		ocrams: sram@00900000 {
-			compatible = "fsl,lpm-sram";
-			reg = <0x00900000 0x4000>;
+		ocram: sram@900000 {
+			compatible = "mmio-sram";
+			reg = <0x00900000 0x20000>;
 		};
 
-		ocrams_ddr: sram@00904000 {
-			compatible = "fsl,ddr-lpm-sram";
-			reg = <0x00904000 0x1000>;
+		intc: interrupt-controller@a01000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x00a01000 0x1000>,
+			      <0x00a00100 0x100>;
+			interrupt-parent = <&intc>;
 		};
 
-		ocram: sram@00905000 {
-			compatible = "mmio-sram";
-			reg = <0x00905000 0x1B000>;
-		};
-
-		L2: l2-cache@00a02000 {
+		L2: cache-controller@a02000 {
 			compatible = "arm,pl310-cache";
 			reg = <0x00a02000 0x1000>;
 			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -176,21 +136,21 @@
 			arm,data-latency = <4 2 3>;
 		};
 
-		aips1: bus@02000000 {
+		aips1: bus@2000000 {
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			reg = <0x02000000 0x100000>;
 			ranges;
 
-			spba: spba-bus@02000000 {
+			spba: spba-bus@2000000 {
 				compatible = "fsl,spba-bus", "simple-bus";
 				#address-cells = <1>;
 				#size-cells = <1>;
 				reg = <0x02000000 0x40000>;
 				ranges;
 
-				spdif: spdif@02004000 {
+				spdif: spdif@2004000 {
 					compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
 					reg = <0x02004000 0x4000>;
 					interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
@@ -214,7 +174,7 @@
 					status = "disabled";
 				};
 
-				ecspi1: ecspi@02008000 {
+				ecspi1: spi@2008000 {
 					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 					reg = <0x02008000 0x4000>;
 					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
@@ -226,7 +186,7 @@
 					status = "disabled";
 				};
 
-				ecspi2: ecspi@0200c000 {
+				ecspi2: spi@200c000 {
 					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 					reg = <0x0200c000 0x4000>;
 					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
@@ -238,7 +198,7 @@
 					status = "disabled";
 				};
 
-				ecspi3: ecspi@02010000 {
+				ecspi3: spi@2010000 {
 					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 					reg = <0x02010000 0x4000>;
 					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
@@ -250,7 +210,7 @@
 					status = "disabled";
 				};
 
-				ecspi4: ecspi@02014000 {
+				ecspi4: spi@2014000 {
 					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 					reg = <0x02014000 0x4000>;
 					interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
@@ -262,10 +222,11 @@
 					status = "disabled";
 				};
 
-				uart4: serial@02018000 {
-					compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+				uart4: serial@2018000 {
+					compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
+						     "fsl,imx21-uart";
 					reg = <0x02018000 0x4000>;
-					interrupts =<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+					interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 					dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 					dma-names = "rx", "tx";
 					clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
@@ -274,8 +235,9 @@
 					status = "disabled";
 				};
 
-				uart1: serial@02020000 {
-					compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+				uart1: serial@2020000 {
+					compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
+						     "fsl,imx21-uart";
 					reg = <0x02020000 0x4000>;
 					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 					dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
@@ -286,8 +248,9 @@
 					status = "disabled";
 				};
 
-				uart2: serial@02024000 {
-					compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+				uart2: serial@2024000 {
+					compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
+						     "fsl,imx21-uart";
 					reg = <0x02024000 0x4000>;
 					interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 					dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
@@ -298,8 +261,8 @@
 					status = "disabled";
 				};
 
-				ssi1: ssi@02028000 {
-					compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
+				ssi1: ssi@2028000 {
+					compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
 					reg = <0x02028000 0x4000>;
 					interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 					dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
@@ -311,8 +274,8 @@
 					status = "disabled";
 				};
 
-				ssi2: ssi2@0202c000 {
-					compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
+				ssi2: ssi@202c000 {
+					compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
 					reg = <0x0202c000 0x4000>;
 					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 					dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
@@ -324,8 +287,8 @@
 					status = "disabled";
 				};
 
-				ssi3: ssi@02030000 {
-					compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
+				ssi3: ssi@2030000 {
+					compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
 					reg = <0x02030000 0x4000>;
 					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 					dmas = <&sdma 45 22 0>, <&sdma 46 22 0>;
@@ -337,8 +300,9 @@
 					status = "disabled";
 				};
 
-				uart3: serial@02034000 {
-					compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+				uart3: serial@2034000 {
+					compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
+						     "fsl,imx21-uart";
 					reg = <0x02034000 0x4000>;
 					interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 					dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
@@ -350,48 +314,48 @@
 				};
 			};
 
-			pwm1: pwm@02080000 {
+			pwm1: pwm@2080000 {
 				compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 				reg = <0x02080000 0x4000>;
 				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SLL_CLK_PWM1>,
 					 <&clks IMX6SLL_CLK_PWM1>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 			};
 
-			pwm2: pwm@02084000 {
+			pwm2: pwm@2084000 {
 				compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 				reg = <0x02084000 0x4000>;
 				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SLL_CLK_PWM2>,
 					 <&clks IMX6SLL_CLK_PWM2>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 			};
 
-			pwm3: pwm@02088000 {
+			pwm3: pwm@2088000 {
 				compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 				reg = <0x02088000 0x4000>;
 				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SLL_CLK_PWM3>,
 					 <&clks IMX6SLL_CLK_PWM3>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 			};
 
-			pwm4: pwm@0208c000 {
+			pwm4: pwm@208c000 {
 				compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 				reg = <0x0208c000 0x4000>;
 				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SLL_CLK_PWM4>,
 					 <&clks IMX6SLL_CLK_PWM4>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 			};
 
-			gpt1: gpt@02098000 {
-				compatible = "fsl,imx6sll-gpt";
+			gpt1: timer@2098000 {
+				compatible = "fsl,imx6sl-gpt";
 				reg = <0x02098000 0x4000>;
 				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
@@ -399,73 +363,104 @@
 				clock-names = "ipg", "per";
 			};
 
-			gpio1: gpio@0209c000 {
+			gpio1: gpio@209c000 {
 				compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 				reg = <0x0209c000 0x4000>;
 				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6SLL_CLK_GPIO1>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
 			};
 
-			gpio2: gpio@020a0000 {
+			gpio2: gpio@20a0000 {
 				compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 				reg = <0x020a0000 0x4000>;
 				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6SLL_CLK_GPIO2>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 50 32>;
 			};
 
-			gpio3: gpio@020a4000 {
+			gpio3: gpio@20a4000 {
 				compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 				reg = <0x020a4000 0x4000>;
 				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6SLL_CLK_GPIO3>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
+				gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
+					      <&iomuxc 16 101 2>, <&iomuxc 18 5 1>,
+					      <&iomuxc 21 6 11>;
 			};
 
-			gpio4: gpio@020a8000 {
+			gpio4: gpio@20a8000 {
 				compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 				reg = <0x020a8000 0x4000>;
 				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6SLL_CLK_GPIO4>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
-			};
-
-			gpio5: gpio@020ac000 {
+				gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
+					      <&iomuxc 16 151 1>, <&iomuxc 17 149 1>,
+					      <&iomuxc 18 146 1>, <&iomuxc 19 144 1>,
+					      <&iomuxc 20 142 1>, <&iomuxc 21 143 1>,
+					      <&iomuxc 22 150 1>, <&iomuxc 23 148 1>,
+					      <&iomuxc 24 147 1>, <&iomuxc 25 145 1>,
+					      <&iomuxc 26 152 1>, <&iomuxc 27 125 1>,
+					      <&iomuxc 28 131 1>, <&iomuxc 29 134 1>,
+					      <&iomuxc 30 129 1>, <&iomuxc 31 133 1>;
+			};
+
+			gpio5: gpio@20ac000 {
 				compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 				reg = <0x020ac000 0x4000>;
 				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6SLL_CLK_GPIO5>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
-			};
-
-			gpio6: gpio@020b0000 {
+				gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
+					      <&iomuxc 2 132 1>, <&iomuxc 3 130 1>,
+					      <&iomuxc 4 127 1>, <&iomuxc 5 126 1>,
+					      <&iomuxc 6 120 1>, <&iomuxc 7 123 1>,
+					      <&iomuxc 8 118 1>, <&iomuxc 9 122 1>,
+					      <&iomuxc 10 124 1>, <&iomuxc 11 117 1>,
+					      <&iomuxc 12 121 1>, <&iomuxc 13 119 1>,
+					      <&iomuxc 14 116 1>, <&iomuxc 15 115 1>,
+					      <&iomuxc 16 140 2>, <&iomuxc 18 136 1>,
+					      <&iomuxc 19 138 1>, <&iomuxc 20 139 1>,
+					      <&iomuxc 21 137 1>;
+			};
+
+			gpio6: gpio@20b0000 {
 				compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 				reg = <0x020b0000 0x4000>;
 				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6SLL_CLK_GPIO6>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 			};
 
-			kpp: kpp@020b8000 {
+			kpp: keypad@20b8000 {
 				compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
 				reg = <0x020b8000 0x4000>;
 				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -473,14 +468,14 @@
 				status = "disabled";
 			};
 
-			wdog1: wdog@020bc000 {
+			wdog1: watchdog@20bc000 {
 				compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
 				reg = <0x020bc000 0x4000>;
 				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SLL_CLK_WDOG1>;
 			};
 
-			wdog2: wdog@020c0000 {
+			wdog2: watchdog@20c0000 {
 				compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
 				reg = <0x020c0000 0x4000>;
 				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -488,7 +483,7 @@
 				status = "disabled";
 			};
 
-			clks: ccm@020c4000 {
+			clks: clock-controller@20c4000 {
 				compatible = "fsl,imx6sll-ccm";
 				reg = <0x020c4000 0x4000>;
 				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
@@ -496,19 +491,25 @@
 				#clock-cells = <1>;
 				clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 				clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
+
+				assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
+				assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
 			};
 
-			anatop: anatop@020c8000 {
+			anatop: anatop@20c8000 {
 				compatible = "fsl,imx6sll-anatop",
 					     "fsl,imx6q-anatop",
-					     "syscon", "simple-bus";
+					     "syscon", "simple-mfd";
 				reg = <0x020c8000 0x4000>;
 				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 
-				reg_3p0: regulator-3p0@120 {
+				reg_3p0: regulator-3p0@20c8120 {
 					compatible = "fsl,anatop-regulator";
+					reg = <0x20c8120>;
 					regulator-name = "vdd3p0";
 					regulator-min-microvolt = <2625000>;
 					regulator-max-microvolt = <3400000>;
@@ -520,18 +521,19 @@
 					anatop-max-voltage = <3400000>;
 					anatop-enable-bit = <0>;
 				};
-			};
 
-			tempmon: tempmon {
-				compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
-				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-				fsl,tempmon = <&anatop>;
-				fsl,tempmon-data = <&ocotp>;
-				clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
-				status = "disabled";
+				tempmon: temperature-sensor {
+					compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
+					interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+					interrupt-parent = <&gpc>;
+					fsl,tempmon = <&anatop>;
+					nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+					nvmem-cell-names = "calib", "temp_grade";
+					clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
+				};
 			};
 
-			usbphy1: usbphy@020c9000 {
+			usbphy1: usb-phy@20c9000 {
 				compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
 						"fsl,imx23-usbphy";
 				reg = <0x020c9000 0x1000>;
@@ -541,7 +543,7 @@
 				fsl,anatop = <&anatop>;
 			};
 
-			usbphy2: usbphy@020ca000 {
+			usbphy2: usb-phy@20ca000 {
 				compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
 						"fsl,imx23-usbphy";
 				reg = <0x020ca000 0x1000>;
@@ -551,7 +553,7 @@
 				fsl,anatop = <&anatop>;
 			};
 
-			snvs: snvs@020cc000 {
+			snvs: snvs@20cc000 {
 				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 				reg = <0x020cc000 0x4000>;
 
@@ -559,7 +561,8 @@
 					compatible = "fsl,sec-v4.0-mon-rtc-lp";
 					regmap = <&snvs>;
 					offset = <0x34>;
-					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 				};
 
 				snvs_poweroff: snvs-poweroff {
@@ -567,6 +570,7 @@
 					regmap = <&snvs>;
 					offset = <0x38>;
 					mask = <0x61>;
+					status = "disabled";
 				};
 
 				snvs_pwrkey: snvs-powerkey {
@@ -574,21 +578,12 @@
 					regmap = <&snvs>;
 					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 					linux,keycode = <KEY_POWER>;
-					wakeup;
+					wakeup-source;
+					status = "disabled";
 				};
 			};
 
-			epit1: epit@020d0000 {
-				reg = <0x020d0000 0x4000>;
-				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
-			};
-
-			epit2: epit@020d4000 {
-				reg = <0x020d4000 0x4000>;
-				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
-			};
-
-			src: src@020d8000 {
+			src: reset-controller@20d8000 {
 				compatible = "fsl,imx6sll-src", "fsl,imx51-src";
 				reg = <0x020d8000 0x4000>;
 				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
@@ -596,28 +591,27 @@
 				#reset-cells = <1>;
 			};
 
-			gpc: gpc@020dc000 {
+			gpc: interrupt-controller@20dc000 {
 				compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
 				reg = <0x020dc000 0x4000>;
 				interrupt-controller;
 				#interrupt-cells = <3>;
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-parent = <&intc>;
-				fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>;
 			};
 
-			iomuxc: iomuxc@020e0000 {
+			iomuxc: pinctrl@20e0000 {
 				compatible = "fsl,imx6sll-iomuxc";
 				reg = <0x020e0000 0x4000>;
 			};
 
-			gpr: iomuxc-gpr@020e4000 {
+			gpr: iomuxc-gpr@20e4000 {
 				compatible = "fsl,imx6sll-iomuxc-gpr",
 					     "fsl,imx6q-iomuxc-gpr", "syscon";
 				reg = <0x020e4000 0x4000>;
 			};
 
-			csi: csi@020e8000 {
+			csi: csi@20e8000 {
 				compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
 				reg = <0x020e8000 0x4000>;
 				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -628,11 +622,11 @@
 				status = "disabled";
 			};
 
-			sdma: sdma@020ec000 {
-				compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma";
+			sdma: dma-controller@20ec000 {
+				compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma";
 				reg = <0x020ec000 0x4000>;
 				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX6SLL_CLK_SDMA>,
+				clocks = <&clks IMX6SLL_CLK_IPG>,
 					 <&clks IMX6SLL_CLK_SDMA>;
 				clock-names = "ipg", "ahb";
 				#dma-cells = <3>;
@@ -640,27 +634,16 @@
 				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 			};
 
-			pxp: pxp@020f0000 {
-				compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma";
-				reg = <0x020f0000 0x4000>;
+			pxp: pxp@20f0000 {
+				compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp";
+				reg = <0x20f0000 0x4000>;
 				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX6SLL_CLK_DUMMY>,
-					 <&clks IMX6SLL_CLK_PXP>;
-				clock-names = "pxp_ipg", "pxp_axi";
-				status = "disabled";
-			};
-
-			epdc: epdc@020f4000 {
-				compatible = "fsl,imx6sll-epdc", "fsl,imx7d-epdc";
-				reg = <0x020f4000 0x4000>;
-				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX6SLL_CLK_EPDC_AXI>, <&clks IMX6SLL_CLK_EPDC_PIX>;
-				clock-names = "epdc_axi", "epdc_pix";
-				status = "disabled";
+				clocks = <&clks IMX6SLL_CLK_PXP>;
+				clock-names = "axi";
 			};
 
-			lcdif: lcdif@020f8000 {
+			lcdif: lcd-controller@20f8000 {
 				compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
 				reg = <0x020f8000 0x4000>;
 				interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
@@ -671,8 +654,8 @@
 				status = "disabled";
 			};
 
-			dcp: dcp@020fc000 {
-				compatible = "fsl,imx6sl-dcp";
+			dcp: crypto@20fc000 {
+				compatible = "fsl,imx28-dcp";
 				reg = <0x020fc000 0x4000>;
 				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
@@ -682,14 +665,14 @@
 			};
 		};
 
-		aips2: bus@02100000 {
+		aips2: bus@2100000 {
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			reg = <0x02100000 0x100000>;
 			ranges;
 
-			usbotg1: usb@02184000 {
+			usbotg1: usb@2184000 {
 				compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
 						"fsl,imx27-usb";
 				reg = <0x02184000 0x200>;
@@ -704,7 +687,7 @@
 				status = "disabled";
 			};
 
-			usbotg2: usb@02184200 {
+			usbotg2: usb@2184200 {
 				compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
 						"fsl,imx27-usb";
 				reg = <0x02184200 0x200>;
@@ -718,14 +701,14 @@
 				status = "disabled";
 			};
 
-			usbmisc: usbmisc@02184800 {
+			usbmisc: usbmisc@2184800 {
 				#index-cells = <1>;
 				compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
 						"fsl,imx6q-usbmisc";
 				reg = <0x02184800 0x200>;
 			};
 
-			usdhc1: usdhc@02190000 {
+			usdhc1: mmc@2190000 {
 				compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
 				reg = <0x02190000 0x4000>;
 				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -739,7 +722,7 @@
 				status = "disabled";
 			};
 
-			usdhc2: usdhc@02194000 {
+			usdhc2: mmc@2194000 {
 				compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
 				reg = <0x02194000 0x4000>;
 				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
@@ -753,7 +736,7 @@
 				status = "disabled";
 			};
 
-			usdhc3: usdhc@02198000 {
+			usdhc3: mmc@2198000 {
 				compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
 				reg = <0x02198000 0x4000>;
 				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
@@ -767,17 +750,17 @@
 				status = "disabled";
 			};
 
-			i2c1: i2c@021a0000 {
+			i2c1: i2c@21a0000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c";
+				compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
 				reg = <0x021a0000 0x4000>;
 				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SLL_CLK_I2C1>;
 				status = "disabled";
 			};
 
-			i2c2: i2c@021a4000 {
+			i2c2: i2c@21a4000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
@@ -787,7 +770,7 @@
 				status = "disabled";
 			};
 
-			i2c3: i2c@021a8000 {
+			i2c3: i2c@21a8000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
@@ -797,56 +780,50 @@
 				status = "disabled";
 			};
 
-			romcp@021ac000 {
-				compatible = "fsl,imx6sll-romcp", "syscon";
-				reg = <0x021ac000 0x4000>;
-			};
-
-			mmdc: mmdc@021b0000 {
+			mmdc: memory-controller@21b0000 {
 				compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
 				reg = <0x021b0000 0x4000>;
+				clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
 			};
 
-			rngb: rngb@021b4000 {
-				compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng";
+			rngb: rng@21b4000 {
+				compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb";
 				reg = <0x021b4000 0x4000>;
 				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-				clocks =  <&clks IMX6SLL_CLK_DUMMY>;
+				clocks = <&clks IMX6SLL_CLK_DUMMY>;
 			};
 
-			ocotp: ocotp-ctrl@021bc000 {
+			ocotp: efuse@21bc000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
 				compatible = "fsl,imx6sll-ocotp", "syscon";
 				reg = <0x021bc000 0x4000>;
 				clocks = <&clks IMX6SLL_CLK_OCOTP>;
-			};
 
-			csu: csu@021c0000 {
-				compatible = "fsl,imx6sll-csu";
-				reg = <0x021c0000 0x4000>;
-				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-				status = "disabled";
-			};
+				cpu_speed_grade: speed-grade@10 {
+					reg = <0x10 4>;
+				};
 
-			snvs_gpr: snvs-gpr@0x021c4000 {
-				compatible = "fsl, imx6sll-snvs-gpr";
-				reg = <0x021c4000 0x10000>;
-			};
+				tempmon_calib: calib@38 {
+					reg = <0x38 4>;
+				};
 
-			iomuxc_snvs: iomuxc-snvs@021c8000 {
-				compatible = "fsl,imx6sll-iomuxc-snvs";
-				reg = <0x021c80000 0x10000>;
+				tempmon_temp_grade: temp-grade@20 {
+					reg = <0x20 4>;
+				};
 			};
 
-			audmux: audmux@021d8000 {
+			audmux: audmux@21d8000 {
 				compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
 				reg = <0x021d8000 0x4000>;
 				status = "disabled";
 			};
 
-			uart5: serial@021f4000 {
-				compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+			uart5: serial@21f4000 {
+				compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
+					     "fsl,imx21-uart";
 				reg = <0x021f4000 0x4000>;
-				interrupts =<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 				dma-names = "rx", "tx";
 				clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h
index 39c2567..494fd0c 100644
--- a/include/dt-bindings/clock/imx6sll-clock.h
+++ b/include/dt-bindings/clock/imx6sll-clock.h
@@ -1,9 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright 2017-2018 NXP.
  *
  */
 
@@ -199,6 +197,14 @@
 #define IMX6SLL_CLK_EXTERN_AUDIO_PODF   171
 #define IMX6SLL_CLK_EXTERN_AUDIO        172
 
-#define IMX6SLL_CLK_END			173
+#define IMX6SLL_CLK_GPIO1               173
+#define IMX6SLL_CLK_GPIO2               174
+#define IMX6SLL_CLK_GPIO3               175
+#define IMX6SLL_CLK_GPIO4               176
+#define IMX6SLL_CLK_GPIO5               177
+#define IMX6SLL_CLK_GPIO6               178
+#define IMX6SLL_CLK_MMDC_P1_IPG		179
+
+#define IMX6SLL_CLK_END			180
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */