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| author | Michael Trimarchi <michael@amarulasolutions.com> | 2022-07-25 12:20:24 +0200 |
|---|---|---|
| committer | Michael Trimarchi <michael@amarulasolutions.com> | 2022-08-22 11:15:24 +0200 |
| commit | 007f1d14738a1d4c94ebdb726f0d874f9e08f36d (patch) | |
| tree | ac12d64f64a2a4018ba623e91038511a012b4b9a | |
| parent | 6cda1dc210304d8d74fd3c4b98b80b47ba1982c1 (diff) | |
| download | u-boot-007f1d14738a1d4c94ebdb726f0d874f9e08f36d.zip u-boot-007f1d14738a1d4c94ebdb726f0d874f9e08f36d.tar.gz u-boot-007f1d14738a1d4c94ebdb726f0d874f9e08f36d.tar.bz2 | |
mtd: nand: samsung: Retrieve ECC requirements from extended
Upstream linux commit 8fc82d456e40a0.
On some nand controllers with hw-ecc the controller code wants to know
the ecc strength and size and having these as 0, 0 is not accepted.
Specifying these in devicetree is possible but undesirable as the nand
may be different in different production runs of the same board, so it
is better to get this info from the nand id where possible.
This commit adds code to read the ecc strength and size from the nand
for Samsung extended-id nands. This code is based on the info for the 5th
id byte in the datasheets for the following Samsung nands: K9GAG08U0E,
K9GAG08U0F, K9GAG08X0D, K9GBG08U0A, K9GBG08U0B. These all use these bits
in the exact same way.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
| -rw-r--r-- | drivers/mtd/nand/raw/nand_samsung.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/mtd/nand/raw/nand_samsung.c b/drivers/mtd/nand/raw/nand_samsung.c index 0ab8062..36ef48e 100644 --- a/drivers/mtd/nand/raw/nand_samsung.c +++ b/drivers/mtd/nand/raw/nand_samsung.c @@ -64,6 +64,26 @@ static void samsung_nand_decode_id(struct nand_chip *chip) extid >>= 2; mtd->erasesize = (128 * 1024) << (((extid >> 1) & 0x04) | (extid & 0x03)); + + /* Extract ECC requirements from 5th id byte*/ + extid = (chip->id.data[4] >> 4) & 0x07; + if (extid < 5) { + chip->ecc_step_ds = 512; + chip->ecc_strength_ds = 1 << extid; + } else { + chip->ecc_step_ds = 1024; + switch (extid) { + case 5: + chip->ecc_strength_ds = 24; + break; + case 6: + chip->ecc_strength_ds = 40; + break; + case 7: + chip->ecc_strength_ds = 60; + break; + } + } } else { nand_decode_ext_id(chip); } |