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| author | Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> | 2022-08-24 05:38:46 -0600 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2022-09-13 11:32:48 +0200 |
| commit | d0003b5edf11b0fc2a050e2a0eaac39ba921d85e (patch) | |
| tree | 2cfbc2842bce9ce245042039af25613393bdd5a1 | |
| parent | 68852f3241af7d2f3e7cf85fbcd2268fd8c22b1e (diff) | |
| download | u-boot-d0003b5edf11b0fc2a050e2a0eaac39ba921d85e.zip u-boot-d0003b5edf11b0fc2a050e2a0eaac39ba921d85e.tar.gz u-boot-d0003b5edf11b0fc2a050e2a0eaac39ba921d85e.tar.bz2 | |
spi: cadence_qspi: Call read_setup for STIG_READ
In cadence_spi_read_id we are using STIG mode to read flash id's.
Call cadence_qspi_apb_command_read_setup() to setup cmd, addr and data
bus width properly before cadence_qspi_apb_command_read().
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220824113847.7482-3-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
| -rw-r--r-- | drivers/spi/cadence_qspi.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 907f5da..6e50b94 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -59,12 +59,17 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz) static int cadence_spi_read_id(struct cadence_spi_plat *plat, u8 len, u8 *idcode) { + int err; struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1), SPI_MEM_OP_NO_ADDR, SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_DATA_IN(len, idcode, 1)); - return cadence_qspi_apb_command_read(plat, &op); + err = cadence_qspi_apb_command_read_setup(plat, &op); + if (!err) + err = cadence_qspi_apb_command_read(plat, &op); + + return err; } /* Calibration sequence to determine the read data capture delay register */ |