diff options
| author | Tom Rini <trini@konsulko.com> | 2022-06-25 11:02:34 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-07-07 09:29:08 -0400 |
| commit | f1c6dfa4264cdb4da68e0f47a5a8b046fb67b0d1 (patch) | |
| tree | 0f140281c78825c5410aaa018df0325e779b365c | |
| parent | ac8b36938a74d87a272e730998d03fe15aa9f503 (diff) | |
| download | u-boot-f1c6dfa4264cdb4da68e0f47a5a8b046fb67b0d1.zip u-boot-f1c6dfa4264cdb4da68e0f47a5a8b046fb67b0d1.tar.gz u-boot-f1c6dfa4264cdb4da68e0f47a5a8b046fb67b0d1.tar.bz2 | |
layerscape: Remove some unused CONFIG symbols
All of these symbols are not referenced anywhere else in the code, so
remove them.
Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-ls102xa/config.h | 6 | ||||
| -rw-r--r-- | include/configs/MPC837XERDB.h | 1 | ||||
| -rw-r--r-- | include/configs/ids8313.h | 1 | ||||
| -rw-r--r-- | include/configs/mx6ullevk.h | 6 |
6 files changed, 1 insertions, 18 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 4b0f554..f2dbcdc 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -13,10 +13,8 @@ #define CONFIG_SYS_DCSRBAR 0x20000000 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) -#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040) #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) -#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) @@ -26,9 +24,7 @@ #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) #define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) #define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) -#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) -#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 304cd79..570397b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -52,7 +52,6 @@ #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL -#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 796e2b2..e5f61ea 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -32,14 +32,11 @@ #define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) -#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 #define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 -#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 -#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000 #define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) @@ -79,8 +76,7 @@ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) #ifdef CONFIG_DDR_SPD #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE +#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #endif #define CONFIG_SYS_FSL_IFC_BE diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 3e4d668..8517b03 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -227,7 +227,6 @@ #ifdef CONFIG_TSEC2 #define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 #define TSEC2_PHY_ADDR 0x1c #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) #define TSEC2_PHYIDX 0 diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index e0994d1..a8bb209 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -164,7 +164,6 @@ #ifdef CONFIG_TSEC2 #define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 #define TSEC2_PHY_ADDR 0x3 #define TSEC2_FLAGS TSEC_GIGABIT #define TSEC2_PHYIDX 0 diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index db09db4..00cc547 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -21,14 +21,8 @@ /* MMC Configs */ #ifdef CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR - -/* NAND pin conflicts with usdhc2 */ -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_SYS_FSL_USDHC_NUM 1 -#else #define CONFIG_SYS_FSL_USDHC_NUM 2 #endif -#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ |