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| author | David Lechner <david@lechnology.com> | 2018-05-19 23:25:06 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-06-05 10:33:57 -0400 |
| commit | 71eb63e7ee10299e1edfbdfcec21592de6953d62 (patch) | |
| tree | b7e9aa4635afc51599f5573ae0cf1066df8d3aed | |
| parent | 98ada4b3f035e11510c4a5bfc10b1c134ffbd2af (diff) | |
| download | u-boot-71eb63e7ee10299e1edfbdfcec21592de6953d62.zip u-boot-71eb63e7ee10299e1edfbdfcec21592de6953d62.tar.gz u-boot-71eb63e7ee10299e1edfbdfcec21592de6953d62.tar.bz2 | |
ARM: legoev3: remove unused configuration options
This removes the unused clock and RAM config options that were cargo-
culted when this board was copied from the DA850 EVM.
Signed-off-by: David Lechner <david@lechnology.com>
| -rw-r--r-- | include/configs/legoev3.h | 54 |
1 files changed, 0 insertions, 54 deletions
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 6972ced..9eb95bc 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -39,60 +39,6 @@ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ - DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ - DAVINCI_SYSCFG_SUSPSRC_SPI0 | \ - DAVINCI_SYSCFG_SUSPSRC_UART1 | \ - DAVINCI_SYSCFG_SUSPSRC_I2C) - -/* - * PLL configuration - */ - -#define CONFIG_SYS_DA850_PLL0_PLLM 24 -#define CONFIG_SYS_DA850_PLL1_PLLM 21 - -/* - * DDR2 memory configuration - */ -#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ - DV_DDR_PHY_EXT_STRBEN | \ - (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ - (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ - (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ - (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ - (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ - (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ - (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ - (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) - -/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ -#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 - -#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ - (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ - (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ - (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ - (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ - (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ - (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ - (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ - (0 << DV_DDR_SDTMR1_WTR_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ - (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ - (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ - (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ - (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ - (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ - (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ - (0 << DV_DDR_SDTMR2_CKE_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 -#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 - /* * Serial Driver info */ |