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authorAndre Przywara <andre.przywara@arm.com>2017-02-16 01:20:18 +0000
committerJagan Teki <jagan@amarulasolutions.com>2017-04-05 15:03:17 +0530
commit1afd0f6f17db1625a50b69a1edc40f5163db7c31 (patch)
tree3b71bb4210df00db1913e66da81155e3a3a292c0
parent11db152246607868f0e74db958947fbf79f28119 (diff)
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sunxi: fix ACTLR.SMP assembly routine
If we take the liberty to use register r0 to perform our bit set, we should be nice enough to tell the compiler about it. Add r0 to the clobber list to avoid potential mayhem. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Jagan Teki <jagan@openedev.com>
-rw-r--r--arch/arm/mach-sunxi/board.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 52be5b0..58fbacb 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -188,7 +188,8 @@ void s_init(void)
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
"orr r0, r0, #1 << 6\n"
- "mcr p15, 0, r0, c1, c0, 1\n");
+ "mcr p15, 0, r0, c1, c0, 1\n"
+ ::: "r0");
#endif
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
/* Enable non-secure access to some peripherals */