diff options
author | Tom Rini <trini@konsulko.com> | 2021-05-17 10:01:56 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2021-05-17 10:01:56 -0400 |
commit | feddbdb55f47b94f9f6695dc19a826953f893f7a (patch) | |
tree | 0548162461ec8301549ed2303be59faed4add4c6 | |
parent | 7e1d0a8f17547f7aeedad0681753f260c8e60196 (diff) | |
parent | e1c55dfc7b59e8e49fc400290b3bea8066b74de1 (diff) | |
download | u-boot-feddbdb55f47b94f9f6695dc19a826953f893f7a.zip u-boot-feddbdb55f47b94f9f6695dc19a826953f893f7a.tar.gz u-boot-feddbdb55f47b94f9f6695dc19a826953f893f7a.tar.bz2 |
Merge https://source.denx.de/u-boot/custodians/u-boot-marvellWIP/17May2021
- Add base support for Marvell OcteonTX2 CN9130 DB (mostly done
by Kostya)
- Sync Armada 8k MMU setup with Marvell version (misc Marvell
authors)
- spi: kirkwood: Some fixes especially for baudrate generation
(misc Marvell authors)
- mvebu: x530: Reduce SPL image size (Stefan)
- Rename "rx_training" to "mvebu_comphy_rx_training" (Stefan)
-rw-r--r-- | arch/arm/dts/Makefile | 6 | ||||
-rw-r--r-- | arch/arm/dts/cn9130-db-A.dts | 55 | ||||
-rw-r--r-- | arch/arm/dts/cn9130-db-B.dts | 51 | ||||
-rw-r--r-- | arch/arm/dts/cn9130-db-dev-info.dtsi | 44 | ||||
-rw-r--r-- | arch/arm/dts/cn9130-db.dtsi | 316 | ||||
-rw-r--r-- | arch/arm/dts/cn9131-db-A.dts | 54 | ||||
-rw-r--r-- | arch/arm/dts/cn9131-db-B.dts | 69 | ||||
-rw-r--r-- | arch/arm/dts/cn9131-db.dtsi | 166 | ||||
-rw-r--r-- | arch/arm/dts/cn9132-db-A.dts | 13 | ||||
-rw-r--r-- | arch/arm/dts/cn9132-db-B.dts | 13 | ||||
-rw-r--r-- | arch/arm/dts/cn9132-db.dtsi | 217 | ||||
-rw-r--r-- | arch/arm/mach-mvebu/armada8k/cpu.c | 70 | ||||
-rw-r--r-- | arch/arm/mach-mvebu/include/mach/fw_info.h | 18 | ||||
-rw-r--r-- | board/Marvell/octeontx2_cn913x/MAINTAINERS | 1 | ||||
-rw-r--r-- | board/Marvell/octeontx2_cn913x/README | 24 | ||||
-rw-r--r-- | cmd/mvebu/Kconfig | 9 | ||||
-rw-r--r-- | cmd/mvebu/Makefile | 2 | ||||
-rw-r--r-- | cmd/mvebu/comphy_rx_training.c (renamed from cmd/mvebu/rx_training.c) | 10 | ||||
-rw-r--r-- | configs/mvebu_db_cn9130_defconfig | 89 | ||||
-rw-r--r-- | configs/x530_defconfig | 2 | ||||
-rw-r--r-- | drivers/pci/pcie_dw_mvebu.c | 37 | ||||
-rw-r--r-- | drivers/spi/kirkwood_spi.c | 67 |
22 files changed, 1250 insertions, 83 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2538dd3..9c601a5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -237,6 +237,12 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-xp-maxbcm.dtb \ armada-xp-synology-ds414.dtb \ armada-xp-theadorable.dtb \ + cn9130-db-A.dtb \ + cn9130-db-B.dtb \ + cn9131-db-A.dtb \ + cn9131-db-B.dtb \ + cn9132-db-A.dtb \ + cn9132-db-B.dtb \ cn9130-crb-A.dtb \ cn9130-crb-B.dtb diff --git a/arch/arm/dts/cn9130-db-A.dts b/arch/arm/dts/cn9130-db-A.dts new file mode 100644 index 0000000..90d6e4a --- /dev/null +++ b/arch/arm/dts/cn9130-db-A.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#include "cn9130-db.dtsi" + +/ { + model = "Marvell CN9130 development board (CP NOR) setup(A)"; + + aliases { + spi0 = &cp0_spi1; + }; +}; + +/* + * CP related configuration + */ +&cp0_pinctl { + /* MPP Bus: + * [0-11] RGMII1 + * [12] GPIO GE-IN + * [13-16] SPI1 + * [17-27] NAND + * [28] MSS_GPIO[5] XXX:(mode nr from a3900) + * [29-30] SATA + * [31] MSS_GPIO[4] XXX:(mode nr from a3900) + * [32,34] SMI + * [33] SDIO + * [35-36] I2C1 + * [37-38] I2C0 + * [39-43] SDIOctrl + * [44-55] RGMII2 + * [56-62] SDIO + */ + + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 3 3 3 3 3 3 3 3 3 3 + 3 3 0 3 3 3 3 1 1 1 + 1 1 1 1 1 1 1 1 3 9 + 9 3 7 6 7 2 2 2 2 1 + 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 0xe 0xe 0xe 0xe + 0xe 0xe 0xe>; +}; + +/* U54 */ +&cp0_nand { + status = "disabled"; +}; + +/* U55 */ +&cp0_spi1 { + status = "okay"; +}; diff --git a/arch/arm/dts/cn9130-db-B.dts b/arch/arm/dts/cn9130-db-B.dts new file mode 100644 index 0000000..fb52aa8 --- /dev/null +++ b/arch/arm/dts/cn9130-db-B.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#include "cn9130-db.dtsi" + +/ { + model = "Marvell CN9130 development board (CP NAND) setup(B)"; +}; + +/* + * CP related configuration + */ +&cp0_pinctl { + /* MPP Bus: + * [0-11] RGMII1 + * [12] GPIO GE-IN + * [13-14] SPI1 + * [15-27] NAND + * [28] MSS_GPIO[5] XXX:(mode nr from a3900) + * [29-30] SATA + * [31] MSS_GPIO[4] XXX:(mode nr from a3900) + * [32,34] SMI + * [33] SDIO + * [35-36] I2C1 + * [37-38] I2C0 + * [39-43] SDIOctrl + * [44-55] RGMII2 + * [56-62] SDIO + */ + + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 3 3 3 3 3 3 3 3 3 3 + 3 3 0 2 3 1 1 1 1 1 + 1 1 1 1 1 1 1 1 3 9 + 9 3 7 6 7 2 2 2 2 1 + 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 0xe 0xe 0xe 0xe + 0xe 0xe 0xe>; +}; + +/* U54 */ +&cp0_nand { + status = "okay"; +}; + +/* U55 */ +&cp0_spi1 { + status = "disabled"; +}; diff --git a/arch/arm/dts/cn9130-db-dev-info.dtsi b/arch/arm/dts/cn9130-db-dev-info.dtsi new file mode 100644 index 0000000..68e9c0b --- /dev/null +++ b/arch/arm/dts/cn9130-db-dev-info.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ +/ { + /* This should go only into devel boards */ + compatible = "marvell,cp110"; + sar { + #address-cells = <1>; + #size-cells = <0>; + + sar_fields { + compatible = "marvell,sample-at-reset"; + reg = <0x4c 0x4e>; + chip_count = <2>; + bit_width = <5>; + freq { + key = "freq"; + description = "CPU/DDR and PIDI frequencies"; + start-bit = <0>; + bit-length = <4>; + option-cnt = <3>; + options = "0x0", "CPU/DDR = 0x0: 2000/1200 Mhz, PIDI = 0: 1Ghz", + "0x2", "CPU/DDR = 0x6: 2200/1200 Mhz, PIDI = 0: 1Ghz", + "0x4", "CPU/DDR = 0xD: 1600/1200 Mhz, PIDI = 0: 1Ghz"; + default = <0x2>; + status = "okay"; + }; + boot_mode { + key = "boot_mode"; + description = "Boot mode options"; + start-bit = <4>; + bit-length = <6>; + option-cnt = <4>; + options = "0xE", "CP0_NAND PIDI BW-8bit, PS-4KB, ECC-4bit\t(supported configuration: B)", + "0xF", "CP0_NAND PIDI BW-8bit, PS-4KB, ECC-8bit\t(supported configuration: B)", + "0x2A", "AP_EMMC", + "0x32", "CP1_SPI_1 24bits"; + default = <0x32>; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/dts/cn9130-db.dtsi b/arch/arm/dts/cn9130-db.dtsi new file mode 100644 index 0000000..1b28732 --- /dev/null +++ b/arch/arm/dts/cn9130-db.dtsi @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#include "cn9130.dtsi" /* include SoC device tree */ +#include "cn9130-db-dev-info.dtsi" + +/ { + model = "DB-CN-9130"; + compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd", + "marvell,cn9030", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + i2c0 = &cp0_i2c0; + gpio0 = &ap_gpio0; + gpio1 = &cp0_gpio0; + gpio2 = &cp0_gpio1; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + cp0 { + config-space { + i2c@701000 { + /* U36 */ + expander0: pca953x@21 { + compatible = "nxp,pca9555"; + #gpio-cells = <2>; + reg = <0x21>; + status = "okay"; + }; + }; + sdhci@780000 { + vqmmc-supply = <&cp0_reg_sd_vccq>; + vmmc-supply = <&cp0_reg_sd_vcc>; + }; + + ap_reg_mmc_vccq: ap_mmc_vccq@0 { + compatible = "regulator-gpio"; + regulator-name = "ap_mmc_vccq"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&expander0 8 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1 + 3300000 0x0>; + }; + cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 { + compatible = "regulator-fixed"; + regulator-name = "cp0-xhci0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + regulator-force-boot-off; + gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; + }; + + cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 { + compatible = "regulator-fixed"; + regulator-name = "cp0-xhci1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + regulator-force-boot-off; + gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; + }; + cp0_reg_sd_vccq: cp0_sd_vccq@0 { + compatible = "regulator-gpio"; + regulator-name = "cp0_sd_vccq"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&expander0 15 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1 + 3300000 0x0>; + }; + cp0_reg_sd_vcc: cp0_sd_vcc@0 { + compatible = "regulator-fixed"; + regulator-name = "cp0_sd_vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + cp0_reg_usb3_current_lim0:cp0_usb3_current_limiter@0 { + compatible = "regulator-fixed"; + regulator-min-microamp = <900000>; + regulator-max-microamp = <900000>; + regulator-force-boot-off; + gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; + }; + + cp0_reg_usb3_current_lim1: cp0_usb3_current_limiter@1 { + compatible = "regulator-fixed"; + regulator-min-microamp = <900000>; + regulator-max-microamp = <900000>; + regulator-force-boot-off; + gpio = <&expander0 5 GPIO_ACTIVE_HIGH>; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +/* + * AP related configuration + */ +&ap_pinctl { + /* MPP Bus: + * SDIO [0-10, 12] + * UART0 [11,19] + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 1 1 1 1 1 1 1 1 1 1 + 1 3 1 0 0 0 0 0 0 3 >; +}; + +/* on-board eMMC - U9 */ +&ap_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&ap_emmc_pins>; + vqmmc-supply = <&ap_reg_mmc_vccq>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + status = "okay"; +}; + +/* + * CP related configuration + */ +&cp0_pinctl { + cp0_nand_pins: cp0-nand-pins { + marvell,pins = <15 16 17 18 19 20 21 22 23 24 25 26 27 >; + marvell,function = <1>; + }; + cp0_nand_rb: cp0-nand-rb { + marvell,pins = < 13 >; + marvell,function = <2>; + }; +}; + +/* + * CP0 + */ +&cp0_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cp0_i2c1 { + status = "okay"; +}; + +/* CON 28 */ +&cp0_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_sdhci_pins>; + bus-width = <4>; + status = "okay"; +}; + +/* U54 */ +&cp0_nand { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_nand_pins &cp0_nand_rb>; + status = "disabled"; +}; + +/* U55 */ +&cp0_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_spi0_pins>; + reg = <0x700680 0x50>, /* control */ + <0x2000000 0x1000000>, /* CS0 */ + <0 0xffffffff>, /* CS1 */ + <0 0xffffffff>, /* CS2 */ + <0 0xffffffff>; /* CS3 */ + status = "disabled"; + + spi-flash@0 { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "jedec,spi-nor", "spi-flash"; + reg = <0x0>; + /* On-board MUX does not allow higher frequencies */ + spi-max-frequency = <40000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x200000>; + }; + + partition@400000 { + label = "Filesystem"; + reg = <0x200000 0xe00000>; + }; + }; + }; +}; + +&cp0_comphy { + phy0 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + + phy1 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + + phy2 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + + phy3 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + + phy4 { + phy-type = <COMPHY_TYPE_SFI0>; + phy-speed = <COMPHY_SPEED_10_3125G>; + }; + + phy5 { + phy-type = <COMPHY_TYPE_SATA1>; + }; +}; + +/* SLM-1521-V2, CON6 */ +&cp0_pcie0 { + num-lanes = <4>; + status = "disabled"; +}; + +&cp0_mdio { + status = "okay"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cp0_ethernet { + status = "okay"; +}; + +/* SLM-1521-V2, CON9 */ +&cp0_eth0 { + status = "okay"; + phy-mode = "sfi"; +}; + +/* CON56 */ +&cp0_eth1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +/* CON57 */ +&cp0_eth2 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; +}; + +/* SLM-1521-V2, CON2 */ +&cp0_sata0 { + status = "okay"; +}; + +&cp0_utmi0 { + status = "okay"; +}; + +&cp0_utmi1 { + status = "okay"; +}; + +&cp0_usb3_0 { + status = "okay"; + vbus-supply = <&cp0_reg_usb3_vbus0>; + current-limiter = <&cp0_reg_usb3_current_lim0>; + vbus-disable-delay = <500>; +}; + +&cp0_usb3_1 { + status = "okay"; + vbus-supply = <&cp0_reg_usb3_vbus1>; + current-limiter = <&cp0_reg_usb3_current_lim1>; + vbus-disable-delay = <500>; +}; + +&cp0_pcie0 { + status = "okay"; +}; diff --git a/arch/arm/dts/cn9131-db-A.dts b/arch/arm/dts/cn9131-db-A.dts new file mode 100644 index 0000000..81aff17 --- /dev/null +++ b/arch/arm/dts/cn9131-db-A.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#include "cn9130-db-A.dts" +#include "cn9131-db.dtsi" + +/ { + model = "Marvell CN9131 development board (CP NOR) setup(A)"; + compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; + +&cp1_comphy { + /* Serdes Configuration: + * Lane 0: PCIe0 (x2) + * Lane 1: PCIe0 (x2) + * Lane 2: unconnected + * Lane 3: USB1 + * Lane 4: SFP (port 0) + * Lane 5: SATA1 + */ + phy0 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + phy1 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + phy2 { + phy-type = <COMPHY_TYPE_UNCONNECTED>; + }; + phy3 { + phy-type = <COMPHY_TYPE_USB3_HOST1>; + }; + phy4 { + phy-type = <COMPHY_TYPE_SFI0>; + phy-speed = <COMPHY_SPEED_10_3125G>; + }; + phy5 { + phy-type = <COMPHY_TYPE_SATA1>; + }; +}; + +&cp1_ethernet { + status = "okay"; +}; + +/* CON50 */ +&cp1_eth0 { + status = "okay"; + phy-mode = "sfi"; /* lane-4 */ + marvell,sfp-tx-disable-gpio = <&cp1_gpio0 9 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/dts/cn9131-db-B.dts b/arch/arm/dts/cn9131-db-B.dts new file mode 100644 index 0000000..0269183 --- /dev/null +++ b/arch/arm/dts/cn9131-db-B.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#include "cn9130-db-B.dts" +#include "cn9131-db.dtsi" + +/ { + model = "Marvell CN9131 development board (CP NAND) setup(B)"; + compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; + +&cp1_comphy { + /* Serdes Configuration: + * Lane 0: PCIe0 (x2) + * Lane 1: PCIe0 (x2) + * Lane 2: SFI (port 0) + * Lane 3: USB1 + * Lane 4: SGMII (port 1) + * Lane 5: SATA1 + */ + phy0 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + phy1 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + phy2 { + phy-type = <COMPHY_TYPE_SFI0>; + phy-speed = <COMPHY_SPEED_10_3125G>; + }; + phy3 { + phy-type = <COMPHY_TYPE_USB3_HOST1>; + }; + phy4 { + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; + }; + phy5 { + phy-type = <COMPHY_TYPE_SATA1>; + }; +}; + +&cp1_ethernet { + status = "okay"; +}; + +/* 3310 RJ45 CON55 */ +&cp1_eth0 { + status = "okay"; + phy-mode = "sfi"; /* lane-2 */ + phy = <&sfi_phy8>; /* required by 3310 fw download */ +}; + +/* CON50 */ +&cp1_eth1 { + status = "okay"; + phy-mode = "sgmii"; /* lane-4 */ + marvell,sfp-tx-disable-gpio = <&cp1_gpio0 9 GPIO_ACTIVE_HIGH>; +}; + +&cp1_xmdio { + status = "okay"; + sfi_phy8: ethernet-phy@8 { + reg = <8>; + }; +}; diff --git a/arch/arm/dts/cn9131-db.dtsi b/arch/arm/dts/cn9131-db.dtsi new file mode 100644 index 0000000..5057605 --- /dev/null +++ b/arch/arm/dts/cn9131-db.dtsi @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#undef CP110_NAME +#undef CP110_NUM +#undef CP110_PCIE_MEM_SIZE +#undef CP110_PCIEx_CPU_MEM_BASE +#undef CP110_PCIEx_BUS_MEM_BASE + +/* CP110-1 Settings */ +#define CP110_NAME cp1 +#define CP110_NUM 1 +#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000) +#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) + +#include "armada-cp110.dtsi" + +/ { + model = "Marvell CN9131 development board"; + compatible = "marvell,cn9131-db"; + + aliases { + gpio3 = &cp1_gpio0; + gpio4 = &cp1_gpio1; + }; + + cp1 { + config-space { + cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_xhci0_vbus_pins>; + regulator-name = "cp1-xhci0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + regulator-force-boot-off; + gpio = <&cp1_gpio0 3 GPIO_ACTIVE_HIGH>; + }; + cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 { + compatible = "regulator-fixed"; + regulator-min-microamp = <900000>; + regulator-max-microamp = <900000>; + regulator-force-boot-off; + gpio = <&cp1_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + cp1_pcie_reset_pins: cp1-pcie-reset-pins { + marvell,pins = <0>; + marvell,function = <0>; + }; + }; + }; +}; + +&cp1_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp1_i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +/* CON40 */ +&cp1_pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp1_pcie_reset_pins>; + marvell,reset-gpio = <&cp1_gpio0 0 GPIO_ACTIVE_LOW>; + status = "okay"; + num-lanes = <2>; + /* non-prefetchable memory */ + ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>; +}; + +&cp1_pinctl { + compatible = "marvell,mvebu-pinctrl", + "marvell,cp115-standalone-pinctrl"; + bank-name ="cp1-110"; + + /* MPP Bus: + * [0-12] GPIO + * [13-16] SPI1 + * [17-27] GPIO (Default) + * [28] SATA1_PRESENT_ACTIVEn + * [29-34] GPIO (Default) + * [35-36] xSMI + * [37-38] I2C0 + * [39-62] GPIO + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x3 0x3 0x3 0x3 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9 0x0 + 0x0 0x0 0x0 0x0 0x0 0x7 0x7 0x2 0x2 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 >; + + cp1_i2c0_pins: cp1-i2c-pins-0 { + marvell,pins = < 37 38 >; + marvell,function = <2>; + }; + cp1_spi0_pins: cp1-spi-pins-0 { + marvell,pins = < 13 14 15 16 >; + marvell,function = <3>; + }; + cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins { + marvell,pins = <3>; + marvell,function = <0>; + }; +}; + +/* CON32 */ +&cp1_sata0 { + status = "okay"; +}; + +/* U24 */ +&cp1_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp1_spi0_pins>; + reg = <0x700680 0x50>, /* control */ + <0x2000000 0x1000000>, /* CS0 */ + <0 0xffffffff>, /* CS1 */ + <0 0xffffffff>, /* CS2 */ + <0 0xffffffff>; /* CS3 */ + status = "okay"; + + spi-flash@0 { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "jedec,spi-nor", "spi-flash"; + reg = <0x0>; + /* On-board MUX does not allow higher frequencies */ + spi-max-frequency = <40000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x200000>; + }; + + partition@400000 { + label = "Filesystem"; + reg = <0x200000 0xe00000>; + }; + }; + }; +}; + +/* CON58 */ +&cp1_usb3_1 { + vbus-supply = <&cp1_reg_usb3_vbus0>; + current-limiter = <&cp1_reg_usb3_current_lim0>; + vbus-disable-delay = <500>; + status = "okay"; +}; + +&cp1_utmi1 { + status = "okay"; +}; diff --git a/arch/arm/dts/cn9132-db-A.dts b/arch/arm/dts/cn9132-db-A.dts new file mode 100644 index 0000000..ba9b8a2 --- /dev/null +++ b/arch/arm/dts/cn9132-db-A.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#include "cn9131-db-A.dts" +#include "cn9132-db.dtsi" + +/ { + model = "Marvell CN9132 development board (CP NOR) setup(A)"; + compatible = "marvell,cn9132-db", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; diff --git a/arch/arm/dts/cn9132-db-B.dts b/arch/arm/dts/cn9132-db-B.dts new file mode 100644 index 0000000..e126e23 --- /dev/null +++ b/arch/arm/dts/cn9132-db-B.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#include "cn9131-db-B.dts" +#include "cn9132-db.dtsi" + +/ { + model = "Marvell CN9132 development board (CP NAND) setup(B)"; + compatible = "marvell,cn9132-db-B", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; diff --git a/arch/arm/dts/cn9132-db.dtsi b/arch/arm/dts/cn9132-db.dtsi new file mode 100644 index 0000000..d51a4d0 --- /dev/null +++ b/arch/arm/dts/cn9132-db.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018-2021 Marvell International Ltd. + */ + +#undef CP110_NAME +#undef CP110_NUM +#undef CP110_PCIE_MEM_SIZE +#undef CP110_PCIEx_CPU_MEM_BASE +#undef CP110_PCIEx_BUS_MEM_BASE + +/* CP110-2 Settings */ +#define CP110_NAME cp2 +#define CP110_NUM 2 +#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000) +#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) + +#include "armada-cp110.dtsi" + +/ { + model = "Marvell CN9132 development board"; + compatible = "marvell,cn9132-db"; + + aliases { + gpio5 = &cp2_gpio0; + gpio6 = &cp2_gpio1; + }; + + cp2 { + config-space { + sdhci@780000 { + vqmmc-supply = <&cp2_reg_sd_vccq>; + }; + + cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 { + compatible = "regulator-fixed"; + regulator-name = "cp2-xhci0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + regulator-force-boot-off; + gpio = <&cp2_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + + cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 { + compatible = "regulator-fixed"; + regulator-name = "cp2-xhci1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + regulator-force-boot-off; + gpio = <&cp2_gpio0 3 GPIO_ACTIVE_HIGH>; + }; + cp2_reg_sd_vccq: cp2_sd_vccq@0 { + compatible = "regulator-gpio"; + regulator-name = "cp2_sd_vcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + /* cp2_mpp49 */ + gpios = <&cp2_gpio1 17 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1 + 3300000 0x0>; + }; + cp2_reg_usb3_current_lim0: cp2_usb3_current_limiter@0 { + compatible = "regulator-fixed"; + regulator-min-microamp = <900000>; + regulator-max-microamp = <900000>; + regulator-force-boot-off; + gpio = <&cp2_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + cp2_reg_usb3_current_lim1: cp2_usb3_current_limiter@1 { + compatible = "regulator-fixed"; + regulator-min-microamp = <900000>; + regulator-max-microamp = <900000>; + regulator-force-boot-off; + gpio = <&cp2_gpio0 1 GPIO_ACTIVE_HIGH>; + }; + }; + }; +}; + +&cp2_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp2_i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cp2_pinctl { + compatible = "marvell,mvebu-pinctrl", + "marvell,cp115-standalone-pinctrl"; + bank-name ="cp2-110"; + + /* MPP Bus: + * [0-26] GPIO + * [27] SATA0_PRESENT_ACTIVEn + * [28] SATA1_PRESENT_ACTIVEn + * [29-31, 33] GPIO (Default) + * [32,34] SMI + * [37-38] I2C0 + * [39-53] GPIO + * [54] SD_CRD_RSTn (out) + * [55] SD_CRD_DT (in) + * [56-62] SDIO + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9 0x9 0x0 + 0x0 0x0 0x8 0x0 0x8 0x0 0x0 0x2 0x2 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0xa 0xb 0xe 0xe 0xe 0xe + 0xe 0xe 0xe >; + + cp2_i2c0_pins: cp2-i2c-pins-0 { + marvell,pins = < 37 38 >; + marvell,function = <2>; + }; + + cp2_sdhci_pins: cp2-sdhi-pins-0 { + marvell,pins = < 56 57 58 59 60 61 >; + marvell,function = <14>; + }; +}; + +&cp2_usb3_0 { + status = "okay"; + vbus-supply = <&cp2_reg_usb3_vbus0>; + current-limiter = <&cp2_reg_usb3_current_lim0>; + vbus-disable-delay = <500>; +}; + +/* SLM-1521-V2, CON11 */ +&cp2_usb3_1 { + status = "okay"; + vbus-supply = <&cp2_reg_usb3_vbus1>; + current-limiter = <&cp2_reg_usb3_current_lim1>; + vbus-disable-delay = <500>; + status = "okay"; +}; + +&cp2_utmi0 { + status = "okay"; +}; + +&cp2_utmi1 { + status = "okay"; +}; + +&cp2_comphy { + phy0 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + + phy1 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + + phy2 { + phy-type = <COMPHY_TYPE_SATA0>; + }; + + phy3 { + phy-type = <COMPHY_TYPE_USB3_HOST1>; + }; + + phy4 { + phy-type = <COMPHY_TYPE_SFI0>; + phy-speed = <COMPHY_SPEED_10_3125G>; + }; + + phy5 { + phy-type = <COMPHY_TYPE_PEX2>; + }; +}; + +&cp2_ethernet { + status = "okay"; +}; + +/* SLM-1521-V2, CON9 */ +&cp2_eth0 { + status = "okay"; + phy-mode = "sfi"; +}; + +/* SLM-1521-V2, CON6 */ +&cp2_pcie0 { + /* non-prefetchable memory */ + ranges =<0x82000000 0 0xe5000000 0 0xe5000000 0 0x1000000>; + num-lanes = <2>; + status = "okay"; +}; + +/* SLM-1521-V2, CON8 */ +&cp2_pcie2 { + num-lanes = <1>; + status = "okay"; +}; + +&cp2_pinctl { +}; + +/* SLM-1521-V2, CON4 */ +&cp2_sata0 { + status = "okay"; +}; + +/* CON 2 on SLM-1683 - microSD */ +&cp2_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp2_sdhci_pins>; + bus-width = <4>; + status = "okay"; +}; diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index 474327a..939abce 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -8,11 +8,13 @@ #include <dm.h> #include <fdtdec.h> #include <linux/libfdt.h> +#include <linux/sizes.h> #include <asm/io.h> #include <asm/system.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <asm/armv8/mmu.h> +#include <mach/fw_info.h> /* Armada 7k/8k */ #define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000)) @@ -23,62 +25,31 @@ #define BOOT_MODE_MASK 0x3f #define BOOT_MODE_OFFSET 4 -/* - * The following table includes all memory regions for Armada 7k and - * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets - * define these regions at the beginning of the struct so that they - * can be easier removed later dynamically if an Armada 7k device is detected. - * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt - */ -#define ARMADA_7K8K_COMMON_REGIONS_START 2 static struct mm_region mvebu_mem_map[] = { /* Armada 80x0 memory regions include the CP1 (slave) units */ { - /* SRAM, MMIO regions - CP110 slave region */ - .phys = 0xf4000000UL, - .virt = 0xf4000000UL, - .size = 0x02000000UL, /* 32MiB internal registers */ - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE - }, - { - /* PCI CP1 regions */ - .phys = 0xfa000000UL, - .virt = 0xfa000000UL, - .size = 0x04000000UL, /* 64MiB CP110 slave PCI space */ - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE - }, - /* Armada 80x0 and 70x0 common memory regions start here */ - { - /* RAM */ + /* RAM 0-64MB */ .phys = 0x0UL, .virt = 0x0UL, - .size = 0x80000000UL, + .size = ATF_REGION_START, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, + /* ATF and TEE region 0x4000000-0x5400000 not mapped */ { - /* SRAM, MMIO regions - AP806 region */ - .phys = 0xf0000000UL, - .virt = 0xf0000000UL, - .size = 0x01000000UL, /* 16MiB internal registers */ - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE - }, - { - /* SRAM, MMIO regions - CP110 master region */ - .phys = 0xf2000000UL, - .virt = 0xf2000000UL, - .size = 0x02000000UL, /* 32MiB internal registers */ - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE + /* RAM 66MB-2GB */ + .phys = ATF_REGION_END, + .virt = ATF_REGION_END, + .size = SZ_2G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE }, { - /* PCI CP0 regions */ - .phys = 0xf6000000UL, - .virt = 0xf6000000UL, - .size = 0x04000000UL, /* 64MiB CP110 master PCI space */ + /* MMIO regions */ + .phys = MMIO_REGS_PHY_BASE, + .virt = MMIO_REGS_PHY_BASE, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, @@ -91,15 +62,6 @@ struct mm_region *mem_map = mvebu_mem_map; void enable_caches(void) { - /* - * Armada 7k is not equipped with the CP110 slave CP. In case this - * code runs on an Armada 7k device, lets remove the CP110 slave - * entries from the memory mapping by moving the start to the - * common regions. - */ - if (of_machine_is_compatible("marvell,armada7040")) - mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START]; - icache_enable(); dcache_enable(); } diff --git a/arch/arm/mach-mvebu/include/mach/fw_info.h b/arch/arm/mach-mvebu/include/mach/fw_info.h new file mode 100644 index 0000000..1382438 --- /dev/null +++ b/arch/arm/mach-mvebu/include/mach/fw_info.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Marvell International Ltd. + */ + +#ifndef _FW_INFO_H_ +#define _FW_INFO_H_ + +/* Protected ATF and TEE region */ +#define ATF_REGION_START 0x4000000 +#define ATF_REGION_END 0x5400000 + +/* Firmware related definition used for SMC calls */ +#define MV_SIP_DRAM_SIZE 0x82000010 + +#define MMIO_REGS_PHY_BASE 0xc0000000 + +#endif /* _FW_INFO_H_ */ diff --git a/board/Marvell/octeontx2_cn913x/MAINTAINERS b/board/Marvell/octeontx2_cn913x/MAINTAINERS index d469e16..74c5fd1 100644 --- a/board/Marvell/octeontx2_cn913x/MAINTAINERS +++ b/board/Marvell/octeontx2_cn913x/MAINTAINERS @@ -3,3 +3,4 @@ M: Kostya Porotchkin <kostap@marvell.com> S: Maintained F: board/Marvell/octeontx2_cn913x/ F: configs/mvebu_crb_cn9130_defconfig +F: configs/mvebu_db_cn9130_defconfig diff --git a/board/Marvell/octeontx2_cn913x/README b/board/Marvell/octeontx2_cn913x/README new file mode 100644 index 0000000..3d0c8b3 --- /dev/null +++ b/board/Marvell/octeontx2_cn913x/README @@ -0,0 +1,24 @@ +Not all board variants are represented with a specific defconfig in +mainline U-Boot. Here a small documentation on how to generate U-Boot +images for all other board variants, available via different dts +files and defconfigs. + +Use a different dts than in the defconfig: + +make DEVICE_TREE=cn9131-db-B + +Use a different boot device (e.g. MMC or NAND instead of SPI NOR): + +For MMC, please make the following changes to the defconfig via +e.g. "make menuconfig": +Remove CONFIG_MVEBU_SPI_BOOT +Select CONFIG_MVEBU_MMC_BOOT +Remove CONFIG_ENV_IS_IN_SPI_FLASH +Select CONFIG_ENV_IS_IN_MMC + +For NAND, please make the following changes to the defconfig via +e.g. "make menuconfig": +Remove CONFIG_MVEBU_SPI_BOOT +Select CONFIG_MVEBU_NAND_BOOT +Remove CONFIG_ENV_IS_IN_SPI_FLASH +Select CONFIG_ENV_IS_IN_NAND diff --git a/cmd/mvebu/Kconfig b/cmd/mvebu/Kconfig index f0e4f88..7c42c75 100644 --- a/cmd/mvebu/Kconfig +++ b/cmd/mvebu/Kconfig @@ -49,11 +49,10 @@ config MVEBU_UBOOT_DFLT_NAME This option should contain a default file name to be used with MVEBU "bubt" command if the source file name is omitted -config CMD_MVEBU_RX_TRAINING - bool "rx_training" - depends on TARGET_MVEBU_ARMADA_8K - default n +config CMD_MVEBU_COMPHY_RX_TRAINING + bool "mvebu_comphy_rx_training" + depends on ARMADA_8K help - Perform RX training sequence + Perform COMPHY RX training sequence endmenu diff --git a/cmd/mvebu/Makefile b/cmd/mvebu/Makefile index 79299b0..ca96ad0 100644 --- a/cmd/mvebu/Makefile +++ b/cmd/mvebu/Makefile @@ -5,4 +5,4 @@ # https://spdx.org/licenses obj-$(CONFIG_CMD_MVEBU_BUBT) += bubt.o -obj-$(CONFIG_CMD_MVEBU_RX_TRAINING) += rx_training.o +obj-$(CONFIG_CMD_MVEBU_COMPHY_RX_TRAINING) += comphy_rx_training.o diff --git a/cmd/mvebu/rx_training.c b/cmd/mvebu/comphy_rx_training.c index 4bae765..0798dec 100644 --- a/cmd/mvebu/rx_training.c +++ b/cmd/mvebu/comphy_rx_training.c @@ -13,8 +13,8 @@ #include <dm/device-internal.h> #include <mvebu/comphy.h> -int rx_training_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char * const argv[]) +int mvebu_comphy_rx_training_cmd(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) { struct udevice *dev; struct uclass *uc; @@ -51,7 +51,7 @@ int rx_training_cmd(struct cmd_tbl *cmdtp, int flag, int argc, } U_BOOT_CMD( - rx_training, 3, 0, rx_training_cmd, - "rx_training <cp id> <comphy id>\n", - "\n\tRun RX training sequence, the user must state CP index (0/1) and comphy ID (0/5)" + mvebu_comphy_rx_training, 3, 0, mvebu_comphy_rx_training_cmd, + "mvebu_comphy_rx_training <cp id> <comphy id>\n", + "\n\tRun COMPHY RX training sequence, the user must state CP index (0/1) and comphy ID (0/5)" ); diff --git a/configs/mvebu_db_cn9130_defconfig b/configs/mvebu_db_cn9130_defconfig new file mode 100644 index 0000000..57fe525 --- /dev/null +++ b/configs/mvebu_db_cn9130_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_OCTEONTX2_CN913x=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x3f0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEBUG_UART_BASE=0xf0512000 +CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEFAULT_DEVICE_TREE="cn9130-db-A" +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="Marvell>> " +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_MVEBU_BUBT=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_MAC_PARTITION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_AHCI_MVEBU=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_MISC=y +CONFIG_MVEBU_SAR=y +CONFIG_MMC_BROKEN_CD=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_NAND_PXA3XX=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_GIGE=y +CONFIG_MVPP2=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCIE_DW_MVEBU=y +CONFIG_MVEBU_COMPHY_SUPPORT=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_8K=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y diff --git a/configs/x530_defconfig b/configs/x530_defconfig index 890c94b..76574c4 100644 --- a/configs/x530_defconfig +++ b/configs/x530_defconfig @@ -62,7 +62,6 @@ CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_PXA3XX=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_SPEED=50000000 -CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y @@ -84,3 +83,4 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_WDT=y CONFIG_WDT_ORION=y +CONFIG_SPL_TINY_MEMSET=y diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 93e57cf..0490fd3 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -115,6 +115,7 @@ struct pcie_dw_mvebu { int first_busno; /* IO and MEM PCI regions */ + int region_count; struct pci_region io; struct pci_region mem; }; @@ -267,9 +268,10 @@ static int pcie_dw_mvebu_read_config(const struct udevice *bus, pci_dev_t bdf, debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); *valuep = pci_conv_32_to_size(value, offset, size); - pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, - PCIE_ATU_TYPE_IO, pcie->io.phys_start, - pcie->io.bus_start, pcie->io.size); + if (pcie->region_count > 1) + pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_IO, pcie->io.phys_start, + pcie->io.bus_start, pcie->io.size); return 0; } @@ -312,9 +314,10 @@ static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf, value = pci_conv_size_to_32(old, value, offset, size); writel(value, va_address); - pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, - PCIE_ATU_TYPE_IO, pcie->io.phys_start, - pcie->io.bus_start, pcie->io.size); + if (pcie->region_count > 1) + pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_IO, pcie->io.phys_start, + pcie->io.bus_start, pcie->io.size); return 0; } @@ -513,14 +516,24 @@ static int pcie_dw_mvebu_probe(struct udevice *dev) hose->first_busno); } + pcie->region_count = hose->region_count - CONFIG_NR_DRAM_BANKS; + /* Store the IO and MEM windows settings for future use by the ATU */ - pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */ - pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */ - pcie->io.size = hose->regions[0].size; /* IO size */ + if (pcie->region_count > 1) { + /* IO base */ + pcie->io.phys_start = hose->regions[0].phys_start; + /* IO_bus_addr */ + pcie->io.bus_start = hose->regions[0].bus_start; + /* IO size */ + pcie->io.size = hose->regions[0].size; + } - pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */ - pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */ - pcie->mem.size = hose->regions[1].size; /* MEM size */ + /* MEM base */ + pcie->mem.phys_start = hose->regions[pcie->region_count - 1].phys_start; + /* MEM_bus_addr */ + pcie->mem.bus_start = hose->regions[pcie->region_count - 1].bus_start; + /* MEM size */ + pcie->mem.size = hose->regions[pcie->region_count - 1].size; pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1, PCIE_ATU_TYPE_MEM, pcie->mem.phys_start, diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 43812da..bc5da0a 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -110,13 +110,70 @@ static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen, static int mvebu_spi_set_speed(struct udevice *bus, uint hz) { struct mvebu_spi_plat *plat = dev_get_plat(bus); + struct dm_spi_bus *spi = dev_get_uclass_priv(bus); struct kwspi_registers *reg = plat->spireg; - u32 data; + u32 data, divider; + unsigned int spr, sppr; + + if (spi->max_hz && (hz > spi->max_hz)) { + debug("%s: limit speed to the max_hz of the bus %d\n", + __func__, spi->max_hz); + hz = spi->max_hz; + } + + /* + * Calculate spi clock prescaller using max_hz. + * SPPR is SPI Baud Rate Pre-selection, it holds bits 5 and 7:6 in + * SPI Interface Configuration Register; + * SPR is SPI Baud Rate Selection, it holds bits 3:0 in SPI Interface + * Configuration Register. + * The SPR together with the SPPR define the SPI CLK frequency as + * follows: + * SPI actual frequency = core_clk / (SPR * (2 ^ SPPR)) + */ + divider = DIV_ROUND_UP(CONFIG_SYS_TCLK, hz); + if (divider < 16) { + /* This is the easy case, divider is less than 16 */ + spr = divider; + sppr = 0; + + } else { + unsigned int two_pow_sppr; + /* + * Find the highest bit set in divider. This and the + * three next bits define SPR (apart from rounding). + * SPPR is then the number of zero bits that must be + * appended: + */ + sppr = fls(divider) - 4; + + /* + * As SPR only has 4 bits, we have to round divider up + * to the next multiple of 2 ** sppr. + */ + two_pow_sppr = 1 << sppr; + divider = (divider + two_pow_sppr - 1) & -two_pow_sppr; + + /* + * recalculate sppr as rounding up divider might have + * increased it enough to change the position of the + * highest set bit. In this case the bit that now + * doesn't make it into SPR is 0, so there is no need to + * round again. + */ + sppr = fls(divider) - 4; + spr = divider >> sppr; + + /* + * Now do range checking. SPR is constructed to have a + * width of 4 bits, so this is fine for sure. So we + * still need to check for sppr to fit into 3 bits: + */ + if (sppr > 7) + return -EINVAL; + } - /* calculate spi clock prescaller using max_hz */ - data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10; - data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data; - data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data; + data = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr; /* program spi clock prescaler using max_hz */ writel(KWSPI_ADRLEN_3BYTE | data, ®->cfg); |