Merge tag 'u-boot-rockchip-20210618' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into nextWIP/19Jun2021-next

- New SoC platform support: rk3568;
- rockchip pcie Code compile issue fix;
- Board fix for rk3399 Khadas Edge;
- Add Rockchip NFC driver;

39 files changed, 10837 insertions, 9 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0960682..9918e46 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -146,6 +146,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
 	rk3399-rockpro64.dtb \
 	rk3399pro-rock-pi-n10.dtb
 
+dtb-$(CONFIG_ROCKCHIP_RK3568) += \
+	rk3568-evb.dtb
+
 dtb-$(CONFIG_ROCKCHIP_RV1108) += \
 	rv1108-elgin-r1.dtb \
 	rv1108-evb.dtb
diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi b/arch/arm/dts/rk3568-evb-u-boot.dtsi
new file mode 100644
index 0000000..b03cbea
--- /dev/null
+++ b/arch/arm/dts/rk3568-evb-u-boot.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&sdmmc0 {
+	status = "okay";
+};
+
+&uart2 {
+	clock-frequency = <24000000>;
+	u-boot,dm-spl;
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-evb.dts b/arch/arm/dts/rk3568-evb.dts
new file mode 100644
index 0000000..6978655
--- /dev/null
+++ b/arch/arm/dts/rk3568-evb.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
+	compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc3v3_lcd0_n: vcc3v3-lcd0-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd0_n";
+		regulator-boot-on;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vcc3v3_lcd1_n: vcc3v3-lcd1-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd1_n";
+		regulator-boot-on;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-pinctrl.dtsi b/arch/arm/dts/rk3568-pinctrl.dtsi
new file mode 100644
index 0000000..a588ca9
--- /dev/null
+++ b/arch/arm/dts/rk3568-pinctrl.dtsi
@@ -0,0 +1,3111 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+	acodec {
+		/omit-if-no-ref/
+		acodec_pins: acodec-pins {
+			rockchip,pins =
+				/* acodec_adc_sync */
+				<1 RK_PB1 5 &pcfg_pull_none>,
+				/* acodec_adcclk */
+				<1 RK_PA1 5 &pcfg_pull_none>,
+				/* acodec_adcdata */
+				<1 RK_PA0 5 &pcfg_pull_none>,
+				/* acodec_dac_datal */
+				<1 RK_PA7 5 &pcfg_pull_none>,
+				/* acodec_dac_datar */
+				<1 RK_PB0 5 &pcfg_pull_none>,
+				/* acodec_dacclk */
+				<1 RK_PA3 5 &pcfg_pull_none>,
+				/* acodec_dacsync */
+				<1 RK_PA5 5 &pcfg_pull_none>;
+		};
+	};
+
+	audiopwm {
+		/omit-if-no-ref/
+		audiopwm_lout: audiopwm-lout {
+			rockchip,pins =
+				/* audiopwm_lout */
+				<1 RK_PA0 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		audiopwm_loutn: audiopwm-loutn {
+			rockchip,pins =
+				/* audiopwm_loutn */
+				<1 RK_PA1 6 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		audiopwm_loutp: audiopwm-loutp {
+			rockchip,pins =
+				/* audiopwm_loutp */
+				<1 RK_PA0 6 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		audiopwm_rout: audiopwm-rout {
+			rockchip,pins =
+				/* audiopwm_rout */
+				<1 RK_PA1 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		audiopwm_routn: audiopwm-routn {
+			rockchip,pins =
+				/* audiopwm_routn */
+				<1 RK_PA7 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		audiopwm_routp: audiopwm-routp {
+			rockchip,pins =
+				/* audiopwm_routp */
+				<1 RK_PA6 4 &pcfg_pull_none>;
+		};
+	};
+
+	bt656 {
+		/omit-if-no-ref/
+		bt656m0_pins: bt656m0-pins {
+			rockchip,pins =
+				/* bt656_clkm0 */
+				<3 RK_PA0 2 &pcfg_pull_none>,
+				/* bt656_d0m0 */
+				<2 RK_PD0 2 &pcfg_pull_none>,
+				/* bt656_d1m0 */
+				<2 RK_PD1 2 &pcfg_pull_none>,
+				/* bt656_d2m0 */
+				<2 RK_PD2 2 &pcfg_pull_none>,
+				/* bt656_d3m0 */
+				<2 RK_PD3 2 &pcfg_pull_none>,
+				/* bt656_d4m0 */
+				<2 RK_PD4 2 &pcfg_pull_none>,
+				/* bt656_d5m0 */
+				<2 RK_PD5 2 &pcfg_pull_none>,
+				/* bt656_d6m0 */
+				<2 RK_PD6 2 &pcfg_pull_none>,
+				/* bt656_d7m0 */
+				<2 RK_PD7 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		bt656m1_pins: bt656m1-pins {
+			rockchip,pins =
+				/* bt656_clkm1 */
+				<4 RK_PB4 5 &pcfg_pull_none>,
+				/* bt656_d0m1 */
+				<3 RK_PC6 5 &pcfg_pull_none>,
+				/* bt656_d1m1 */
+				<3 RK_PC7 5 &pcfg_pull_none>,
+				/* bt656_d2m1 */
+				<3 RK_PD0 5 &pcfg_pull_none>,
+				/* bt656_d3m1 */
+				<3 RK_PD1 5 &pcfg_pull_none>,
+				/* bt656_d4m1 */
+				<3 RK_PD2 5 &pcfg_pull_none>,
+				/* bt656_d5m1 */
+				<3 RK_PD3 5 &pcfg_pull_none>,
+				/* bt656_d6m1 */
+				<3 RK_PD4 5 &pcfg_pull_none>,
+				/* bt656_d7m1 */
+				<3 RK_PD5 5 &pcfg_pull_none>;
+		};
+	};
+
+	bt1120 {
+		/omit-if-no-ref/
+		bt1120_pins: bt1120-pins {
+			rockchip,pins =
+				/* bt1120_clk */
+				<3 RK_PA6 2 &pcfg_pull_none>,
+				/* bt1120_d0 */
+				<3 RK_PA1 2 &pcfg_pull_none>,
+				/* bt1120_d1 */
+				<3 RK_PA2 2 &pcfg_pull_none>,
+				/* bt1120_d2 */
+				<3 RK_PA3 2 &pcfg_pull_none>,
+				/* bt1120_d3 */
+				<3 RK_PA4 2 &pcfg_pull_none>,
+				/* bt1120_d4 */
+				<3 RK_PA5 2 &pcfg_pull_none>,
+				/* bt1120_d5 */
+				<3 RK_PA7 2 &pcfg_pull_none>,
+				/* bt1120_d6 */
+				<3 RK_PB0 2 &pcfg_pull_none>,
+				/* bt1120_d7 */
+				<3 RK_PB1 2 &pcfg_pull_none>,
+				/* bt1120_d8 */
+				<3 RK_PB2 2 &pcfg_pull_none>,
+				/* bt1120_d9 */
+				<3 RK_PB3 2 &pcfg_pull_none>,
+				/* bt1120_d10 */
+				<3 RK_PB4 2 &pcfg_pull_none>,
+				/* bt1120_d11 */
+				<3 RK_PB5 2 &pcfg_pull_none>,
+				/* bt1120_d12 */
+				<3 RK_PB6 2 &pcfg_pull_none>,
+				/* bt1120_d13 */
+				<3 RK_PC1 2 &pcfg_pull_none>,
+				/* bt1120_d14 */
+				<3 RK_PC2 2 &pcfg_pull_none>,
+				/* bt1120_d15 */
+				<3 RK_PC3 2 &pcfg_pull_none>;
+		};
+	};
+
+	cam {
+		/omit-if-no-ref/
+		cam_clkout0: cam-clkout0 {
+			rockchip,pins =
+				/* cam_clkout0 */
+				<4 RK_PA7 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		cam_clkout1: cam-clkout1 {
+			rockchip,pins =
+				/* cam_clkout1 */
+				<4 RK_PB0 1 &pcfg_pull_none>;
+		};
+	};
+
+	can0 {
+		/omit-if-no-ref/
+		can0m0_pins: can0m0-pins {
+			rockchip,pins =
+				/* can0_rxm0 */
+				<0 RK_PB4 2 &pcfg_pull_none>,
+				/* can0_txm0 */
+				<0 RK_PB3 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		can0m1_pins: can0m1-pins {
+			rockchip,pins =
+				/* can0_rxm1 */
+				<2 RK_PA2 4 &pcfg_pull_none>,
+				/* can0_txm1 */
+				<2 RK_PA1 4 &pcfg_pull_none>;
+		};
+	};
+
+	can1 {
+		/omit-if-no-ref/
+		can1m0_pins: can1m0-pins {
+			rockchip,pins =
+				/* can1_rxm0 */
+				<1 RK_PA0 3 &pcfg_pull_none>,
+				/* can1_txm0 */
+				<1 RK_PA1 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		can1m1_pins: can1m1-pins {
+			rockchip,pins =
+				/* can1_rxm1 */
+				<4 RK_PC2 3 &pcfg_pull_none>,
+				/* can1_txm1 */
+				<4 RK_PC3 3 &pcfg_pull_none>;
+		};
+	};
+
+	can2 {
+		/omit-if-no-ref/
+		can2m0_pins: can2m0-pins {
+			rockchip,pins =
+				/* can2_rxm0 */
+				<4 RK_PB4 3 &pcfg_pull_none>,
+				/* can2_txm0 */
+				<4 RK_PB5 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		can2m1_pins: can2m1-pins {
+			rockchip,pins =
+				/* can2_rxm1 */
+				<2 RK_PB1 4 &pcfg_pull_none>,
+				/* can2_txm1 */
+				<2 RK_PB2 4 &pcfg_pull_none>;
+		};
+	};
+
+	cif {
+		/omit-if-no-ref/
+		cif_clk: cif-clk {
+			rockchip,pins =
+				/* cif_clkout */
+				<4 RK_PC0 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		cif_dvp_clk: cif-dvp-clk {
+			rockchip,pins =
+				/* cif_clkin */
+				<4 RK_PC1 1 &pcfg_pull_none>,
+				/* cif_href */
+				<4 RK_PB6 1 &pcfg_pull_none>,
+				/* cif_vsync */
+				<4 RK_PB7 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		cif_dvp_bus16: cif-dvp-bus16 {
+			rockchip,pins =
+				/* cif_d8 */
+				<3 RK_PD6 1 &pcfg_pull_none>,
+				/* cif_d9 */
+				<3 RK_PD7 1 &pcfg_pull_none>,
+				/* cif_d10 */
+				<4 RK_PA0 1 &pcfg_pull_none>,
+				/* cif_d11 */
+				<4 RK_PA1 1 &pcfg_pull_none>,
+				/* cif_d12 */
+				<4 RK_PA2 1 &pcfg_pull_none>,
+				/* cif_d13 */
+				<4 RK_PA3 1 &pcfg_pull_none>,
+				/* cif_d14 */
+				<4 RK_PA4 1 &pcfg_pull_none>,
+				/* cif_d15 */
+				<4 RK_PA5 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		cif_dvp_bus8: cif-dvp-bus8 {
+			rockchip,pins =
+				/* cif_d0 */
+				<3 RK_PC6 1 &pcfg_pull_none>,
+				/* cif_d1 */
+				<3 RK_PC7 1 &pcfg_pull_none>,
+				/* cif_d2 */
+				<3 RK_PD0 1 &pcfg_pull_none>,
+				/* cif_d3 */
+				<3 RK_PD1 1 &pcfg_pull_none>,
+				/* cif_d4 */
+				<3 RK_PD2 1 &pcfg_pull_none>,
+				/* cif_d5 */
+				<3 RK_PD3 1 &pcfg_pull_none>,
+				/* cif_d6 */
+				<3 RK_PD4 1 &pcfg_pull_none>,
+				/* cif_d7 */
+				<3 RK_PD5 1 &pcfg_pull_none>;
+		};
+	};
+
+	clk32k {
+		/omit-if-no-ref/
+		clk32k_in: clk32k-in {
+			rockchip,pins =
+				/* clk32k_in */
+				<0 RK_PB0 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		clk32k_out0: clk32k-out0 {
+			rockchip,pins =
+				/* clk32k_out0 */
+				<0 RK_PB0 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		clk32k_out1: clk32k-out1 {
+			rockchip,pins =
+				/* clk32k_out1 */
+				<2 RK_PC6 1 &pcfg_pull_none>;
+		};
+	};
+
+	cpu {
+		/omit-if-no-ref/
+		cpu_pins: cpu-pins {
+			rockchip,pins =
+				/* cpu_avs */
+				<0 RK_PB7 2 &pcfg_pull_none>;
+		};
+	};
+
+	ebc {
+		/omit-if-no-ref/
+		ebc_extern: ebc-extern {
+			rockchip,pins =
+				/* ebc_sdce1 */
+				<4 RK_PA7 2 &pcfg_pull_none>,
+				/* ebc_sdce2 */
+				<4 RK_PB0 2 &pcfg_pull_none>,
+				/* ebc_sdce3 */
+				<4 RK_PB1 2 &pcfg_pull_none>,
+				/* ebc_sdshr */
+				<4 RK_PB5 2 &pcfg_pull_none>,
+				/* ebc_vcom */
+				<4 RK_PB2 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		ebc_pins: ebc-pins {
+			rockchip,pins =
+				/* ebc_gdclk */
+				<4 RK_PC0 2 &pcfg_pull_none>,
+				/* ebc_gdoe */
+				<4 RK_PB3 2 &pcfg_pull_none>,
+				/* ebc_gdsp */
+				<4 RK_PB4 2 &pcfg_pull_none>,
+				/* ebc_sdce0 */
+				<4 RK_PA6 2 &pcfg_pull_none>,
+				/* ebc_sdclk */
+				<4 RK_PC1 2 &pcfg_pull_none>,
+				/* ebc_sddo0 */
+				<3 RK_PC6 2 &pcfg_pull_none>,
+				/* ebc_sddo1 */
+				<3 RK_PC7 2 &pcfg_pull_none>,
+				/* ebc_sddo2 */
+				<3 RK_PD0 2 &pcfg_pull_none>,
+				/* ebc_sddo3 */
+				<3 RK_PD1 2 &pcfg_pull_none>,
+				/* ebc_sddo4 */
+				<3 RK_PD2 2 &pcfg_pull_none>,
+				/* ebc_sddo5 */
+				<3 RK_PD3 2 &pcfg_pull_none>,
+				/* ebc_sddo6 */
+				<3 RK_PD4 2 &pcfg_pull_none>,
+				/* ebc_sddo7 */
+				<3 RK_PD5 2 &pcfg_pull_none>,
+				/* ebc_sddo8 */
+				<3 RK_PD6 2 &pcfg_pull_none>,
+				/* ebc_sddo9 */
+				<3 RK_PD7 2 &pcfg_pull_none>,
+				/* ebc_sddo10 */
+				<4 RK_PA0 2 &pcfg_pull_none>,
+				/* ebc_sddo11 */
+				<4 RK_PA1 2 &pcfg_pull_none>,
+				/* ebc_sddo12 */
+				<4 RK_PA2 2 &pcfg_pull_none>,
+				/* ebc_sddo13 */
+				<4 RK_PA3 2 &pcfg_pull_none>,
+				/* ebc_sddo14 */
+				<4 RK_PA4 2 &pcfg_pull_none>,
+				/* ebc_sddo15 */
+				<4 RK_PA5 2 &pcfg_pull_none>,
+				/* ebc_sdle */
+				<4 RK_PB6 2 &pcfg_pull_none>,
+				/* ebc_sdoe */
+				<4 RK_PB7 2 &pcfg_pull_none>;
+		};
+	};
+
+	edpdp {
+		/omit-if-no-ref/
+		edpdpm0_pins: edpdpm0-pins {
+			rockchip,pins =
+				/* edpdp_hpdinm0 */
+				<4 RK_PC4 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		edpdpm1_pins: edpdpm1-pins {
+			rockchip,pins =
+				/* edpdp_hpdinm1 */
+				<0 RK_PC2 2 &pcfg_pull_none>;
+		};
+	};
+
+	emmc {
+		/omit-if-no-ref/
+		emmc_rstnout: emmc-rstnout {
+			rockchip,pins =
+				/* emmc_rstn */
+				<1 RK_PC7 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		emmc_bus8: emmc-bus8 {
+			rockchip,pins =
+				/* emmc_d0 */
+				<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d1 */
+				<1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d2 */
+				<1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d3 */
+				<1 RK_PB7 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d4 */
+				<1 RK_PC0 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d5 */
+				<1 RK_PC1 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d6 */
+				<1 RK_PC2 1 &pcfg_pull_up_drv_level_2>,
+				/* emmc_d7 */
+				<1 RK_PC3 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		emmc_clk: emmc-clk {
+			rockchip,pins =
+				/* emmc_clkout */
+				<1 RK_PC5 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		emmc_cmd: emmc-cmd {
+			rockchip,pins =
+				/* emmc_cmd */
+				<1 RK_PC4 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		emmc_datastrobe: emmc-datastrobe {
+			rockchip,pins =
+				/* emmc_datastrobe */
+				<1 RK_PC6 1 &pcfg_pull_none>;
+		};
+	};
+
+	eth0 {
+		/omit-if-no-ref/
+		eth0_pins: eth0-pins {
+			rockchip,pins =
+				/* eth0_refclko25m */
+				<2 RK_PC1 2 &pcfg_pull_none>;
+		};
+	};
+
+	eth1 {
+		/omit-if-no-ref/
+		eth1m0_pins: eth1m0-pins {
+			rockchip,pins =
+				/* eth1_refclko25mm0 */
+				<3 RK_PB0 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		eth1m1_pins: eth1m1-pins {
+			rockchip,pins =
+				/* eth1_refclko25mm1 */
+				<4 RK_PB3 3 &pcfg_pull_none>;
+		};
+	};
+
+	flash {
+		/omit-if-no-ref/
+		flash_pins: flash-pins {
+			rockchip,pins =
+				/* flash_ale */
+				<1 RK_PD0 2 &pcfg_pull_none>,
+				/* flash_cle */
+				<1 RK_PC6 3 &pcfg_pull_none>,
+				/* flash_cs0n */
+				<1 RK_PD3 2 &pcfg_pull_none>,
+				/* flash_cs1n */
+				<1 RK_PD4 2 &pcfg_pull_none>,
+				/* flash_d0 */
+				<1 RK_PB4 2 &pcfg_pull_none>,
+				/* flash_d1 */
+				<1 RK_PB5 2 &pcfg_pull_none>,
+				/* flash_d2 */
+				<1 RK_PB6 2 &pcfg_pull_none>,
+				/* flash_d3 */
+				<1 RK_PB7 2 &pcfg_pull_none>,
+				/* flash_d4 */
+				<1 RK_PC0 2 &pcfg_pull_none>,
+				/* flash_d5 */
+				<1 RK_PC1 2 &pcfg_pull_none>,
+				/* flash_d6 */
+				<1 RK_PC2 2 &pcfg_pull_none>,
+				/* flash_d7 */
+				<1 RK_PC3 2 &pcfg_pull_none>,
+				/* flash_dqs */
+				<1 RK_PC5 2 &pcfg_pull_none>,
+				/* flash_rdn */
+				<1 RK_PD2 2 &pcfg_pull_none>,
+				/* flash_rdy */
+				<1 RK_PD1 2 &pcfg_pull_none>,
+				/* flash_volsel */
+				<0 RK_PA7 1 &pcfg_pull_none>,
+				/* flash_wpn */
+				<1 RK_PC7 3 &pcfg_pull_none>,
+				/* flash_wrn */
+				<1 RK_PC4 2 &pcfg_pull_none>;
+		};
+	};
+
+	fspi {
+		/omit-if-no-ref/
+		fspi_pins: fspi-pins {
+			rockchip,pins =
+				/* fspi_clk */
+				<1 RK_PD0 1 &pcfg_pull_none>,
+				/* fspi_cs0n */
+				<1 RK_PD3 1 &pcfg_pull_none>,
+				/* fspi_d0 */
+				<1 RK_PD1 1 &pcfg_pull_none>,
+				/* fspi_d1 */
+				<1 RK_PD2 1 &pcfg_pull_none>,
+				/* fspi_d2 */
+				<1 RK_PC7 2 &pcfg_pull_none>,
+				/* fspi_d3 */
+				<1 RK_PD4 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		fspi_cs1: fspi-cs1 {
+			rockchip,pins =
+				/* fspi_cs1n */
+				<1 RK_PC6 2 &pcfg_pull_up>;
+		};
+	};
+
+	gmac0 {
+		/omit-if-no-ref/
+		gmac0_miim: gmac0-miim {
+			rockchip,pins =
+				/* gmac0_mdc */
+				<2 RK_PC3 2 &pcfg_pull_none>,
+				/* gmac0_mdio */
+				<2 RK_PC4 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac0_clkinout: gmac0-clkinout {
+			rockchip,pins =
+				/* gmac0_mclkinout */
+				<2 RK_PC2 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac0_rx_er: gmac0-rx-er {
+			rockchip,pins =
+				/* gmac0_rxer */
+				<2 RK_PC5 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac0_rx_bus2: gmac0-rx-bus2 {
+			rockchip,pins =
+				/* gmac0_rxd0 */
+				<2 RK_PB6 1 &pcfg_pull_none>,
+				/* gmac0_rxd1 */
+				<2 RK_PB7 2 &pcfg_pull_none>,
+				/* gmac0_rxdvcrs */
+				<2 RK_PC0 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac0_tx_bus2: gmac0-tx-bus2 {
+			rockchip,pins =
+				/* gmac0_txd0 */
+				<2 RK_PB3 1 &pcfg_pull_none_drv_level_2>,
+				/* gmac0_txd1 */
+				<2 RK_PB4 1 &pcfg_pull_none_drv_level_2>,
+				/* gmac0_txen */
+				<2 RK_PB5 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac0_rgmii_clk: gmac0-rgmii-clk {
+			rockchip,pins =
+				/* gmac0_rxclk */
+				<2 RK_PA5 2 &pcfg_pull_none>,
+				/* gmac0_txclk */
+				<2 RK_PB0 2 &pcfg_pull_none_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		gmac0_rgmii_bus: gmac0-rgmii-bus {
+			rockchip,pins =
+				/* gmac0_rxd2 */
+				<2 RK_PA3 2 &pcfg_pull_none>,
+				/* gmac0_rxd3 */
+				<2 RK_PA4 2 &pcfg_pull_none>,
+				/* gmac0_txd2 */
+				<2 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
+				/* gmac0_txd3 */
+				<2 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
+		};
+	};
+
+	gmac1 {
+		/omit-if-no-ref/
+		gmac1m0_miim: gmac1m0-miim {
+			rockchip,pins =
+				/* gmac1_mdcm0 */
+				<3 RK_PC4 3 &pcfg_pull_none>,
+				/* gmac1_mdiom0 */
+				<3 RK_PC5 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m0_clkinout: gmac1m0-clkinout {
+			rockchip,pins =
+				/* gmac1_mclkinoutm0 */
+				<3 RK_PC0 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m0_rx_er: gmac1m0-rx-er {
+			rockchip,pins =
+				/* gmac1_rxerm0 */
+				<3 RK_PB4 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
+			rockchip,pins =
+				/* gmac1_rxd0m0 */
+				<3 RK_PB1 3 &pcfg_pull_none>,
+				/* gmac1_rxd1m0 */
+				<3 RK_PB2 3 &pcfg_pull_none>,
+				/* gmac1_rxdvcrsm0 */
+				<3 RK_PB3 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
+			rockchip,pins =
+				/* gmac1_txd0m0 */
+				<3 RK_PB5 3 &pcfg_pull_none_drv_level_2>,
+				/* gmac1_txd1m0 */
+				<3 RK_PB6 3 &pcfg_pull_none_drv_level_2>,
+				/* gmac1_txenm0 */
+				<3 RK_PB7 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
+			rockchip,pins =
+				/* gmac1_rxclkm0 */
+				<3 RK_PA7 3 &pcfg_pull_none>,
+				/* gmac1_txclkm0 */
+				<3 RK_PA6 3 &pcfg_pull_none_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
+			rockchip,pins =
+				/* gmac1_rxd2m0 */
+				<3 RK_PA4 3 &pcfg_pull_none>,
+				/* gmac1_rxd3m0 */
+				<3 RK_PA5 3 &pcfg_pull_none>,
+				/* gmac1_txd2m0 */
+				<3 RK_PA2 3 &pcfg_pull_none_drv_level_2>,
+				/* gmac1_txd3m0 */
+				<3 RK_PA3 3 &pcfg_pull_none_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m1_miim: gmac1m1-miim {
+			rockchip,pins =
+				/* gmac1_mdcm1 */
+				<4 RK_PB6 3 &pcfg_pull_none>,
+				/* gmac1_mdiom1 */
+				<4 RK_PB7 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m1_clkinout: gmac1m1-clkinout {
+			rockchip,pins =
+				/* gmac1_mclkinoutm1 */
+				<4 RK_PC1 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m1_rx_er: gmac1m1-rx-er {
+			rockchip,pins =
+				/* gmac1_rxerm1 */
+				<4 RK_PB2 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m1_rx_bus2: gmac1m1-rx-bus2 {
+			rockchip,pins =
+				/* gmac1_rxd0m1 */
+				<4 RK_PA7 3 &pcfg_pull_none>,
+				/* gmac1_rxd1m1 */
+				<4 RK_PB0 3 &pcfg_pull_none>,
+				/* gmac1_rxdvcrsm1 */
+				<4 RK_PB1 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m1_tx_bus2: gmac1m1-tx-bus2 {
+			rockchip,pins =
+				/* gmac1_txd0m1 */
+				<4 RK_PA4 3 &pcfg_pull_none_drv_level_2>,
+				/* gmac1_txd1m1 */
+				<4 RK_PA5 3 &pcfg_pull_none_drv_level_2>,
+				/* gmac1_txenm1 */
+				<4 RK_PA6 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m1_rgmii_clk: gmac1m1-rgmii-clk {
+			rockchip,pins =
+				/* gmac1_rxclkm1 */
+				<4 RK_PA3 3 &pcfg_pull_none>,
+				/* gmac1_txclkm1 */
+				<4 RK_PA0 3 &pcfg_pull_none_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m1_rgmii_bus: gmac1m1-rgmii-bus {
+			rockchip,pins =
+				/* gmac1_rxd2m1 */
+				<4 RK_PA1 3 &pcfg_pull_none>,
+				/* gmac1_rxd3m1 */
+				<4 RK_PA2 3 &pcfg_pull_none>,
+				/* gmac1_txd2m1 */
+				<3 RK_PD6 3 &pcfg_pull_none_drv_level_2>,
+				/* gmac1_txd3m1 */
+				<3 RK_PD7 3 &pcfg_pull_none_drv_level_2>;
+		};
+	};
+
+	gpu {
+		/omit-if-no-ref/
+		gpu_pins: gpu-pins {
+			rockchip,pins =
+				/* gpu_avs */
+				<0 RK_PC0 2 &pcfg_pull_none>,
+				/* gpu_pwren */
+				<0 RK_PA6 4 &pcfg_pull_none>;
+		};
+	};
+
+	hdmitx {
+		/omit-if-no-ref/
+		hdmitxm0_cec: hdmitxm0-cec {
+			rockchip,pins =
+				/* hdmitxm0_cec */
+				<4 RK_PD1 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		hdmitxm1_cec: hdmitxm1-cec {
+			rockchip,pins =
+				/* hdmitxm1_cec */
+				<0 RK_PC7 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		hdmitx_scl: hdmitx-scl {
+			rockchip,pins =
+				/* hdmitx_scl */
+				<4 RK_PC7 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		hdmitx_sda: hdmitx-sda {
+			rockchip,pins =
+				/* hdmitx_sda */
+				<4 RK_PD0 1 &pcfg_pull_none>;
+		};
+	};
+
+	i2c0 {
+		/omit-if-no-ref/
+		i2c0_xfer: i2c0-xfer {
+			rockchip,pins =
+				/* i2c0_scl */
+				<0 RK_PB1 1 &pcfg_pull_none_smt>,
+				/* i2c0_sda */
+				<0 RK_PB2 1 &pcfg_pull_none_smt>;
+		};
+	};
+
+	i2c1 {
+		/omit-if-no-ref/
+		i2c1_xfer: i2c1-xfer {
+			rockchip,pins =
+				/* i2c1_scl */
+				<0 RK_PB3 1 &pcfg_pull_none_smt>,
+				/* i2c1_sda */
+				<0 RK_PB4 1 &pcfg_pull_none_smt>;
+		};
+	};
+
+	i2c2 {
+		/omit-if-no-ref/
+		i2c2m0_xfer: i2c2m0-xfer {
+			rockchip,pins =
+				/* i2c2_sclm0 */
+				<0 RK_PB5 1 &pcfg_pull_none_smt>,
+				/* i2c2_sdam0 */
+				<0 RK_PB6 1 &pcfg_pull_none_smt>;
+		};
+
+		/omit-if-no-ref/
+		i2c2m1_xfer: i2c2m1-xfer {
+			rockchip,pins =
+				/* i2c2_sclm1 */
+				<4 RK_PB5 1 &pcfg_pull_none_smt>,
+				/* i2c2_sdam1 */
+				<4 RK_PB4 1 &pcfg_pull_none_smt>;
+		};
+	};
+
+	i2c3 {
+		/omit-if-no-ref/
+		i2c3m0_xfer: i2c3m0-xfer {
+			rockchip,pins =
+				/* i2c3_sclm0 */
+				<1 RK_PA1 1 &pcfg_pull_none_smt>,
+				/* i2c3_sdam0 */
+				<1 RK_PA0 1 &pcfg_pull_none_smt>;
+		};
+
+		/omit-if-no-ref/
+		i2c3m1_xfer: i2c3m1-xfer {
+			rockchip,pins =
+				/* i2c3_sclm1 */
+				<3 RK_PB5 4 &pcfg_pull_none_smt>,
+				/* i2c3_sdam1 */
+				<3 RK_PB6 4 &pcfg_pull_none_smt>;
+		};
+	};
+
+	i2c4 {
+		/omit-if-no-ref/
+		i2c4m0_xfer: i2c4m0-xfer {
+			rockchip,pins =
+				/* i2c4_sclm0 */
+				<4 RK_PB3 1 &pcfg_pull_none_smt>,
+				/* i2c4_sdam0 */
+				<4 RK_PB2 1 &pcfg_pull_none_smt>;
+		};
+
+		/omit-if-no-ref/
+		i2c4m1_xfer: i2c4m1-xfer {
+			rockchip,pins =
+				/* i2c4_sclm1 */
+				<2 RK_PB2 2 &pcfg_pull_none_smt>,
+				/* i2c4_sdam1 */
+				<2 RK_PB1 2 &pcfg_pull_none_smt>;
+		};
+	};
+
+	i2c5 {
+		/omit-if-no-ref/
+		i2c5m0_xfer: i2c5m0-xfer {
+			rockchip,pins =
+				/* i2c5_sclm0 */
+				<3 RK_PB3 4 &pcfg_pull_none_smt>,
+				/* i2c5_sdam0 */
+				<3 RK_PB4 4 &pcfg_pull_none_smt>;
+		};
+
+		/omit-if-no-ref/
+		i2c5m1_xfer: i2c5m1-xfer {
+			rockchip,pins =
+				/* i2c5_sclm1 */
+				<4 RK_PC7 2 &pcfg_pull_none_smt>,
+				/* i2c5_sdam1 */
+				<4 RK_PD0 2 &pcfg_pull_none_smt>;
+		};
+	};
+
+	i2s1 {
+		/omit-if-no-ref/
+		i2s1m0_lrckrx: i2s1m0-lrckrx {
+			rockchip,pins =
+				/* i2s1m0_lrckrx */
+				<1 RK_PA6 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m0_lrcktx: i2s1m0-lrcktx {
+			rockchip,pins =
+				/* i2s1m0_lrcktx */
+				<1 RK_PA5 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m0_mclk: i2s1m0-mclk {
+			rockchip,pins =
+				/* i2s1m0_mclk */
+				<1 RK_PA2 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m0_sclkrx: i2s1m0-sclkrx {
+			rockchip,pins =
+				/* i2s1m0_sclkrx */
+				<1 RK_PA4 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m0_sclktx: i2s1m0-sclktx {
+			rockchip,pins =
+				/* i2s1m0_sclktx */
+				<1 RK_PA3 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m0_sdi0: i2s1m0-sdi0 {
+			rockchip,pins =
+				/* i2s1m0_sdi0 */
+				<1 RK_PB3 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m0_sdi1: i2s1m0-sdi1 {
+			rockchip,pins =
+				/* i2s1m0_sdi1 */
+				<1 RK_PB2 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m0_sdi2: i2s1m0-sdi2 {
+			rockchip,pins =
+				/* i2s1m0_sdi2 */
+				<1 RK_PB1 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m0_sdi3: i2s1m0-sdi3 {
+			rockchip,pins =
+				/* i2s1m0_sdi3 */
+				<1 RK_PB0 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m0_sdo0: i2s1m0-sdo0 {
+			rockchip,pins =
+				/* i2s1m0_sdo0 */
+				<1 RK_PA7 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m0_sdo1: i2s1m0-sdo1 {
+			rockchip,pins =
+				/* i2s1m0_sdo1 */
+				<1 RK_PB0 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m0_sdo2: i2s1m0-sdo2 {
+			rockchip,pins =
+				/* i2s1m0_sdo2 */
+				<1 RK_PB1 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m0_sdo3: i2s1m0-sdo3 {
+			rockchip,pins =
+				/* i2s1m0_sdo3 */
+				<1 RK_PB2 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m1_lrckrx: i2s1m1-lrckrx {
+			rockchip,pins =
+				/* i2s1m1_lrckrx */
+				<4 RK_PA7 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m1_lrcktx: i2s1m1-lrcktx {
+			rockchip,pins =
+				/* i2s1m1_lrcktx */
+				<3 RK_PD0 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m1_mclk: i2s1m1-mclk {
+			rockchip,pins =
+				/* i2s1m1_mclk */
+				<3 RK_PC6 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m1_sclkrx: i2s1m1-sclkrx {
+			rockchip,pins =
+				/* i2s1m1_sclkrx */
+				<4 RK_PA6 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m1_sclktx: i2s1m1-sclktx {
+			rockchip,pins =
+				/* i2s1m1_sclktx */
+				<3 RK_PC7 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m1_sdi0: i2s1m1-sdi0 {
+			rockchip,pins =
+				/* i2s1m1_sdi0 */
+				<3 RK_PD2 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m1_sdi1: i2s1m1-sdi1 {
+			rockchip,pins =
+				/* i2s1m1_sdi1 */
+				<3 RK_PD3 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m1_sdi2: i2s1m1-sdi2 {
+			rockchip,pins =
+				/* i2s1m1_sdi2 */
+				<3 RK_PD4 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m1_sdi3: i2s1m1-sdi3 {
+			rockchip,pins =
+				/* i2s1m1_sdi3 */
+				<3 RK_PD5 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m1_sdo0: i2s1m1-sdo0 {
+			rockchip,pins =
+				/* i2s1m1_sdo0 */
+				<3 RK_PD1 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m1_sdo1: i2s1m1-sdo1 {
+			rockchip,pins =
+				/* i2s1m1_sdo1 */
+				<4 RK_PB0 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m1_sdo2: i2s1m1-sdo2 {
+			rockchip,pins =
+				/* i2s1m1_sdo2 */
+				<4 RK_PB1 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m1_sdo3: i2s1m1-sdo3 {
+			rockchip,pins =
+				/* i2s1m1_sdo3 */
+				<4 RK_PB5 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m2_lrckrx: i2s1m2-lrckrx {
+			rockchip,pins =
+				/* i2s1m2_lrckrx */
+				<3 RK_PC5 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m2_lrcktx: i2s1m2-lrcktx {
+			rockchip,pins =
+				/* i2s1m2_lrcktx */
+				<2 RK_PD2 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m2_mclk: i2s1m2-mclk {
+			rockchip,pins =
+				/* i2s1m2_mclk */
+				<2 RK_PD0 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m2_sclkrx: i2s1m2-sclkrx {
+			rockchip,pins =
+				/* i2s1m2_sclkrx */
+				<3 RK_PC3 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m2_sclktx: i2s1m2-sclktx {
+			rockchip,pins =
+				/* i2s1m2_sclktx */
+				<2 RK_PD1 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m2_sdi0: i2s1m2-sdi0 {
+			rockchip,pins =
+				/* i2s1m2_sdi0 */
+				<2 RK_PD3 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m2_sdi1: i2s1m2-sdi1 {
+			rockchip,pins =
+				/* i2s1m2_sdi1 */
+				<2 RK_PD4 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m2_sdi2: i2s1m2-sdi2 {
+			rockchip,pins =
+				/* i2s1m2_sdi2 */
+				<2 RK_PD5 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m2_sdi3: i2s1m2-sdi3 {
+			rockchip,pins =
+				/* i2s1m2_sdi3 */
+				<2 RK_PD6 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m2_sdo0: i2s1m2-sdo0 {
+			rockchip,pins =
+				/* i2s1m2_sdo0 */
+				<2 RK_PD7 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m2_sdo1: i2s1m2-sdo1 {
+			rockchip,pins =
+				/* i2s1m2_sdo1 */
+				<3 RK_PA0 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m2_sdo2: i2s1m2-sdo2 {
+			rockchip,pins =
+				/* i2s1m2_sdo2 */
+				<3 RK_PC1 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s1m2_sdo3: i2s1m2-sdo3 {
+			rockchip,pins =
+				/* i2s1m2_sdo3 */
+				<3 RK_PC2 5 &pcfg_pull_none>;
+		};
+	};
+
+	i2s2 {
+		/omit-if-no-ref/
+		i2s2m0_lrckrx: i2s2m0-lrckrx {
+			rockchip,pins =
+				/* i2s2m0_lrckrx */
+				<2 RK_PC0 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s2m0_lrcktx: i2s2m0-lrcktx {
+			rockchip,pins =
+				/* i2s2m0_lrcktx */
+				<2 RK_PC3 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s2m0_mclk: i2s2m0-mclk {
+			rockchip,pins =
+				/* i2s2m0_mclk */
+				<2 RK_PC1 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s2m0_sclkrx: i2s2m0-sclkrx {
+			rockchip,pins =
+				/* i2s2m0_sclkrx */
+				<2 RK_PB7 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s2m0_sclktx: i2s2m0-sclktx {
+			rockchip,pins =
+				/* i2s2m0_sclktx */
+				<2 RK_PC2 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s2m0_sdi: i2s2m0-sdi {
+			rockchip,pins =
+				/* i2s2m0_sdi */
+				<2 RK_PC5 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s2m0_sdo: i2s2m0-sdo {
+			rockchip,pins =
+				/* i2s2m0_sdo */
+				<2 RK_PC4 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s2m1_lrckrx: i2s2m1-lrckrx {
+			rockchip,pins =
+				/* i2s2m1_lrckrx */
+				<4 RK_PA5 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s2m1_lrcktx: i2s2m1-lrcktx {
+			rockchip,pins =
+				/* i2s2m1_lrcktx */
+				<4 RK_PA4 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s2m1_mclk: i2s2m1-mclk {
+			rockchip,pins =
+				/* i2s2m1_mclk */
+				<4 RK_PB6 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s2m1_sclkrx: i2s2m1-sclkrx {
+			rockchip,pins =
+				/* i2s2m1_sclkrx */
+				<4 RK_PC1 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s2m1_sclktx: i2s2m1-sclktx {
+			rockchip,pins =
+				/* i2s2m1_sclktx */
+				<4 RK_PB7 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s2m1_sdi: i2s2m1-sdi {
+			rockchip,pins =
+				/* i2s2m1_sdi */
+				<4 RK_PB2 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s2m1_sdo: i2s2m1-sdo {
+			rockchip,pins =
+				/* i2s2m1_sdo */
+				<4 RK_PB3 5 &pcfg_pull_none>;
+		};
+	};
+
+	i2s3 {
+		/omit-if-no-ref/
+		i2s3m0_lrck: i2s3m0-lrck {
+			rockchip,pins =
+				/* i2s3m0_lrck */
+				<3 RK_PA4 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s3m0_mclk: i2s3m0-mclk {
+			rockchip,pins =
+				/* i2s3m0_mclk */
+				<3 RK_PA2 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s3m0_sclk: i2s3m0-sclk {
+			rockchip,pins =
+				/* i2s3m0_sclk */
+				<3 RK_PA3 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s3m0_sdi: i2s3m0-sdi {
+			rockchip,pins =
+				/* i2s3m0_sdi */
+				<3 RK_PA6 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s3m0_sdo: i2s3m0-sdo {
+			rockchip,pins =
+				/* i2s3m0_sdo */
+				<3 RK_PA5 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s3m1_lrck: i2s3m1-lrck {
+			rockchip,pins =
+				/* i2s3m1_lrck */
+				<4 RK_PC4 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s3m1_mclk: i2s3m1-mclk {
+			rockchip,pins =
+				/* i2s3m1_mclk */
+				<4 RK_PC2 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s3m1_sclk: i2s3m1-sclk {
+			rockchip,pins =
+				/* i2s3m1_sclk */
+				<4 RK_PC3 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s3m1_sdi: i2s3m1-sdi {
+			rockchip,pins =
+				/* i2s3m1_sdi */
+				<4 RK_PC6 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		i2s3m1_sdo: i2s3m1-sdo {
+			rockchip,pins =
+				/* i2s3m1_sdo */
+				<4 RK_PC5 5 &pcfg_pull_none>;
+		};
+	};
+
+	isp {
+		/omit-if-no-ref/
+		isp_pins: isp-pins {
+			rockchip,pins =
+				/* isp_flashtrigin */
+				<4 RK_PB4 4 &pcfg_pull_none>,
+				/* isp_flashtrigout */
+				<4 RK_PA6 1 &pcfg_pull_none>,
+				/* isp_prelighttrig */
+				<4 RK_PB1 1 &pcfg_pull_none>;
+		};
+	};
+
+	jtag {
+		/omit-if-no-ref/
+		jtag_pins: jtag-pins {
+			rockchip,pins =
+				/* jtag_tck */
+				<1 RK_PD7 2 &pcfg_pull_none>,
+				/* jtag_tms */
+				<2 RK_PA0 2 &pcfg_pull_none>;
+		};
+	};
+
+	lcdc {
+		/omit-if-no-ref/
+		lcdc_ctl: lcdc-ctl {
+			rockchip,pins =
+				/* lcdc_clk */
+				<3 RK_PA0 1 &pcfg_pull_none>,
+				/* lcdc_d0 */
+				<2 RK_PD0 1 &pcfg_pull_none>,
+				/* lcdc_d1 */
+				<2 RK_PD1 1 &pcfg_pull_none>,
+				/* lcdc_d2 */
+				<2 RK_PD2 1 &pcfg_pull_none>,
+				/* lcdc_d3 */
+				<2 RK_PD3 1 &pcfg_pull_none>,
+				/* lcdc_d4 */
+				<2 RK_PD4 1 &pcfg_pull_none>,
+				/* lcdc_d5 */
+				<2 RK_PD5 1 &pcfg_pull_none>,
+				/* lcdc_d6 */
+				<2 RK_PD6 1 &pcfg_pull_none>,
+				/* lcdc_d7 */
+				<2 RK_PD7 1 &pcfg_pull_none>,
+				/* lcdc_d8 */
+				<3 RK_PA1 1 &pcfg_pull_none>,
+				/* lcdc_d9 */
+				<3 RK_PA2 1 &pcfg_pull_none>,
+				/* lcdc_d10 */
+				<3 RK_PA3 1 &pcfg_pull_none>,
+				/* lcdc_d11 */
+				<3 RK_PA4 1 &pcfg_pull_none>,
+				/* lcdc_d12 */
+				<3 RK_PA5 1 &pcfg_pull_none>,
+				/* lcdc_d13 */
+				<3 RK_PA6 1 &pcfg_pull_none>,
+				/* lcdc_d14 */
+				<3 RK_PA7 1 &pcfg_pull_none>,
+				/* lcdc_d15 */
+				<3 RK_PB0 1 &pcfg_pull_none>,
+				/* lcdc_d16 */
+				<3 RK_PB1 1 &pcfg_pull_none>,
+				/* lcdc_d17 */
+				<3 RK_PB2 1 &pcfg_pull_none>,
+				/* lcdc_d18 */
+				<3 RK_PB3 1 &pcfg_pull_none>,
+				/* lcdc_d19 */
+				<3 RK_PB4 1 &pcfg_pull_none>,
+				/* lcdc_d20 */
+				<3 RK_PB5 1 &pcfg_pull_none>,
+				/* lcdc_d21 */
+				<3 RK_PB6 1 &pcfg_pull_none>,
+				/* lcdc_d22 */
+				<3 RK_PB7 1 &pcfg_pull_none>,
+				/* lcdc_d23 */
+				<3 RK_PC0 1 &pcfg_pull_none>,
+				/* lcdc_den */
+				<3 RK_PC3 1 &pcfg_pull_none>,
+				/* lcdc_hsync */
+				<3 RK_PC1 1 &pcfg_pull_none>,
+				/* lcdc_vsync */
+				<3 RK_PC2 1 &pcfg_pull_none>;
+		};
+	};
+
+	mcu {
+		/omit-if-no-ref/
+		mcu_pins: mcu-pins {
+			rockchip,pins =
+				/* mcu_jtagtck */
+				<0 RK_PB4 4 &pcfg_pull_none>,
+				/* mcu_jtagtdi */
+				<0 RK_PC1 4 &pcfg_pull_none>,
+				/* mcu_jtagtdo */
+				<0 RK_PB3 4 &pcfg_pull_none>,
+				/* mcu_jtagtms */
+				<0 RK_PC2 4 &pcfg_pull_none>,
+				/* mcu_jtagtrstn */
+				<0 RK_PC3 4 &pcfg_pull_none>;
+		};
+	};
+
+	npu {
+		/omit-if-no-ref/
+		npu_pins: npu-pins {
+			rockchip,pins =
+				/* npu_avs */
+				<0 RK_PC1 2 &pcfg_pull_none>;
+		};
+	};
+
+	pcie20 {
+		/omit-if-no-ref/
+		pcie20m0_pins: pcie20m0-pins {
+			rockchip,pins =
+				/* pcie20_clkreqnm0 */
+				<0 RK_PA5 3 &pcfg_pull_none>,
+				/* pcie20_perstnm0 */
+				<0 RK_PB6 3 &pcfg_pull_none>,
+				/* pcie20_wakenm0 */
+				<0 RK_PB5 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pcie20m1_pins: pcie20m1-pins {
+			rockchip,pins =
+				/* pcie20_clkreqnm1 */
+				<2 RK_PD0 4 &pcfg_pull_none>,
+				/* pcie20_perstnm1 */
+				<3 RK_PC1 4 &pcfg_pull_none>,
+				/* pcie20_wakenm1 */
+				<2 RK_PD1 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pcie20m2_pins: pcie20m2-pins {
+			rockchip,pins =
+				/* pcie20_clkreqnm2 */
+				<1 RK_PB0 4 &pcfg_pull_none>,
+				/* pcie20_perstnm2 */
+				<1 RK_PB2 4 &pcfg_pull_none>,
+				/* pcie20_wakenm2 */
+				<1 RK_PB1 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pcie20_buttonrstn: pcie20-buttonrstn {
+			rockchip,pins =
+				/* pcie20_buttonrstn */
+				<0 RK_PB4 3 &pcfg_pull_none>;
+		};
+	};
+
+	pcie30x1 {
+		/omit-if-no-ref/
+		pcie30x1m0_pins: pcie30x1m0-pins {
+			rockchip,pins =
+				/* pcie30x1_clkreqnm0 */
+				<0 RK_PA4 3 &pcfg_pull_none>,
+				/* pcie30x1_perstnm0 */
+				<0 RK_PC3 3 &pcfg_pull_none>,
+				/* pcie30x1_wakenm0 */
+				<0 RK_PC2 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pcie30x1m1_pins: pcie30x1m1-pins {
+			rockchip,pins =
+				/* pcie30x1_clkreqnm1 */
+				<2 RK_PD2 4 &pcfg_pull_none>,
+				/* pcie30x1_perstnm1 */
+				<3 RK_PA1 4 &pcfg_pull_none>,
+				/* pcie30x1_wakenm1 */
+				<2 RK_PD3 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pcie30x1m2_pins: pcie30x1m2-pins {
+			rockchip,pins =
+				/* pcie30x1_clkreqnm2 */
+				<1 RK_PA5 4 &pcfg_pull_none>,
+				/* pcie30x1_perstnm2 */
+				<1 RK_PA2 4 &pcfg_pull_none>,
+				/* pcie30x1_wakenm2 */
+				<1 RK_PA3 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pcie30x1_buttonrstn: pcie30x1-buttonrstn {
+			rockchip,pins =
+				/* pcie30x1_buttonrstn */
+				<0 RK_PB3 3 &pcfg_pull_none>;
+		};
+	};
+
+	pcie30x2 {
+		/omit-if-no-ref/
+		pcie30x2m0_pins: pcie30x2m0-pins {
+			rockchip,pins =
+				/* pcie30x2_clkreqnm0 */
+				<0 RK_PA6 2 &pcfg_pull_none>,
+				/* pcie30x2_perstnm0 */
+				<0 RK_PC6 3 &pcfg_pull_none>,
+				/* pcie30x2_wakenm0 */
+				<0 RK_PC5 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pcie30x2m1_pins: pcie30x2m1-pins {
+			rockchip,pins =
+				/* pcie30x2_clkreqnm1 */
+				<2 RK_PD4 4 &pcfg_pull_none>,
+				/* pcie30x2_perstnm1 */
+				<2 RK_PD6 4 &pcfg_pull_none>,
+				/* pcie30x2_wakenm1 */
+				<2 RK_PD5 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pcie30x2m2_pins: pcie30x2m2-pins {
+			rockchip,pins =
+				/* pcie30x2_clkreqnm2 */
+				<4 RK_PC2 4 &pcfg_pull_none>,
+				/* pcie30x2_perstnm2 */
+				<4 RK_PC4 4 &pcfg_pull_none>,
+				/* pcie30x2_wakenm2 */
+				<4 RK_PC3 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pcie30x2_buttonrstn: pcie30x2-buttonrstn {
+			rockchip,pins =
+				/* pcie30x2_buttonrstn */
+				<0 RK_PB0 3 &pcfg_pull_none>;
+		};
+	};
+
+	pdm {
+		/omit-if-no-ref/
+		pdmm0_clk: pdmm0-clk {
+			rockchip,pins =
+				/* pdm_clk0m0 */
+				<1 RK_PA6 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm0_clk1: pdmm0-clk1 {
+			rockchip,pins =
+				/* pdmm0_clk1 */
+				<1 RK_PA4 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm0_sdi0: pdmm0-sdi0 {
+			rockchip,pins =
+				/* pdmm0_sdi0 */
+				<1 RK_PB3 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm0_sdi1: pdmm0-sdi1 {
+			rockchip,pins =
+				/* pdmm0_sdi1 */
+				<1 RK_PB2 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm0_sdi2: pdmm0-sdi2 {
+			rockchip,pins =
+				/* pdmm0_sdi2 */
+				<1 RK_PB1 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm0_sdi3: pdmm0-sdi3 {
+			rockchip,pins =
+				/* pdmm0_sdi3 */
+				<1 RK_PB0 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm1_clk: pdmm1-clk {
+			rockchip,pins =
+				/* pdm_clk0m1 */
+				<3 RK_PD6 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm1_clk1: pdmm1-clk1 {
+			rockchip,pins =
+				/* pdmm1_clk1 */
+				<4 RK_PA0 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm1_sdi0: pdmm1-sdi0 {
+			rockchip,pins =
+				/* pdmm1_sdi0 */
+				<3 RK_PD7 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm1_sdi1: pdmm1-sdi1 {
+			rockchip,pins =
+				/* pdmm1_sdi1 */
+				<4 RK_PA1 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm1_sdi2: pdmm1-sdi2 {
+			rockchip,pins =
+				/* pdmm1_sdi2 */
+				<4 RK_PA2 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm1_sdi3: pdmm1-sdi3 {
+			rockchip,pins =
+				/* pdmm1_sdi3 */
+				<4 RK_PA3 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm2_clk1: pdmm2-clk1 {
+			rockchip,pins =
+				/* pdmm2_clk1 */
+				<3 RK_PC4 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm2_sdi0: pdmm2-sdi0 {
+			rockchip,pins =
+				/* pdmm2_sdi0 */
+				<3 RK_PB3 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm2_sdi1: pdmm2-sdi1 {
+			rockchip,pins =
+				/* pdmm2_sdi1 */
+				<3 RK_PB4 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm2_sdi2: pdmm2-sdi2 {
+			rockchip,pins =
+				/* pdmm2_sdi2 */
+				<3 RK_PB7 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pdmm2_sdi3: pdmm2-sdi3 {
+			rockchip,pins =
+				/* pdmm2_sdi3 */
+				<3 RK_PC0 5 &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		/omit-if-no-ref/
+		pmic_pins: pmic-pins {
+			rockchip,pins =
+				/* pmic_sleep */
+				<0 RK_PA2 1 &pcfg_pull_none>;
+		};
+	};
+
+	pmu {
+		/omit-if-no-ref/
+		pmu_pins: pmu-pins {
+			rockchip,pins =
+				/* pmu_debug0 */
+				<0 RK_PA5 4 &pcfg_pull_none>,
+				/* pmu_debug1 */
+				<0 RK_PA6 3 &pcfg_pull_none>,
+				/* pmu_debug2 */
+				<0 RK_PC4 4 &pcfg_pull_none>,
+				/* pmu_debug3 */
+				<0 RK_PC5 4 &pcfg_pull_none>,
+				/* pmu_debug4 */
+				<0 RK_PC6 4 &pcfg_pull_none>,
+				/* pmu_debug5 */
+				<0 RK_PC7 4 &pcfg_pull_none>;
+		};
+	};
+
+	pwm0 {
+		/omit-if-no-ref/
+		pwm0m0_pins: pwm0m0-pins {
+			rockchip,pins =
+				/* pwm0_m0 */
+				<0 RK_PB7 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm0m1_pins: pwm0m1-pins {
+			rockchip,pins =
+				/* pwm0_m1 */
+				<0 RK_PC7 2 &pcfg_pull_none>;
+		};
+	};
+
+	pwm1 {
+		/omit-if-no-ref/
+		pwm1m0_pins: pwm1m0-pins {
+			rockchip,pins =
+				/* pwm1_m0 */
+				<0 RK_PC0 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm1m1_pins: pwm1m1-pins {
+			rockchip,pins =
+				/* pwm1_m1 */
+				<0 RK_PB5 4 &pcfg_pull_none>;
+		};
+	};
+
+	pwm2 {
+		/omit-if-no-ref/
+		pwm2m0_pins: pwm2m0-pins {
+			rockchip,pins =
+				/* pwm2_m0 */
+				<0 RK_PC1 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm2m1_pins: pwm2m1-pins {
+			rockchip,pins =
+				/* pwm2_m1 */
+				<0 RK_PB6 4 &pcfg_pull_none>;
+		};
+	};
+
+	pwm3 {
+		/omit-if-no-ref/
+		pwm3_pins: pwm3-pins {
+			rockchip,pins =
+				/* pwm3_ir */
+				<0 RK_PC2 1 &pcfg_pull_none>;
+		};
+	};
+
+	pwm4 {
+		/omit-if-no-ref/
+		pwm4_pins: pwm4-pins {
+			rockchip,pins =
+				/* pwm4 */
+				<0 RK_PC3 1 &pcfg_pull_none>;
+		};
+	};
+
+	pwm5 {
+		/omit-if-no-ref/
+		pwm5_pins: pwm5-pins {
+			rockchip,pins =
+				/* pwm5 */
+				<0 RK_PC4 1 &pcfg_pull_none>;
+		};
+	};
+
+	pwm6 {
+		/omit-if-no-ref/
+		pwm6_pins: pwm6-pins {
+			rockchip,pins =
+				/* pwm6 */
+				<0 RK_PC5 1 &pcfg_pull_none>;
+		};
+	};
+
+	pwm7 {
+		/omit-if-no-ref/
+		pwm7_pins: pwm7-pins {
+			rockchip,pins =
+				/* pwm7_ir */
+				<0 RK_PC6 1 &pcfg_pull_none>;
+		};
+	};
+
+	pwm8 {
+		/omit-if-no-ref/
+		pwm8m0_pins: pwm8m0-pins {
+			rockchip,pins =
+				/* pwm8_m0 */
+				<3 RK_PB1 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm8m1_pins: pwm8m1-pins {
+			rockchip,pins =
+				/* pwm8_m1 */
+				<1 RK_PD5 4 &pcfg_pull_none>;
+		};
+	};
+
+	pwm9 {
+		/omit-if-no-ref/
+		pwm9m0_pins: pwm9m0-pins {
+			rockchip,pins =
+				/* pwm9_m0 */
+				<3 RK_PB2 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm9m1_pins: pwm9m1-pins {
+			rockchip,pins =
+				/* pwm9_m1 */
+				<1 RK_PD6 4 &pcfg_pull_none>;
+		};
+	};
+
+	pwm10 {
+		/omit-if-no-ref/
+		pwm10m0_pins: pwm10m0-pins {
+			rockchip,pins =
+				/* pwm10_m0 */
+				<3 RK_PB5 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm10m1_pins: pwm10m1-pins {
+			rockchip,pins =
+				/* pwm10_m1 */
+				<2 RK_PA1 2 &pcfg_pull_none>;
+		};
+	};
+
+	pwm11 {
+		/omit-if-no-ref/
+		pwm11m0_pins: pwm11m0-pins {
+			rockchip,pins =
+				/* pwm11_irm0 */
+				<3 RK_PB6 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm11m1_pins: pwm11m1-pins {
+			rockchip,pins =
+				/* pwm11_irm1 */
+				<4 RK_PC0 3 &pcfg_pull_none>;
+		};
+	};
+
+	pwm12 {
+		/omit-if-no-ref/
+		pwm12m0_pins: pwm12m0-pins {
+			rockchip,pins =
+				/* pwm12_m0 */
+				<3 RK_PB7 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm12m1_pins: pwm12m1-pins {
+			rockchip,pins =
+				/* pwm12_m1 */
+				<4 RK_PC5 1 &pcfg_pull_none>;
+		};
+	};
+
+	pwm13 {
+		/omit-if-no-ref/
+		pwm13m0_pins: pwm13m0-pins {
+			rockchip,pins =
+				/* pwm13_m0 */
+				<3 RK_PC0 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm13m1_pins: pwm13m1-pins {
+			rockchip,pins =
+				/* pwm13_m1 */
+				<4 RK_PC6 1 &pcfg_pull_none>;
+		};
+	};
+
+	pwm14 {
+		/omit-if-no-ref/
+		pwm14m0_pins: pwm14m0-pins {
+			rockchip,pins =
+				/* pwm14_m0 */
+				<3 RK_PC4 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm14m1_pins: pwm14m1-pins {
+			rockchip,pins =
+				/* pwm14_m1 */
+				<4 RK_PC2 1 &pcfg_pull_none>;
+		};
+	};
+
+	pwm15 {
+		/omit-if-no-ref/
+		pwm15m0_pins: pwm15m0-pins {
+			rockchip,pins =
+				/* pwm15_irm0 */
+				<3 RK_PC5 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		pwm15m1_pins: pwm15m1-pins {
+			rockchip,pins =
+				/* pwm15_irm1 */
+				<4 RK_PC3 1 &pcfg_pull_none>;
+		};
+	};
+
+	refclk {
+		/omit-if-no-ref/
+		refclk_pins: refclk-pins {
+			rockchip,pins =
+				/* refclk_ou */
+				<0 RK_PA0 1 &pcfg_pull_none>;
+		};
+	};
+
+	sata {
+		/omit-if-no-ref/
+		sata_pins: sata-pins {
+			rockchip,pins =
+				/* sata_cpdet */
+				<0 RK_PA4 2 &pcfg_pull_none>,
+				/* sata_cppod */
+				<0 RK_PA6 1 &pcfg_pull_none>,
+				/* sata_mpswitch */
+				<0 RK_PA5 2 &pcfg_pull_none>;
+		};
+	};
+
+	sata0 {
+		/omit-if-no-ref/
+		sata0_pins: sata0-pins {
+			rockchip,pins =
+				/* sata0_actled */
+				<4 RK_PC6 3 &pcfg_pull_none>;
+		};
+	};
+
+	sata1 {
+		/omit-if-no-ref/
+		sata1_pins: sata1-pins {
+			rockchip,pins =
+				/* sata1_actled */
+				<4 RK_PC5 3 &pcfg_pull_none>;
+		};
+	};
+
+	sata2 {
+		/omit-if-no-ref/
+		sata2_pins: sata2-pins {
+			rockchip,pins =
+				/* sata2_actled */
+				<4 RK_PC4 3 &pcfg_pull_none>;
+		};
+	};
+
+	scr {
+		/omit-if-no-ref/
+		scr_pins: scr-pins {
+			rockchip,pins =
+				/* scr_clk */
+				<1 RK_PA2 3 &pcfg_pull_none>,
+				/* scr_det */
+				<1 RK_PA7 3 &pcfg_pull_up>,
+				/* scr_io */
+				<1 RK_PA3 3 &pcfg_pull_up>,
+				/* scr_rst */
+				<1 RK_PA5 3 &pcfg_pull_none>;
+		};
+	};
+
+	sdmmc0 {
+		/omit-if-no-ref/
+		sdmmc0_bus4: sdmmc0-bus4 {
+			rockchip,pins =
+				/* sdmmc0_d0 */
+				<1 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc0_d1 */
+				<1 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc0_d2 */
+				<1 RK_PD7 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc0_d3 */
+				<2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc0_clk: sdmmc0-clk {
+			rockchip,pins =
+				/* sdmmc0_clk */
+				<2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc0_cmd: sdmmc0-cmd {
+			rockchip,pins =
+				/* sdmmc0_cmd */
+				<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc0_det: sdmmc0-det {
+			rockchip,pins =
+				/* sdmmc0_det */
+				<0 RK_PA4 1 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc0_pwren: sdmmc0-pwren {
+			rockchip,pins =
+				/* sdmmc0_pwren */
+				<0 RK_PA5 1 &pcfg_pull_none>;
+		};
+	};
+
+	sdmmc1 {
+		/omit-if-no-ref/
+		sdmmc1_bus4: sdmmc1-bus4 {
+			rockchip,pins =
+				/* sdmmc1_d0 */
+				<2 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc1_d1 */
+				<2 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc1_d2 */
+				<2 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc1_d3 */
+				<2 RK_PA6 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc1_clk: sdmmc1-clk {
+			rockchip,pins =
+				/* sdmmc1_clk */
+				<2 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc1_cmd: sdmmc1-cmd {
+			rockchip,pins =
+				/* sdmmc1_cmd */
+				<2 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc1_det: sdmmc1-det {
+			rockchip,pins =
+				/* sdmmc1_det */
+				<2 RK_PB2 1 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc1_pwren: sdmmc1-pwren {
+			rockchip,pins =
+				/* sdmmc1_pwren */
+				<2 RK_PB1 1 &pcfg_pull_none>;
+		};
+	};
+
+	sdmmc2 {
+		/omit-if-no-ref/
+		sdmmc2m0_bus4: sdmmc2m0-bus4 {
+			rockchip,pins =
+				/* sdmmc2_d0m0 */
+				<3 RK_PC6 3 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc2_d1m0 */
+				<3 RK_PC7 3 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc2_d2m0 */
+				<3 RK_PD0 3 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc2_d3m0 */
+				<3 RK_PD1 3 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc2m0_clk: sdmmc2m0-clk {
+			rockchip,pins =
+				/* sdmmc2_clkm0 */
+				<3 RK_PD3 3 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc2m0_cmd: sdmmc2m0-cmd {
+			rockchip,pins =
+				/* sdmmc2_cmdm0 */
+				<3 RK_PD2 3 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc2m0_det: sdmmc2m0-det {
+			rockchip,pins =
+				/* sdmmc2_detm0 */
+				<3 RK_PD4 3 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc2m0_pwren: sdmmc2m0-pwren {
+			rockchip,pins =
+				/* sdmmc2m0_pwren */
+				<3 RK_PD5 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc2m1_bus4: sdmmc2m1-bus4 {
+			rockchip,pins =
+				/* sdmmc2_d0m1 */
+				<3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc2_d1m1 */
+				<3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc2_d2m1 */
+				<3 RK_PA3 5 &pcfg_pull_up_drv_level_2>,
+				/* sdmmc2_d3m1 */
+				<3 RK_PA4 5 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc2m1_clk: sdmmc2m1-clk {
+			rockchip,pins =
+				/* sdmmc2_clkm1 */
+				<3 RK_PA6 5 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc2m1_cmd: sdmmc2m1-cmd {
+			rockchip,pins =
+				/* sdmmc2_cmdm1 */
+				<3 RK_PA5 5 &pcfg_pull_up_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc2m1_det: sdmmc2m1-det {
+			rockchip,pins =
+				/* sdmmc2_detm1 */
+				<3 RK_PA7 4 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		sdmmc2m1_pwren: sdmmc2m1-pwren {
+			rockchip,pins =
+				/* sdmmc2m1_pwren */
+				<3 RK_PB0 4 &pcfg_pull_none>;
+		};
+	};
+
+	spdif {
+		/omit-if-no-ref/
+		spdifm0_tx: spdifm0-tx {
+			rockchip,pins =
+				/* spdifm0_tx */
+				<1 RK_PA4 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spdifm1_tx: spdifm1-tx {
+			rockchip,pins =
+				/* spdifm1_tx */
+				<3 RK_PC5 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spdifm2_tx: spdifm2-tx {
+			rockchip,pins =
+				/* spdifm2_tx */
+				<4 RK_PC4 2 &pcfg_pull_none>;
+		};
+	};
+
+	spi0 {
+		/omit-if-no-ref/
+		spi0m0_pins: spi0m0-pins {
+			rockchip,pins =
+				/* spi0_clkm0 */
+				<0 RK_PB5 2 &pcfg_pull_none>,
+				/* spi0_misom0 */
+				<0 RK_PC5 2 &pcfg_pull_none>,
+				/* spi0_mosim0 */
+				<0 RK_PB6 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi0m0_cs0: spi0m0-cs0 {
+			rockchip,pins =
+				/* spi0_cs0m0 */
+				<0 RK_PC6 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi0m0_cs1: spi0m0-cs1 {
+			rockchip,pins =
+				/* spi0_cs1m0 */
+				<0 RK_PC4 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi0m1_pins: spi0m1-pins {
+			rockchip,pins =
+				/* spi0_clkm1 */
+				<2 RK_PD3 3 &pcfg_pull_none>,
+				/* spi0_misom1 */
+				<2 RK_PD0 3 &pcfg_pull_none>,
+				/* spi0_mosim1 */
+				<2 RK_PD1 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi0m1_cs0: spi0m1-cs0 {
+			rockchip,pins =
+				/* spi0_cs0m1 */
+				<2 RK_PD2 3 &pcfg_pull_none>;
+		};
+	};
+
+	spi1 {
+		/omit-if-no-ref/
+		spi1m0_pins: spi1m0-pins {
+			rockchip,pins =
+				/* spi1_clkm0 */
+				<2 RK_PB5 3 &pcfg_pull_none>,
+				/* spi1_misom0 */
+				<2 RK_PB6 3 &pcfg_pull_none>,
+				/* spi1_mosim0 */
+				<2 RK_PB7 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi1m0_cs0: spi1m0-cs0 {
+			rockchip,pins =
+				/* spi1_cs0m0 */
+				<2 RK_PC0 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi1m0_cs1: spi1m0-cs1 {
+			rockchip,pins =
+				/* spi1_cs1m0 */
+				<2 RK_PC6 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi1m1_pins: spi1m1-pins {
+			rockchip,pins =
+				/* spi1_clkm1 */
+				<3 RK_PC3 3 &pcfg_pull_none>,
+				/* spi1_misom1 */
+				<3 RK_PC2 3 &pcfg_pull_none>,
+				/* spi1_mosim1 */
+				<3 RK_PC1 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi1m1_cs0: spi1m1-cs0 {
+			rockchip,pins =
+				/* spi1_cs0m1 */
+				<3 RK_PA1 3 &pcfg_pull_none>;
+		};
+	};
+
+	spi2 {
+		/omit-if-no-ref/
+		spi2m0_pins: spi2m0-pins {
+			rockchip,pins =
+				/* spi2_clkm0 */
+				<2 RK_PC1 4 &pcfg_pull_none>,
+				/* spi2_misom0 */
+				<2 RK_PC2 4 &pcfg_pull_none>,
+				/* spi2_mosim0 */
+				<2 RK_PC3 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi2m0_cs0: spi2m0-cs0 {
+			rockchip,pins =
+				/* spi2_cs0m0 */
+				<2 RK_PC4 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi2m0_cs1: spi2m0-cs1 {
+			rockchip,pins =
+				/* spi2_cs1m0 */
+				<2 RK_PC5 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi2m1_pins: spi2m1-pins {
+			rockchip,pins =
+				/* spi2_clkm1 */
+				<3 RK_PA0 3 &pcfg_pull_none>,
+				/* spi2_misom1 */
+				<2 RK_PD7 3 &pcfg_pull_none>,
+				/* spi2_mosim1 */
+				<2 RK_PD6 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi2m1_cs0: spi2m1-cs0 {
+			rockchip,pins =
+				/* spi2_cs0m1 */
+				<2 RK_PD5 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi2m1_cs1: spi2m1-cs1 {
+			rockchip,pins =
+				/* spi2_cs1m1 */
+				<2 RK_PD4 3 &pcfg_pull_none>;
+		};
+	};
+
+	spi3 {
+		/omit-if-no-ref/
+		spi3m0_pins: spi3m0-pins {
+			rockchip,pins =
+				/* spi3_clkm0 */
+				<4 RK_PB3 4 &pcfg_pull_none>,
+				/* spi3_misom0 */
+				<4 RK_PB0 4 &pcfg_pull_none>,
+				/* spi3_mosim0 */
+				<4 RK_PB2 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi3m0_cs0: spi3m0-cs0 {
+			rockchip,pins =
+				/* spi3_cs0m0 */
+				<4 RK_PA6 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi3m0_cs1: spi3m0-cs1 {
+			rockchip,pins =
+				/* spi3_cs1m0 */
+				<4 RK_PA7 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi3m1_pins: spi3m1-pins {
+			rockchip,pins =
+				/* spi3_clkm1 */
+				<4 RK_PC2 2 &pcfg_pull_none>,
+				/* spi3_misom1 */
+				<4 RK_PC5 2 &pcfg_pull_none>,
+				/* spi3_mosim1 */
+				<4 RK_PC3 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi3m1_cs0: spi3m1-cs0 {
+			rockchip,pins =
+				/* spi3_cs0m1 */
+				<4 RK_PC6 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		spi3m1_cs1: spi3m1-cs1 {
+			rockchip,pins =
+				/* spi3_cs1m1 */
+				<4 RK_PD1 2 &pcfg_pull_none>;
+		};
+	};
+
+	tsadc {
+		/omit-if-no-ref/
+		tsadcm0_shut: tsadcm0-shut {
+			rockchip,pins =
+				/* tsadcm0_shut */
+				<0 RK_PA1 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		tsadcm1_shut: tsadcm1-shut {
+			rockchip,pins =
+				/* tsadcm1_shut */
+				<0 RK_PA2 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		tsadc_shutorg: tsadc-shutorg {
+			rockchip,pins =
+				/* tsadc_shutorg */
+				<0 RK_PA1 2 &pcfg_pull_none>;
+		};
+	};
+
+	uart0 {
+		/omit-if-no-ref/
+		uart0_xfer: uart0-xfer {
+			rockchip,pins =
+				/* uart0_rx */
+				<0 RK_PC0 3 &pcfg_pull_up>,
+				/* uart0_tx */
+				<0 RK_PC1 3 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart0_ctsn: uart0-ctsn {
+			rockchip,pins =
+				/* uart0_ctsn */
+				<0 RK_PC7 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart0_rtsn: uart0-rtsn {
+			rockchip,pins =
+				/* uart0_rtsn */
+				<0 RK_PC4 3 &pcfg_pull_none>;
+		};
+	};
+
+	uart1 {
+		/omit-if-no-ref/
+		uart1m0_xfer: uart1m0-xfer {
+			rockchip,pins =
+				/* uart1_rxm0 */
+				<2 RK_PB3 2 &pcfg_pull_up>,
+				/* uart1_txm0 */
+				<2 RK_PB4 2 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart1m0_ctsn: uart1m0-ctsn {
+			rockchip,pins =
+				/* uart1m0_ctsn */
+				<2 RK_PB6 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart1m0_rtsn: uart1m0-rtsn {
+			rockchip,pins =
+				/* uart1m0_rtsn */
+				<2 RK_PB5 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart1m1_xfer: uart1m1-xfer {
+			rockchip,pins =
+				/* uart1_rxm1 */
+				<3 RK_PD7 4 &pcfg_pull_up>,
+				/* uart1_txm1 */
+				<3 RK_PD6 4 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart1m1_ctsn: uart1m1-ctsn {
+			rockchip,pins =
+				/* uart1m1_ctsn */
+				<4 RK_PC1 4 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart1m1_rtsn: uart1m1-rtsn {
+			rockchip,pins =
+				/* uart1m1_rtsn */
+				<4 RK_PB6 4 &pcfg_pull_none>;
+		};
+	};
+
+	uart2 {
+		/omit-if-no-ref/
+		uart2m0_xfer: uart2m0-xfer {
+			rockchip,pins =
+				/* uart2_rxm0 */
+				<0 RK_PD0 1 &pcfg_pull_up>,
+				/* uart2_txm0 */
+				<0 RK_PD1 1 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart2m1_xfer: uart2m1-xfer {
+			rockchip,pins =
+				/* uart2_rxm1 */
+				<1 RK_PD6 2 &pcfg_pull_up>,
+				/* uart2_txm1 */
+				<1 RK_PD5 2 &pcfg_pull_up>;
+		};
+	};
+
+	uart3 {
+		/omit-if-no-ref/
+		uart3m0_xfer: uart3m0-xfer {
+			rockchip,pins =
+				/* uart3_rxm0 */
+				<1 RK_PA0 2 &pcfg_pull_up>,
+				/* uart3_txm0 */
+				<1 RK_PA1 2 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart3m0_ctsn: uart3m0-ctsn {
+			rockchip,pins =
+				/* uart3m0_ctsn */
+				<1 RK_PA3 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart3m0_rtsn: uart3m0-rtsn {
+			rockchip,pins =
+				/* uart3m0_rtsn */
+				<1 RK_PA2 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart3m1_xfer: uart3m1-xfer {
+			rockchip,pins =
+				/* uart3_rxm1 */
+				<3 RK_PC0 4 &pcfg_pull_up>,
+				/* uart3_txm1 */
+				<3 RK_PB7 4 &pcfg_pull_up>;
+		};
+	};
+
+	uart4 {
+		/omit-if-no-ref/
+		uart4m0_xfer: uart4m0-xfer {
+			rockchip,pins =
+				/* uart4_rxm0 */
+				<1 RK_PA4 2 &pcfg_pull_up>,
+				/* uart4_txm0 */
+				<1 RK_PA6 2 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart4m0_ctsn: uart4m0-ctsn {
+			rockchip,pins =
+				/* uart4m0_ctsn */
+				<1 RK_PA7 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart4m0_rtsn: uart4m0-rtsn {
+			rockchip,pins =
+				/* uart4m0_rtsn */
+				<1 RK_PA5 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart4m1_xfer: uart4m1-xfer {
+			rockchip,pins =
+				/* uart4_rxm1 */
+				<3 RK_PB1 4 &pcfg_pull_up>,
+				/* uart4_txm1 */
+				<3 RK_PB2 4 &pcfg_pull_up>;
+		};
+	};
+
+	uart5 {
+		/omit-if-no-ref/
+		uart5m0_xfer: uart5m0-xfer {
+			rockchip,pins =
+				/* uart5_rxm0 */
+				<2 RK_PA1 3 &pcfg_pull_up>,
+				/* uart5_txm0 */
+				<2 RK_PA2 3 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart5m0_ctsn: uart5m0-ctsn {
+			rockchip,pins =
+				/* uart5m0_ctsn */
+				<1 RK_PD7 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart5m0_rtsn: uart5m0-rtsn {
+			rockchip,pins =
+				/* uart5m0_rtsn */
+				<2 RK_PA0 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart5m1_xfer: uart5m1-xfer {
+			rockchip,pins =
+				/* uart5_rxm1 */
+				<3 RK_PC3 4 &pcfg_pull_up>,
+				/* uart5_txm1 */
+				<3 RK_PC2 4 &pcfg_pull_up>;
+		};
+	};
+
+	uart6 {
+		/omit-if-no-ref/
+		uart6m0_xfer: uart6m0-xfer {
+			rockchip,pins =
+				/* uart6_rxm0 */
+				<2 RK_PA3 3 &pcfg_pull_up>,
+				/* uart6_txm0 */
+				<2 RK_PA4 3 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart6m0_ctsn: uart6m0-ctsn {
+			rockchip,pins =
+				/* uart6m0_ctsn */
+				<2 RK_PC0 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart6m0_rtsn: uart6m0-rtsn {
+			rockchip,pins =
+				/* uart6m0_rtsn */
+				<2 RK_PB7 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart6m1_xfer: uart6m1-xfer {
+			rockchip,pins =
+				/* uart6_rxm1 */
+				<1 RK_PD6 3 &pcfg_pull_up>,
+				/* uart6_txm1 */
+				<1 RK_PD5 3 &pcfg_pull_up>;
+		};
+	};
+
+	uart7 {
+		/omit-if-no-ref/
+		uart7m0_xfer: uart7m0-xfer {
+			rockchip,pins =
+				/* uart7_rxm0 */
+				<2 RK_PA5 3 &pcfg_pull_up>,
+				/* uart7_txm0 */
+				<2 RK_PA6 3 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart7m0_ctsn: uart7m0-ctsn {
+			rockchip,pins =
+				/* uart7m0_ctsn */
+				<2 RK_PC2 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart7m0_rtsn: uart7m0-rtsn {
+			rockchip,pins =
+				/* uart7m0_rtsn */
+				<2 RK_PC1 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart7m1_xfer: uart7m1-xfer {
+			rockchip,pins =
+				/* uart7_rxm1 */
+				<3 RK_PC5 4 &pcfg_pull_up>,
+				/* uart7_txm1 */
+				<3 RK_PC4 4 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart7m2_xfer: uart7m2-xfer {
+			rockchip,pins =
+				/* uart7_rxm2 */
+				<4 RK_PA3 4 &pcfg_pull_up>,
+				/* uart7_txm2 */
+				<4 RK_PA2 4 &pcfg_pull_up>;
+		};
+	};
+
+	uart8 {
+		/omit-if-no-ref/
+		uart8m0_xfer: uart8m0-xfer {
+			rockchip,pins =
+				/* uart8_rxm0 */
+				<2 RK_PC6 2 &pcfg_pull_up>,
+				/* uart8_txm0 */
+				<2 RK_PC5 3 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart8m0_ctsn: uart8m0-ctsn {
+			rockchip,pins =
+				/* uart8m0_ctsn */
+				<2 RK_PB2 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart8m0_rtsn: uart8m0-rtsn {
+			rockchip,pins =
+				/* uart8m0_rtsn */
+				<2 RK_PB1 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart8m1_xfer: uart8m1-xfer {
+			rockchip,pins =
+				/* uart8_rxm1 */
+				<3 RK_PA0 4 &pcfg_pull_up>,
+				/* uart8_txm1 */
+				<2 RK_PD7 4 &pcfg_pull_up>;
+		};
+	};
+
+	uart9 {
+		/omit-if-no-ref/
+		uart9m0_xfer: uart9m0-xfer {
+			rockchip,pins =
+				/* uart9_rxm0 */
+				<2 RK_PA7 3 &pcfg_pull_up>,
+				/* uart9_txm0 */
+				<2 RK_PB0 3 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart9m0_ctsn: uart9m0-ctsn {
+			rockchip,pins =
+				/* uart9m0_ctsn */
+				<2 RK_PC4 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart9m0_rtsn: uart9m0-rtsn {
+			rockchip,pins =
+				/* uart9m0_rtsn */
+				<2 RK_PC3 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		uart9m1_xfer: uart9m1-xfer {
+			rockchip,pins =
+				/* uart9_rxm1 */
+				<4 RK_PC6 4 &pcfg_pull_up>,
+				/* uart9_txm1 */
+				<4 RK_PC5 4 &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		uart9m2_xfer: uart9m2-xfer {
+			rockchip,pins =
+				/* uart9_rxm2 */
+				<4 RK_PA5 4 &pcfg_pull_up>,
+				/* uart9_txm2 */
+				<4 RK_PA4 4 &pcfg_pull_up>;
+		};
+	};
+
+	vop {
+		/omit-if-no-ref/
+		vopm0_pins: vopm0-pins {
+			rockchip,pins =
+				/* vop_pwmm0 */
+				<0 RK_PC3 2 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		vopm1_pins: vopm1-pins {
+			rockchip,pins =
+				/* vop_pwmm1 */
+				<3 RK_PC4 2 &pcfg_pull_none>;
+		};
+	};
+};
+
+/*
+ * This part is edited handly.
+ */
+&pinctrl {
+	spi0-hs {
+		/omit-if-no-ref/
+		spi0m0_pins_hs: spi0m0-pins {
+			rockchip,pins =
+				/* spi0_clkm0 */
+				<0 RK_PB5 2 &pcfg_pull_up_drv_level_1>,
+				/* spi0_misom0 */
+				<0 RK_PC5 2 &pcfg_pull_up_drv_level_1>,
+				/* spi0_mosim0 */
+				<0 RK_PB6 2 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi0m0_cs0_hs: spi0m0-cs0 {
+			rockchip,pins =
+				/* spi0_cs0m0 */
+				<0 RK_PC6 2 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi0m0_cs1_hs: spi0m0-cs1 {
+			rockchip,pins =
+				/* spi0_cs1m0 */
+				<0 RK_PC4 2 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi0m1_pins_hs: spi0m1-pins {
+			rockchip,pins =
+				/* spi0_clkm1 */
+				<2 RK_PD3 3 &pcfg_pull_up_drv_level_1>,
+				/* spi0_misom1 */
+				<2 RK_PD0 3 &pcfg_pull_up_drv_level_1>,
+				/* spi0_mosim1 */
+				<2 RK_PD1 3 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi0m1_cs0_hs: spi0m1-cs0 {
+			rockchip,pins =
+				/* spi0_cs0m1 */
+				<2 RK_PD2 3 &pcfg_pull_up_drv_level_1>;
+		};
+	};
+
+	spi1-hs {
+		/omit-if-no-ref/
+		spi1m0_pins_hs: spi1m0-pins {
+			rockchip,pins =
+				/* spi1_clkm0 */
+				<2 RK_PB5 3 &pcfg_pull_up_drv_level_1>,
+				/* spi1_misom0 */
+				<2 RK_PB6 3 &pcfg_pull_up_drv_level_1>,
+				/* spi1_mosim0 */
+				<2 RK_PB7 4 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi1m0_cs0_hs: spi1m0-cs0 {
+			rockchip,pins =
+				/* spi1_cs0m0 */
+				<2 RK_PC0 4 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi1m0_cs1_hs: spi1m0-cs1 {
+			rockchip,pins =
+				/* spi1_cs1m0 */
+				<2 RK_PC6 3 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi1m1_pins_hs: spi1m1-pins {
+			rockchip,pins =
+				/* spi1_clkm1 */
+				<3 RK_PC3 3 &pcfg_pull_up_drv_level_1>,
+				/* spi1_misom1 */
+				<3 RK_PC2 3 &pcfg_pull_up_drv_level_1>,
+				/* spi1_mosim1 */
+				<3 RK_PC1 3 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi1m1_cs0_hs: spi1m1-cs0 {
+			rockchip,pins =
+				/* spi1_cs0m1 */
+				<3 RK_PA1 3 &pcfg_pull_up_drv_level_1>;
+		};
+	};
+
+	spi2-hs {
+		/omit-if-no-ref/
+		spi2m0_pins_hs: spi2m0-pins {
+			rockchip,pins =
+				/* spi2_clkm0 */
+				<2 RK_PC1 4 &pcfg_pull_up_drv_level_1>,
+				/* spi2_misom0 */
+				<2 RK_PC2 4 &pcfg_pull_up_drv_level_1>,
+				/* spi2_mosim0 */
+				<2 RK_PC3 4 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi2m0_cs0_hs: spi2m0-cs0 {
+			rockchip,pins =
+				/* spi2_cs0m0 */
+				<2 RK_PC4 4 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi2m0_cs1_hs: spi2m0-cs1 {
+			rockchip,pins =
+				/* spi2_cs1m0 */
+				<2 RK_PC5 4 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi2m1_pins_hs: spi2m1-pins {
+			rockchip,pins =
+				/* spi2_clkm1 */
+				<3 RK_PA0 3 &pcfg_pull_up_drv_level_1>,
+				/* spi2_misom1 */
+				<2 RK_PD7 3 &pcfg_pull_up_drv_level_1>,
+				/* spi2_mosim1 */
+				<2 RK_PD6 3 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi2m1_cs0_hs: spi2m1-cs0 {
+			rockchip,pins =
+				/* spi2_cs0m1 */
+				<2 RK_PD5 3 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi2m1_cs1_hs: spi2m1-cs1 {
+			rockchip,pins =
+				/* spi2_cs1m1 */
+				<2 RK_PD4 3 &pcfg_pull_up_drv_level_1>;
+		};
+	};
+
+	spi3-hs {
+		/omit-if-no-ref/
+		spi3m0_pins_hs: spi3m0-pins {
+			rockchip,pins =
+				/* spi3_clkm0 */
+				<4 RK_PB3 4 &pcfg_pull_up_drv_level_1>,
+				/* spi3_misom0 */
+				<4 RK_PB0 4 &pcfg_pull_up_drv_level_1>,
+				/* spi3_mosim0 */
+				<4 RK_PB2 4 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi3m0_cs0_hs: spi3m0-cs0 {
+			rockchip,pins =
+				/* spi3_cs0m0 */
+				<4 RK_PA6 4 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi3m0_cs1_hs: spi3m0-cs1 {
+			rockchip,pins =
+				/* spi3_cs1m0 */
+				<4 RK_PA7 4 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi3m1_pins_hs: spi3m1-pins {
+			rockchip,pins =
+				/* spi3_clkm1 */
+				<4 RK_PC2 2 &pcfg_pull_up_drv_level_1>,
+				/* spi3_misom1 */
+				<4 RK_PC5 2 &pcfg_pull_up_drv_level_1>,
+				/* spi3_mosim1 */
+				<4 RK_PC3 2 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi3m1_cs0_hs: spi3m1-cs0 {
+			rockchip,pins =
+				/* spi3_cs0m1 */
+				<4 RK_PC6 2 &pcfg_pull_up_drv_level_1>;
+		};
+
+		/omit-if-no-ref/
+		spi3m1_cs1_hs: spi3m1-cs1 {
+			rockchip,pins =
+				/* spi3_cs1m1 */
+				<4 RK_PD1 2 &pcfg_pull_up_drv_level_1>;
+		};
+	};
+
+	gmac-txd-level3 {
+		/omit-if-no-ref/
+		gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 {
+			rockchip,pins =
+				/* gmac0_txd0 */
+				<2 RK_PB3 1 &pcfg_pull_none_drv_level_3>,
+				/* gmac0_txd1 */
+				<2 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
+				/* gmac0_txen */
+				<2 RK_PB5 1 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 {
+			rockchip,pins =
+				/* gmac0_rxd2 */
+				<2 RK_PA3 2 &pcfg_pull_none>,
+				/* gmac0_rxd3 */
+				<2 RK_PA4 2 &pcfg_pull_none>,
+				/* gmac0_txd2 */
+				<2 RK_PA6 2 &pcfg_pull_none_drv_level_3>,
+				/* gmac0_txd3 */
+				<2 RK_PA7 2 &pcfg_pull_none_drv_level_3>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 {
+			rockchip,pins =
+				/* gmac1_txd0m0 */
+				<3 RK_PB5 3 &pcfg_pull_none_drv_level_3>,
+				/* gmac1_txd1m0 */
+				<3 RK_PB6 3 &pcfg_pull_none_drv_level_3>,
+				/* gmac1_txenm0 */
+				<3 RK_PB7 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 {
+			rockchip,pins =
+				/* gmac1_rxd2m0 */
+				<3 RK_PA4 3 &pcfg_pull_none>,
+				/* gmac1_rxd3m0 */
+				<3 RK_PA5 3 &pcfg_pull_none>,
+				/* gmac1_txd2m0 */
+				<3 RK_PA2 3 &pcfg_pull_none_drv_level_3>,
+				/* gmac1_txd3m0 */
+				<3 RK_PA3 3 &pcfg_pull_none_drv_level_3>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 {
+			rockchip,pins =
+				/* gmac1_txd0m1 */
+				<4 RK_PA4 3 &pcfg_pull_none_drv_level_3>,
+				/* gmac1_txd1m1 */
+				<4 RK_PA5 3 &pcfg_pull_none_drv_level_3>,
+				/* gmac1_txenm1 */
+				<4 RK_PA6 3 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 {
+			rockchip,pins =
+				/* gmac1_rxd2m1 */
+				<4 RK_PA1 3 &pcfg_pull_none>,
+				/* gmac1_rxd3m1 */
+				<4 RK_PA2 3 &pcfg_pull_none>,
+				/* gmac1_txd2m1 */
+				<3 RK_PD6 3 &pcfg_pull_none_drv_level_3>,
+				/* gmac1_txd3m1 */
+				<3 RK_PD7 3 &pcfg_pull_none_drv_level_3>;
+		};
+	};
+
+	gmac-txc-level2 {
+		/omit-if-no-ref/
+		gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 {
+			rockchip,pins =
+				/* gmac0_rxclk */
+				<2 RK_PA5 2 &pcfg_pull_none>,
+				/* gmac0_txclk */
+				<2 RK_PB0 2 &pcfg_pull_none_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 {
+			rockchip,pins =
+				/* gmac1_rxclkm0 */
+				<3 RK_PA7 3 &pcfg_pull_none>,
+				/* gmac1_txclkm0 */
+				<3 RK_PA6 3 &pcfg_pull_none_drv_level_2>;
+		};
+
+		/omit-if-no-ref/
+		gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 {
+			rockchip,pins =
+				/* gmac1_rxclkm1 */
+				<4 RK_PA3 3 &pcfg_pull_none>,
+				/* gmac1_txclkm1 */
+				<4 RK_PA0 3 &pcfg_pull_none_drv_level_2>;
+		};
+	};
+};
diff --git a/arch/arm/dts/rk3568-u-boot.dtsi b/arch/arm/dts/rk3568-u-boot.dtsi
new file mode 100644
index 0000000..1570f13
--- /dev/null
+++ b/arch/arm/dts/rk3568-u-boot.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+/ {
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
+	};
+
+	dmc: dmc {
+		compatible = "rockchip,rk3568-dmc";
+		u-boot,dm-pre-reloc;
+		status = "okay";
+	};
+};
+
+&cru {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&pmucru {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&grf {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&pmugrf {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi
new file mode 100644
index 0000000..12a071e
--- /dev/null
+++ b/arch/arm/dts/rk3568.dtsi
@@ -0,0 +1,779 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rk3568-cru.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	compatible = "rockchip,rk3568";
+
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		gpio4 = &gpio4;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+		serial6 = &uart6;
+		serial7 = &uart7;
+		serial8 = &uart8;
+		serial9 = &uart9;
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x0>;
+			clocks = <&scmi_clk 0>;
+			enable-method = "psci";
+			operating-points-v2 = <&cpu0_opp_table>;
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			operating-points-v2 = <&cpu0_opp_table>;
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			operating-points-v2 = <&cpu0_opp_table>;
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			operating-points-v2 = <&cpu0_opp_table>;
+		};
+	};
+
+	cpu0_opp_table: cpu0-opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-408000000 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <900000 900000 1150000>;
+			clock-latency-ns = <40000>;
+		};
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <900000 900000 1150000>;
+		};
+
+		opp-816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <900000 900000 1150000>;
+			opp-suspend;
+		};
+
+		opp-1104000000 {
+			opp-hz = /bits/ 64 <1104000000>;
+			opp-microvolt = <900000 900000 1150000>;
+		};
+
+		opp-1416000000 {
+			opp-hz = /bits/ 64 <1416000000>;
+			opp-microvolt = <900000 900000 1150000>;
+		};
+
+		opp-1608000000 {
+			opp-hz = /bits/ 64 <1608000000>;
+			opp-microvolt = <975000 975000 1150000>;
+		};
+
+		opp-1800000000 {
+			opp-hz = /bits/ 64 <1800000000>;
+			opp-microvolt = <1050000 1050000 1150000>;
+		};
+
+		opp-1992000000 {
+			opp-hz = /bits/ 64 <1992000000>;
+			opp-microvolt = <1150000 1150000 1150000>;
+		};
+	};
+
+	firmware {
+		scmi: scmi {
+			compatible = "arm,scmi-smc";
+			arm,smc-id = <0x82000010>;
+			shmem = <&scmi_shmem>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			scmi_clk: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+		};
+
+	};
+
+	pmu {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		arm,no-tick-in-suspend;
+	};
+
+	xin24m: xin24m {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "xin24m";
+		#clock-cells = <0>;
+	};
+
+	xin32k: xin32k {
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+		pinctrl-0 = <&clk32k_out0>;
+		pinctrl-names = "default";
+		#clock-cells = <0>;
+	};
+
+	sram@10f000 {
+		compatible = "mmio-sram";
+		reg = <0x0 0x0010f000 0x0 0x100>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x0 0x0010f000 0x100>;
+
+		scmi_shmem: sram@0 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x0 0x100>;
+		};
+	};
+
+	gic: interrupt-controller@fd400000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
+		      <0x0 0xfd460000 0 0x80000>; /* GICR */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		mbi-alias = <0x0 0xfd100000>;
+		mbi-ranges = <296 24>;
+		msi-controller;
+	};
+
+	pmugrf: syscon@fdc20000 {
+		compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
+		reg = <0x0 0xfdc20000 0x0 0x10000>;
+	};
+
+	grf: syscon@fdc60000 {
+		compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
+		reg = <0x0 0xfdc60000 0x0 0x10000>;
+	};
+
+	pmucru: clock-controller@fdd00000 {
+		compatible = "rockchip,rk3568-pmucru";
+		reg = <0x0 0xfdd00000 0x0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	cru: clock-controller@fdd20000 {
+		compatible = "rockchip,rk3568-cru";
+		reg = <0x0 0xfdd20000 0x0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	i2c0: i2c@fdd40000 {
+		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+		reg = <0x0 0xfdd40000 0x0 0x1000>;
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
+		clock-names = "i2c", "pclk";
+		pinctrl-0 = <&i2c0_xfer>;
+		pinctrl-names = "default";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	uart0: serial@fdd50000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xfdd50000 0x0 0x100>;
+		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <&dmac0 0>, <&dmac0 1>;
+		pinctrl-0 = <&uart0_xfer>;
+		pinctrl-names = "default";
+		reg-io-width = <4>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	pwm0: pwm@fdd70000 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfdd70000 0x0 0x10>;
+		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm0m0_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pwm1: pwm@fdd70010 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfdd70010 0x0 0x10>;
+		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm1m0_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pwm2: pwm@fdd70020 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfdd70020 0x0 0x10>;
+		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm2m0_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pwm3: pwm@fdd70030 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfdd70030 0x0 0x10>;
+		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm3_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	sdmmc2: mmc@fe000000 {
+		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0x0 0xfe000000 0x0 0x4000>;
+		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
+			 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
+		max-frequency = <150000000>;
+		resets = <&cru SRST_SDMMC2>;
+		reset-names = "reset";
+		status = "disabled";
+	};
+
+	sdmmc0: mmc@fe2b0000 {
+		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0x0 0xfe2b0000 0x0 0x4000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
+			 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
+		max-frequency = <150000000>;
+		resets = <&cru SRST_SDMMC0>;
+		reset-names = "reset";
+		status = "disabled";
+	};
+
+	sdmmc1: mmc@fe2c0000 {
+		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0x0 0xfe2c0000 0x0 0x4000>;
+		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
+			 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
+		max-frequency = <150000000>;
+		resets = <&cru SRST_SDMMC1>;
+		reset-names = "reset";
+		status = "disabled";
+	};
+
+	sdhci: mmc@fe310000 {
+		compatible = "rockchip,rk3568-dwcmshc";
+		reg = <0x0 0xfe310000 0x0 0x10000>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+		assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
+		assigned-clock-rates = <200000000>, <24000000>;
+		clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
+			 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+			 <&cru TCLK_EMMC>;
+		clock-names = "core", "bus", "axi", "block", "timer";
+		status = "disabled";
+	};
+
+	dmac0: dmac@fe530000 {
+		compatible = "arm,pl330", "arm,primecell";
+		reg = <0x0 0xfe530000 0x0 0x4000>;
+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+		arm,pl330-periph-burst;
+		clocks = <&cru ACLK_BUS>;
+		clock-names = "apb_pclk";
+		#dma-cells = <1>;
+	};
+
+	dmac1: dmac@fe550000 {
+		compatible = "arm,pl330", "arm,primecell";
+		reg = <0x0 0xfe550000 0x0 0x4000>;
+		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+		arm,pl330-periph-burst;
+		clocks = <&cru ACLK_BUS>;
+		clock-names = "apb_pclk";
+		#dma-cells = <1>;
+	};
+
+	i2c1: i2c@fe5a0000 {
+		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+		reg = <0x0 0xfe5a0000 0x0 0x1000>;
+		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+		clock-names = "i2c", "pclk";
+		pinctrl-0 = <&i2c1_xfer>;
+		pinctrl-names = "default";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@fe5b0000 {
+		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+		reg = <0x0 0xfe5b0000 0x0 0x1000>;
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+		clock-names = "i2c", "pclk";
+		pinctrl-0 = <&i2c2m0_xfer>;
+		pinctrl-names = "default";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c3: i2c@fe5c0000 {
+		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+		reg = <0x0 0xfe5c0000 0x0 0x1000>;
+		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+		clock-names = "i2c", "pclk";
+		pinctrl-0 = <&i2c3m0_xfer>;
+		pinctrl-names = "default";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c4: i2c@fe5d0000 {
+		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+		reg = <0x0 0xfe5d0000 0x0 0x1000>;
+		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+		clock-names = "i2c", "pclk";
+		pinctrl-0 = <&i2c4m0_xfer>;
+		pinctrl-names = "default";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c5: i2c@fe5e0000 {
+		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+		reg = <0x0 0xfe5e0000 0x0 0x1000>;
+		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+		clock-names = "i2c", "pclk";
+		pinctrl-0 = <&i2c5m0_xfer>;
+		pinctrl-names = "default";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	wdt: watchdog@fe600000 {
+		compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
+		reg = <0x0 0xfe600000 0x0 0x100>;
+		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
+		clock-names = "tclk", "pclk";
+	};
+
+	uart1: serial@fe650000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xfe650000 0x0 0x100>;
+		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <&dmac0 2>, <&dmac0 3>;
+		pinctrl-0 = <&uart1m0_xfer>;
+		pinctrl-names = "default";
+		reg-io-width = <4>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart2: serial@fe660000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xfe660000 0x0 0x100>;
+		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <&dmac0 4>, <&dmac0 5>;
+		pinctrl-0 = <&uart2m0_xfer>;
+		pinctrl-names = "default";
+		reg-io-width = <4>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart3: serial@fe670000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xfe670000 0x0 0x100>;
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <&dmac0 6>, <&dmac0 7>;
+		pinctrl-0 = <&uart3m0_xfer>;
+		pinctrl-names = "default";
+		reg-io-width = <4>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart4: serial@fe680000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xfe680000 0x0 0x100>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <&dmac0 8>, <&dmac0 9>;
+		pinctrl-0 = <&uart4m0_xfer>;
+		pinctrl-names = "default";
+		reg-io-width = <4>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart5: serial@fe690000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xfe690000 0x0 0x100>;
+		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <&dmac0 10>, <&dmac0 11>;
+		pinctrl-0 = <&uart5m0_xfer>;
+		pinctrl-names = "default";
+		reg-io-width = <4>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart6: serial@fe6a0000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xfe6a0000 0x0 0x100>;
+		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <&dmac0 12>, <&dmac0 13>;
+		pinctrl-0 = <&uart6m0_xfer>;
+		pinctrl-names = "default";
+		reg-io-width = <4>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart7: serial@fe6b0000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xfe6b0000 0x0 0x100>;
+		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <&dmac0 14>, <&dmac0 15>;
+		pinctrl-0 = <&uart7m0_xfer>;
+		pinctrl-names = "default";
+		reg-io-width = <4>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart8: serial@fe6c0000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xfe6c0000 0x0 0x100>;
+		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <&dmac0 16>, <&dmac0 17>;
+		pinctrl-0 = <&uart8m0_xfer>;
+		pinctrl-names = "default";
+		reg-io-width = <4>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart9: serial@fe6d0000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xfe6d0000 0x0 0x100>;
+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <&dmac0 18>, <&dmac0 19>;
+		pinctrl-0 = <&uart9m0_xfer>;
+		pinctrl-names = "default";
+		reg-io-width = <4>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	pwm4: pwm@fe6e0000 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfe6e0000 0x0 0x10>;
+		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm4_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pwm5: pwm@fe6e0010 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfe6e0010 0x0 0x10>;
+		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm5_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pwm6: pwm@fe6e0020 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfe6e0020 0x0 0x10>;
+		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm6_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pwm7: pwm@fe6e0030 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfe6e0030 0x0 0x10>;
+		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm7_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pwm8: pwm@fe6f0000 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfe6f0000 0x0 0x10>;
+		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm8m0_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pwm9: pwm@fe6f0010 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfe6f0010 0x0 0x10>;
+		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm9m0_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pwm10: pwm@fe6f0020 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfe6f0020 0x0 0x10>;
+		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm10m0_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pwm11: pwm@fe6f0030 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfe6f0030 0x0 0x10>;
+		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm11m0_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pwm12: pwm@fe700000 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfe700000 0x0 0x10>;
+		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm12m0_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pwm13: pwm@fe700010 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfe700010 0x0 0x10>;
+		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm13m0_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pwm14: pwm@fe700020 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfe700020 0x0 0x10>;
+		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm14m0_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pwm15: pwm@fe700030 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x0 0xfe700030 0x0 0x10>;
+		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <&pwm15m0_pins>;
+		pinctrl-names = "active";
+		#pwm-cells = <3>;
+		status = "disabled";
+	};
+
+	pinctrl: pinctrl {
+		compatible = "rockchip,rk3568-pinctrl";
+		rockchip,grf = <&grf>;
+		rockchip,pmu = <&pmugrf>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gpio0: gpio@fdd60000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x0 0xfdd60000 0x0 0x100>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio1: gpio@fe740000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x0 0xfe740000 0x0 0x100>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio2: gpio@fe750000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x0 0xfe750000 0x0 0x100>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio3: gpio@fe760000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x0 0xfe760000 0x0 0x100>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio4: gpio@fe770000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x0 0xfe770000 0x0 0x100>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
+
+#include "rk3568-pinctrl.dtsi"
diff --git a/arch/arm/dts/rockchip-pinconf.dtsi b/arch/arm/dts/rockchip-pinconf.dtsi
new file mode 100644
index 0000000..5c64543
--- /dev/null
+++ b/arch/arm/dts/rockchip-pinconf.dtsi
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+&pinctrl {
+	/omit-if-no-ref/
+	pcfg_pull_up: pcfg-pull-up {
+		bias-pull-up;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down: pcfg-pull-down {
+		bias-pull-down;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none: pcfg-pull-none {
+		bias-disable;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
+		bias-disable;
+		drive-strength = <0>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
+		bias-disable;
+		drive-strength = <1>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
+		bias-disable;
+		drive-strength = <2>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
+		bias-disable;
+		drive-strength = <3>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
+		bias-disable;
+		drive-strength = <4>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
+		bias-disable;
+		drive-strength = <5>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
+		bias-disable;
+		drive-strength = <6>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
+		bias-disable;
+		drive-strength = <7>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
+		bias-disable;
+		drive-strength = <8>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
+		bias-disable;
+		drive-strength = <9>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
+		bias-disable;
+		drive-strength = <10>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
+		bias-disable;
+		drive-strength = <11>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
+		bias-disable;
+		drive-strength = <12>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
+		bias-disable;
+		drive-strength = <13>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
+		bias-disable;
+		drive-strength = <14>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
+		bias-disable;
+		drive-strength = <15>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
+		bias-pull-up;
+		drive-strength = <0>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
+		bias-pull-up;
+		drive-strength = <1>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
+		bias-pull-up;
+		drive-strength = <2>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
+		bias-pull-up;
+		drive-strength = <3>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
+		bias-pull-up;
+		drive-strength = <4>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
+		bias-pull-up;
+		drive-strength = <5>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
+		bias-pull-up;
+		drive-strength = <6>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
+		bias-pull-up;
+		drive-strength = <7>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
+		bias-pull-up;
+		drive-strength = <8>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
+		bias-pull-up;
+		drive-strength = <9>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
+		bias-pull-up;
+		drive-strength = <10>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
+		bias-pull-up;
+		drive-strength = <11>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
+		bias-pull-up;
+		drive-strength = <12>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
+		bias-pull-up;
+		drive-strength = <13>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
+		bias-pull-up;
+		drive-strength = <14>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
+		bias-pull-up;
+		drive-strength = <15>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
+		bias-pull-down;
+		drive-strength = <0>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
+		bias-pull-down;
+		drive-strength = <1>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
+		bias-pull-down;
+		drive-strength = <2>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
+		bias-pull-down;
+		drive-strength = <3>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
+		bias-pull-down;
+		drive-strength = <4>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
+		bias-pull-down;
+		drive-strength = <5>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
+		bias-pull-down;
+		drive-strength = <6>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
+		bias-pull-down;
+		drive-strength = <7>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
+		bias-pull-down;
+		drive-strength = <8>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
+		bias-pull-down;
+		drive-strength = <9>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
+		bias-pull-down;
+		drive-strength = <10>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
+		bias-pull-down;
+		drive-strength = <11>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
+		bias-pull-down;
+		drive-strength = <12>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
+		bias-pull-down;
+		drive-strength = <13>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
+		bias-pull-down;
+		drive-strength = <14>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
+		bias-pull-down;
+		drive-strength = <15>;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_up_smt: pcfg-pull-up-smt {
+		bias-pull-up;
+		input-schmitt-enable;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_down_smt: pcfg-pull-down-smt {
+		bias-pull-down;
+		input-schmitt-enable;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_smt: pcfg-pull-none-smt {
+		bias-disable;
+		input-schmitt-enable;
+	};
+
+	/omit-if-no-ref/
+	pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
+		bias-disable;
+		drive-strength = <0>;
+		input-schmitt-enable;
+	};
+
+	/omit-if-no-ref/
+	pcfg_output_high: pcfg-output-high {
+		output-high;
+	};
+
+	/omit-if-no-ref/
+	pcfg_output_low: pcfg-output-low {
+		output-low;
+	};
+};
diff --git a/arch/arm/include/asm/arch-rk3568/boot0.h b/arch/arm/include/asm/arch-rk3568/boot0.h
new file mode 100644
index 0000000..dea2b20
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3568/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3568/gpio.h b/arch/arm/include/asm/arch-rk3568/gpio.h
new file mode 100644
index 0000000..b48c0a5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3568/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
new file mode 100644
index 0000000..6c59033
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
@@ -0,0 +1,504 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3568_H
+#define _ASM_ARCH_CRU_RK3568_H
+
+#define MHz		1000000
+#define KHz		1000
+#define OSC_HZ		(24 * MHz)
+
+#define APLL_HZ		(816 * MHz)
+#define GPLL_HZ		(1188 * MHz)
+#define CPLL_HZ		(1000 * MHz)
+#define PPLL_HZ		(100 * MHz)
+
+/* RK3568 pll id */
+enum rk3568_pll_id {
+	APLL,
+	DPLL,
+	CPLL,
+	GPLL,
+	NPLL,
+	VPLL,
+	PPLL,
+	HPLL,
+	PLL_COUNT,
+};
+
+struct rk3568_clk_info {
+	unsigned long id;
+	char *name;
+	bool is_cru;
+};
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3568_pmuclk_priv {
+	struct rk3568_pmucru *pmucru;
+	ulong ppll_hz;
+	ulong hpll_hz;
+};
+
+struct rk3568_clk_priv {
+	struct rk3568_cru *cru;
+	struct rk3568_grf *grf;
+	ulong ppll_hz;
+	ulong hpll_hz;
+	ulong gpll_hz;
+	ulong cpll_hz;
+	ulong npll_hz;
+	ulong vpll_hz;
+	ulong armclk_hz;
+	ulong armclk_enter_hz;
+	ulong armclk_init_hz;
+	bool sync_kernel;
+	bool set_armclk_rate;
+};
+
+struct rk3568_pll {
+	unsigned int con0;
+	unsigned int con1;
+	unsigned int con2;
+	unsigned int con3;
+	unsigned int con4;
+	unsigned int reserved0[3];
+};
+
+struct rk3568_pmucru {
+	struct rk3568_pll pll[2];/* Address Offset: 0x0000 */
+	unsigned int reserved0[16];/* Address Offset: 0x0040 */
+	unsigned int mode_con00;/* Address Offset: 0x0080 */
+	unsigned int reserved1[31];/* Address Offset: 0x0084 */
+	unsigned int pmu_clksel_con[10];/* Address Offset: 0x0100 */
+	unsigned int reserved2[22];/* Address Offset: 0x0128 */
+	unsigned int pmu_clkgate_con[3];/* Address Offset: 0x0180 */
+	unsigned int reserved3[29];/* Address Offset: 0x018C */
+	unsigned int pmu_softrst_con[1];/* Address Offset: 0x0200 */
+};
+
+check_member(rk3568_pmucru, mode_con00, 0x80);
+check_member(rk3568_pmucru, pmu_softrst_con[0], 0x200);
+
+struct rk3568_cru {
+	struct rk3568_pll pll[6];
+	unsigned int mode_con00;/* Address Offset: 0x00C0 */
+	unsigned int misc_con[3];/* Address Offset: 0x00C4 */
+	unsigned int glb_cnt_th;/* Address Offset: 0x00D0 */
+	unsigned int glb_srst_fst;/* Address Offset: 0x00D4 */
+	unsigned int glb_srsr_snd; /* Address Offset: 0x00D8 */
+	unsigned int glb_rst_con;/* Address Offset: 0x00DC */
+	unsigned int glb_rst_st;/* Address Offset: 0x00E0 */
+	unsigned int reserved0[7];/* Address Offset: 0x00E4 */
+	unsigned int clksel_con[85]; /* Address Offset: 0x0100 */
+	unsigned int reserved1[43];/* Address Offset: 0x0254 */
+	unsigned int clkgate_con[36];/* Address Offset: 0x0300 */
+	unsigned int reserved2[28]; /* Address Offset: 0x0390 */
+	unsigned int softrst_con[30];/* Address Offset: 0x0400 */
+	unsigned int reserved3[2];/* Address Offset: 0x0478 */
+	unsigned int ssgtbl[32];/* Address Offset: 0x0480 */
+	unsigned int reserved4[32];/* Address Offset: 0x0500 */
+	unsigned int sdmmc0_con[2];/* Address Offset: 0x0580 */
+	unsigned int sdmmc1_con[2];/* Address Offset: 0x058C */
+	unsigned int sdmmc2_con[2];/* Address Offset: 0x0590 */
+	unsigned int emmc_con[2];/* Address Offset: 0x0598 */
+};
+
+check_member(rk3568_cru, mode_con00, 0xc0);
+check_member(rk3568_cru, softrst_con[0], 0x400);
+
+struct pll_rate_table {
+	unsigned long rate;
+	unsigned int fbdiv;
+	unsigned int postdiv1;
+	unsigned int refdiv;
+	unsigned int postdiv2;
+	unsigned int dsmpd;
+	unsigned int frac;
+};
+
+#define RK3568_PMU_MODE			0x80
+#define RK3568_PMU_PLL_CON(x)		((x) * 0x4)
+#define RK3568_PLL_CON(x)		((x) * 0x4)
+#define RK3568_MODE_CON			0xc0
+
+enum {
+	/* CRU_PMU_CLK_SEL0_CON */
+	RTC32K_SEL_SHIFT		= 6,
+	RTC32K_SEL_MASK			= 0x3 << RTC32K_SEL_SHIFT,
+	RTC32K_SEL_PMUPVTM		= 0,
+	RTC32K_SEL_OSC1_32K,
+	RTC32K_SEL_OSC0_DIV32K,
+
+	/* CRU_PMU_CLK_SEL1_CON */
+	RTC32K_FRAC_NUMERATOR_SHIFT	= 16,
+	RTC32K_FRAC_NUMERATOR_MASK	= 0xffff << 16,
+	RTC32K_FRAC_DENOMINATOR_SHIFT	= 0,
+	RTC32K_FRAC_DENOMINATOR_MASK	= 0xffff,
+
+	/* CRU_PMU_CLK_SEL2_CON */
+	PCLK_PDPMU_SEL_SHIFT		= 15,
+	PCLK_PDPMU_SEL_MASK		= 1 << PCLK_PDPMU_SEL_SHIFT,
+	PCLK_PDPMU_SEL_PPLL		= 0,
+	PCLK_PDPMU_SEL_GPLL,
+	PCLK_PDPMU_DIV_SHIFT		= 0,
+	PCLK_PDPMU_DIV_MASK		= 0x1f,
+
+	/* CRU_PMU_CLK_SEL3_CON */
+	CLK_I2C0_DIV_SHIFT		= 0,
+	CLK_I2C0_DIV_MASK		= 0x7f,
+
+	/* CRU_PMU_CLK_SEL6_CON */
+	CLK_PWM0_SEL_SHIFT		= 7,
+	CLK_PWM0_SEL_MASK		= 1 << CLK_PWM0_SEL_SHIFT,
+	CLK_PWM0_SEL_XIN24M		= 0,
+	CLK_PWM0_SEL_PPLL,
+	CLK_PWM0_DIV_SHIFT		= 0,
+	CLK_PWM0_DIV_MASK		= 0x7f,
+
+	/* CRU_CLK_SEL0_CON */
+	CLK_CORE_PRE_SEL_SHIFT		= 7,
+	CLK_CORE_PRE_SEL_MASK		= 1 << CLK_CORE_PRE_SEL_SHIFT,
+	CLK_CORE_PRE_SEL_SRC		= 0,
+	CLK_CORE_PRE_SEL_APLL,
+
+	/* CRU_CLK_SEL2_CON */
+	SCLK_CORE_PRE_SEL_SHIFT		= 15,
+	SCLK_CORE_PRE_SEL_MASK		= 1 << SCLK_CORE_PRE_SEL_SHIFT,
+	SCLK_CORE_PRE_SEL_SRC		= 0,
+	SCLK_CORE_PRE_SEL_NPLL,
+	SCLK_CORE_SRC_SEL_SHIFT		= 8,
+	SCLK_CORE_SRC_SEL_MASK		= 3 << SCLK_CORE_SRC_SEL_SHIFT,
+	SCLK_CORE_SRC_SEL_APLL		= 0,
+	SCLK_CORE_SRC_SEL_GPLL,
+	SCLK_CORE_SRC_SEL_NPLL,
+	SCLK_CORE_SRC_DIV_SHIFT		= 0,
+	SCLK_CORE_SRC_DIV_MASK		= 0x1f << SCLK_CORE_SRC_DIV_SHIFT,
+
+	/* CRU_CLK_SEL3_CON */
+	GICCLK_CORE_DIV_SHIFT		= 8,
+	GICCLK_CORE_DIV_MASK		= 0x1f << GICCLK_CORE_DIV_SHIFT,
+	ATCLK_CORE_DIV_SHIFT		= 0,
+	ATCLK_CORE_DIV_MASK		= 0x1f << ATCLK_CORE_DIV_SHIFT,
+
+	/* CRU_CLK_SEL4_CON */
+	PERIPHCLK_CORE_PRE_DIV_SHIFT	= 8,
+	PERIPHCLK_CORE_PRE_DIV_MASK	= 0x1f << PERIPHCLK_CORE_PRE_DIV_SHIFT,
+	PCLK_CORE_PRE_DIV_SHIFT		= 0,
+	PCLK_CORE_PRE_DIV_MASK		= 0x1f << PCLK_CORE_PRE_DIV_SHIFT,
+
+	/* CRU_CLK_SEL5_CON */
+	ACLK_CORE_NIU2BUS_SEL_SHIFT	= 14,
+	ACLK_CORE_NIU2BUS_SEL_MASK	= 0x3 << ACLK_CORE_NIU2BUS_SEL_SHIFT,
+	ACLK_CORE_NDFT_DIV_SHIFT	= 8,
+	ACLK_CORE_NDFT_DIV_MASK		= 0x1f << ACLK_CORE_NDFT_DIV_SHIFT,
+
+	/* CRU_CLK_SEL10_CON */
+	HCLK_PERIMID_SEL_SHIFT		= 6,
+	HCLK_PERIMID_SEL_MASK		= 3 << HCLK_PERIMID_SEL_SHIFT,
+	HCLK_PERIMID_SEL_150M		= 0,
+	HCLK_PERIMID_SEL_100M,
+	HCLK_PERIMID_SEL_75M,
+	HCLK_PERIMID_SEL_24M,
+	ACLK_PERIMID_SEL_SHIFT		= 4,
+	ACLK_PERIMID_SEL_MASK		= 3 << ACLK_PERIMID_SEL_SHIFT,
+	ACLK_PERIMID_SEL_300M		= 0,
+	ACLK_PERIMID_SEL_200M,
+	ACLK_PERIMID_SEL_100M,
+	ACLK_PERIMID_SEL_24M,
+
+	/* CRU_CLK_SEL27_CON */
+	CLK_CRYPTO_PKA_SEL_SHIFT	= 6,
+	CLK_CRYPTO_PKA_SEL_MASK		= 3 << CLK_CRYPTO_PKA_SEL_SHIFT,
+	CLK_CRYPTO_PKA_SEL_300M		= 0,
+	CLK_CRYPTO_PKA_SEL_200M,
+	CLK_CRYPTO_PKA_SEL_100M,
+	CLK_CRYPTO_CORE_SEL_SHIFT	= 4,
+	CLK_CRYPTO_CORE_SEL_MASK	= 3 << CLK_CRYPTO_CORE_SEL_SHIFT,
+	CLK_CRYPTO_CORE_SEL_200M	= 0,
+	CLK_CRYPTO_CORE_SEL_150M,
+	CLK_CRYPTO_CORE_SEL_100M,
+	HCLK_SECURE_FLASH_SEL_SHIFT	= 2,
+	HCLK_SECURE_FLASH_SEL_MASK	= 3 << HCLK_SECURE_FLASH_SEL_SHIFT,
+	HCLK_SECURE_FLASH_SEL_150M	= 0,
+	HCLK_SECURE_FLASH_SEL_100M,
+	HCLK_SECURE_FLASH_SEL_75M,
+	HCLK_SECURE_FLASH_SEL_24M,
+	ACLK_SECURE_FLASH_SEL_SHIFT	= 0,
+	ACLK_SECURE_FLASH_SEL_MASK	= 3 << ACLK_SECURE_FLASH_SEL_SHIFT,
+	ACLK_SECURE_FLASH_SEL_200M	= 0,
+	ACLK_SECURE_FLASH_SEL_150M,
+	ACLK_SECURE_FLASH_SEL_100M,
+	ACLK_SECURE_FLASH_SEL_24M,
+
+	/* CRU_CLK_SEL28_CON */
+	CCLK_EMMC_SEL_SHIFT		= 12,
+	CCLK_EMMC_SEL_MASK		= 7 << CCLK_EMMC_SEL_SHIFT,
+	CCLK_EMMC_SEL_24M		= 0,
+	CCLK_EMMC_SEL_200M,
+	CCLK_EMMC_SEL_150M,
+	CCLK_EMMC_SEL_100M,
+	CCLK_EMMC_SEL_50M,
+	CCLK_EMMC_SEL_375K,
+	BCLK_EMMC_SEL_SHIFT		= 8,
+	BCLK_EMMC_SEL_MASK		= 3 << BCLK_EMMC_SEL_SHIFT,
+	BCLK_EMMC_SEL_200M		= 0,
+	BCLK_EMMC_SEL_150M,
+	BCLK_EMMC_SEL_125M,
+	SCLK_SFC_SEL_SHIFT		= 4,
+	SCLK_SFC_SEL_MASK		= 7 << SCLK_SFC_SEL_SHIFT,
+	SCLK_SFC_SEL_24M		= 0,
+	SCLK_SFC_SEL_50M,
+	SCLK_SFC_SEL_75M,
+	SCLK_SFC_SEL_100M,
+	SCLK_SFC_SEL_125M,
+	SCLK_SFC_SEL_150M,
+	NCLK_NANDC_SEL_SHIFT		= 0,
+	NCLK_NANDC_SEL_MASK		= 3 << NCLK_NANDC_SEL_SHIFT,
+	NCLK_NANDC_SEL_200M		= 0,
+	NCLK_NANDC_SEL_150M,
+	NCLK_NANDC_SEL_100M,
+	NCLK_NANDC_SEL_24M,
+
+	/* CRU_CLK_SEL30_CON */
+	CLK_SDMMC1_SEL_SHIFT		= 12,
+	CLK_SDMMC1_SEL_MASK		= 7 << CLK_SDMMC1_SEL_SHIFT,
+	CLK_SDMMC0_SEL_SHIFT		= 8,
+	CLK_SDMMC0_SEL_MASK		= 7 << CLK_SDMMC0_SEL_SHIFT,
+	CLK_SDMMC_SEL_24M		= 0,
+	CLK_SDMMC_SEL_400M,
+	CLK_SDMMC_SEL_300M,
+	CLK_SDMMC_SEL_100M,
+	CLK_SDMMC_SEL_50M,
+	CLK_SDMMC_SEL_750K,
+
+	/* CRU_CLK_SEL31_CON */
+	CLK_MAC0_OUT_SEL_SHIFT		= 14,
+	CLK_MAC0_OUT_SEL_MASK		= 3 << CLK_MAC0_OUT_SEL_SHIFT,
+	CLK_MAC0_OUT_SEL_125M		= 0,
+	CLK_MAC0_OUT_SEL_50M,
+	CLK_MAC0_OUT_SEL_25M,
+	CLK_MAC0_OUT_SEL_24M,
+	CLK_GMAC0_PTP_REF_SEL_SHIFT	= 12,
+	CLK_GMAC0_PTP_REF_SEL_MASK	= 3 << CLK_GMAC0_PTP_REF_SEL_SHIFT,
+	CLK_GMAC0_PTP_REF_SEL_62_5M	= 0,
+	CLK_GMAC0_PTP_REF_SEL_100M,
+	CLK_GMAC0_PTP_REF_SEL_50M,
+	CLK_GMAC0_PTP_REF_SEL_24M,
+	CLK_MAC0_2TOP_SEL_SHIFT		= 8,
+	CLK_MAC0_2TOP_SEL_MASK		= 3 << CLK_MAC0_2TOP_SEL_SHIFT,
+	CLK_MAC0_2TOP_SEL_125M		= 0,
+	CLK_MAC0_2TOP_SEL_50M,
+	CLK_MAC0_2TOP_SEL_25M,
+	CLK_MAC0_2TOP_SEL_PPLL,
+	RGMII0_CLK_SEL_SHIFT		= 4,
+	RGMII0_CLK_SEL_MASK		= 3 << RGMII0_CLK_SEL_SHIFT,
+	RGMII0_CLK_SEL_125M		= 0,
+	RGMII0_CLK_SEL_125M_1,
+	RGMII0_CLK_SEL_2_5M,
+	RGMII0_CLK_SEL_25M,
+	RMII0_CLK_SEL_SHIFT		= 3,
+	RMII0_CLK_SEL_MASK		= 1 << RMII0_CLK_SEL_SHIFT,
+	RMII0_CLK_SEL_2_5M		= 0,
+	RMII0_CLK_SEL_25M,
+	RMII0_EXTCLK_SEL_SHIFT		= 2,
+	RMII0_EXTCLK_SEL_MASK		= 1 << RMII0_EXTCLK_SEL_SHIFT,
+	RMII0_EXTCLK_SEL_MAC0_TOP	= 0,
+	RMII0_EXTCLK_SEL_IO,
+	RMII0_MODE_SHIFT		= 0,
+	RMII0_MODE_MASK			= 3 << RMII0_MODE_SHIFT,
+	RMII0_MODE_SEL_RGMII		= 0,
+	RMII0_MODE_SEL_RMII,
+	RMII0_MODE_SEL_GMII,
+
+	/* CRU_CLK_SEL32_CON */
+	CLK_SDMMC2_SEL_SHIFT		= 8,
+	CLK_SDMMC2_SEL_MASK		= 7 << CLK_SDMMC2_SEL_SHIFT,
+
+	/* CRU_CLK_SEL38_CON */
+	ACLK_VOP_PRE_SEL_SHIFT		= 6,
+	ACLK_VOP_PRE_SEL_MASK		= 3 << ACLK_VOP_PRE_SEL_SHIFT,
+	ACLK_VOP_PRE_SEL_CPLL		= 0,
+	ACLK_VOP_PRE_SEL_GPLL,
+	ACLK_VOP_PRE_SEL_HPLL,
+	ACLK_VOP_PRE_SEL_VPLL,
+	ACLK_VOP_PRE_DIV_SHIFT		= 0,
+	ACLK_VOP_PRE_DIV_MASK		= 0x1f << ACLK_VOP_PRE_DIV_SHIFT,
+
+	/* CRU_CLK_SEL39_CON */
+	DCLK0_VOP_SEL_SHIFT		= 10,
+	DCLK0_VOP_SEL_MASK		= 3 << DCLK0_VOP_SEL_SHIFT,
+	DCLK_VOP_SEL_HPLL		= 0,
+	DCLK_VOP_SEL_VPLL,
+	DCLK_VOP_SEL_GPLL,
+	DCLK_VOP_SEL_CPLL,
+	DCLK0_VOP_DIV_SHIFT		= 0,
+	DCLK0_VOP_DIV_MASK		= 0xff << DCLK0_VOP_DIV_SHIFT,
+
+	/* CRU_CLK_SEL40_CON */
+	DCLK1_VOP_SEL_SHIFT		= 10,
+	DCLK1_VOP_SEL_MASK		= 3 << DCLK1_VOP_SEL_SHIFT,
+	DCLK1_VOP_DIV_SHIFT		= 0,
+	DCLK1_VOP_DIV_MASK		= 0xff << DCLK1_VOP_DIV_SHIFT,
+
+	/* CRU_CLK_SEL41_CON */
+	DCLK2_VOP_SEL_SHIFT		= 10,
+	DCLK2_VOP_SEL_MASK		= 3 << DCLK2_VOP_SEL_SHIFT,
+	DCLK2_VOP_DIV_SHIFT		= 0,
+	DCLK2_VOP_DIV_MASK		= 0xff << DCLK2_VOP_DIV_SHIFT,
+
+	/* CRU_CLK_SEL43_CON */
+	DCLK_EBC_SEL_SHIFT		= 6,
+	DCLK_EBC_SEL_MASK		= 3 << DCLK_EBC_SEL_SHIFT,
+	DCLK_EBC_SEL_GPLL_400M		= 0,
+	DCLK_EBC_SEL_CPLL_333M,
+	DCLK_EBC_SEL_GPLL_200M,
+
+	/* CRU_CLK_SEL47_CON */
+	ACLK_RKVDEC_SEL_SHIFT		= 7,
+	ACLK_RKVDEC_SEL_MASK		= 1 << ACLK_RKVDEC_SEL_SHIFT,
+	ACLK_RKVDEC_SEL_GPLL		= 0,
+	ACLK_RKVDEC_SEL_CPLL,
+	ACLK_RKVDEC_DIV_SHIFT		= 0,
+	ACLK_RKVDEC_DIV_MASK		= 0x1f << ACLK_RKVDEC_DIV_SHIFT,
+
+	/* CRU_CLK_SEL49_CON */
+	CLK_RKVDEC_CORE_SEL_SHIFT	= 14,
+	CLK_RKVDEC_CORE_SEL_MASK	= 0x3 << CLK_RKVDEC_CORE_SEL_SHIFT,
+	CLK_RKVDEC_CORE_SEL_GPLL	= 0,
+	CLK_RKVDEC_CORE_SEL_CPLL,
+	CLK_RKVDEC_CORE_SEL_NPLL,
+	CLK_RKVDEC_CORE_SEL_VPLL,
+	CLK_RKVDEC_CORE_DIV_SHIFT	= 8,
+	CLK_RKVDEC_CORE_DIV_MASK	= 0x1f << CLK_RKVDEC_CORE_DIV_SHIFT,
+
+	/* CRU_CLK_SEL50_CON */
+	PCLK_BUS_SEL_SHIFT		= 4,
+	PCLK_BUS_SEL_MASK		= 3 << PCLK_BUS_SEL_SHIFT,
+	PCLK_BUS_SEL_100M		= 0,
+	PCLK_BUS_SEL_75M,
+	PCLK_BUS_SEL_50M,
+	PCLK_BUS_SEL_24M,
+	ACLK_BUS_SEL_SHIFT		= 0,
+	ACLK_BUS_SEL_MASK		= 3 << ACLK_BUS_SEL_SHIFT,
+	ACLK_BUS_SEL_200M		= 0,
+	ACLK_BUS_SEL_150M,
+	ACLK_BUS_SEL_100M,
+	ACLK_BUS_SEL_24M,
+
+	/* CRU_CLK_SEL51_CON */
+	CLK_TSADC_DIV_SHIFT		= 8,
+	CLK_TSADC_DIV_MASK		= 0x7f << CLK_TSADC_DIV_SHIFT,
+	CLK_TSADC_TSEN_SEL_SHIFT	= 4,
+	CLK_TSADC_TSEN_SEL_MASK		= 0x3 << CLK_TSADC_TSEN_SEL_SHIFT,
+	CLK_TSADC_TSEN_SEL_24M		= 0,
+	CLK_TSADC_TSEN_SEL_100M,
+	CLK_TSADC_TSEN_SEL_CPLL_100M,
+	CLK_TSADC_TSEN_DIV_SHIFT	= 0,
+	CLK_TSADC_TSEN_DIV_MASK		= 0x7 << CLK_TSADC_TSEN_DIV_SHIFT,
+
+	/* CRU_CLK_SEL52_CON */
+	CLK_UART_SEL_SHIFT		= 12,
+	CLK_UART_SEL_MASK		= 0x3 << CLK_UART_SEL_SHIFT,
+	CLK_UART_SEL_SRC		= 0,
+	CLK_UART_SEL_FRAC,
+	CLK_UART_SEL_XIN24M,
+	CLK_UART_SRC_SEL_SHIFT		= 8,
+	CLK_UART_SRC_SEL_MASK		= 0x3 << CLK_UART_SRC_SEL_SHIFT,
+	CLK_UART_SRC_SEL_GPLL		= 0,
+	CLK_UART_SRC_SEL_CPLL,
+	CLK_UART_SRC_SEL_480M,
+	CLK_UART_SRC_DIV_SHIFT		= 0,
+	CLK_UART_SRC_DIV_MASK		= 0x3f << CLK_UART_SRC_DIV_SHIFT,
+
+	/* CRU_CLK_SEL53_CON */
+	CLK_UART_FRAC_NUMERATOR_SHIFT	= 16,
+	CLK_UART_FRAC_NUMERATOR_MASK	= 0xffff << 16,
+	CLK_UART_FRAC_DENOMINATOR_SHIFT	= 0,
+	CLK_UART_FRAC_DENOMINATOR_MASK	= 0xffff,
+
+	/* CRU_CLK_SEL71_CON */
+	CLK_I2C_SEL_SHIFT		= 8,
+	CLK_I2C_SEL_MASK		= 3 << CLK_I2C_SEL_SHIFT,
+	CLK_I2C_SEL_200M		= 0,
+	CLK_I2C_SEL_100M,
+	CLK_I2C_SEL_24M,
+	CLK_I2C_SEL_CPLL_100M,
+
+	/* CRU_CLK_SEL72_CON */
+	CLK_PWM3_SEL_SHIFT		= 12,
+	CLK_PWM3_SEL_MASK		= 3 << CLK_PWM3_SEL_SHIFT,
+	CLK_PWM2_SEL_SHIFT		= 10,
+	CLK_PWM2_SEL_MASK		= 3 << CLK_PWM2_SEL_SHIFT,
+	CLK_PWM1_SEL_SHIFT		= 8,
+	CLK_PWM1_SEL_MASK		= 3 << CLK_PWM1_SEL_SHIFT,
+	CLK_PWM_SEL_100M		= 0,
+	CLK_PWM_SEL_24M,
+	CLK_PWM_SEL_CPLL_100M,
+	CLK_SPI3_SEL_SHIFT		= 6,
+	CLK_SPI3_SEL_MASK		= 3 << CLK_SPI3_SEL_SHIFT,
+	CLK_SPI2_SEL_SHIFT		= 4,
+	CLK_SPI2_SEL_MASK		= 3 << CLK_SPI2_SEL_SHIFT,
+	CLK_SPI1_SEL_SHIFT		= 2,
+	CLK_SPI1_SEL_MASK		= 3 << CLK_SPI1_SEL_SHIFT,
+	CLK_SPI0_SEL_SHIFT		= 0,
+	CLK_SPI0_SEL_MASK		= 3 << CLK_SPI0_SEL_SHIFT,
+	CLK_SPI_SEL_200M		= 0,
+	CLK_SPI_SEL_24M,
+	CLK_SPI_SEL_CPLL_100M,
+
+	/* CRU_CLK_SEL73_CON */
+	PCLK_TOP_SEL_SHIFT		= 12,
+	PCLK_TOP_SEL_MASK		= 3 << PCLK_TOP_SEL_SHIFT,
+	PCLK_TOP_SEL_100M		= 0,
+	PCLK_TOP_SEL_75M,
+	PCLK_TOP_SEL_50M,
+	PCLK_TOP_SEL_24M,
+	HCLK_TOP_SEL_SHIFT		= 8,
+	HCLK_TOP_SEL_MASK		= 3 << HCLK_TOP_SEL_SHIFT,
+	HCLK_TOP_SEL_150M		= 0,
+	HCLK_TOP_SEL_100M,
+	HCLK_TOP_SEL_75M,
+	HCLK_TOP_SEL_24M,
+	ACLK_TOP_LOW_SEL_SHIFT		= 4,
+	ACLK_TOP_LOW_SEL_MASK		= 3 << ACLK_TOP_LOW_SEL_SHIFT,
+	ACLK_TOP_LOW_SEL_400M		= 0,
+	ACLK_TOP_LOW_SEL_300M,
+	ACLK_TOP_LOW_SEL_200M,
+	ACLK_TOP_LOW_SEL_24M,
+	ACLK_TOP_HIGH_SEL_SHIFT		= 0,
+	ACLK_TOP_HIGH_SEL_MASK		= 3 << ACLK_TOP_HIGH_SEL_SHIFT,
+	ACLK_TOP_HIGH_SEL_500M		= 0,
+	ACLK_TOP_HIGH_SEL_400M,
+	ACLK_TOP_HIGH_SEL_300M,
+	ACLK_TOP_HIGH_SEL_24M,
+
+	/* CRU_CLK_SEL78_CON */
+	CPLL_500M_DIV_SHIFT		= 8,
+	CPLL_500M_DIV_MASK		= 0x1f << CPLL_500M_DIV_SHIFT,
+
+	/* CRU_CLK_SEL79_CON */
+	CPLL_250M_DIV_SHIFT		= 8,
+	CPLL_250M_DIV_MASK		= 0x1f << CPLL_250M_DIV_SHIFT,
+	CPLL_333M_DIV_SHIFT		= 0,
+	CPLL_333M_DIV_MASK		= 0x1f << CPLL_333M_DIV_SHIFT,
+
+	/* CRU_CLK_SEL80_CON */
+	CPLL_62P5M_DIV_SHIFT		= 8,
+	CPLL_62P5M_DIV_MASK		= 0x1f << CPLL_62P5M_DIV_SHIFT,
+	CPLL_125M_DIV_SHIFT		= 0,
+	CPLL_125M_DIV_MASK		= 0x1f << CPLL_125M_DIV_SHIFT,
+
+	/* CRU_CLK_SEL81_CON */
+	CPLL_25M_DIV_SHIFT		= 8,
+	CPLL_25M_DIV_MASK		= 0x1f << CPLL_25M_DIV_SHIFT,
+	CPLL_50M_DIV_SHIFT		= 0,
+	CPLL_50M_DIV_MASK		= 0x1f << CPLL_50M_DIV_SHIFT,
+
+	/* CRU_CLK_SEL82_CON */
+	CPLL_100M_DIV_SHIFT		= 0,
+	CPLL_100M_DIV_MASK		= 0x1f << CPLL_100M_DIV_SHIFT,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3568.h b/arch/arm/include/asm/arch-rockchip/grf_rk3568.h
new file mode 100644
index 0000000..d4e9b56
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3568.h
@@ -0,0 +1,369 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3568_GRF_H__
+#define __SOC_ROCKCHIP_RK3568_GRF_H__
+
+struct rk3568_grf {
+	unsigned int gpio1a_iomux_l;
+	unsigned int gpio1a_iomux_h;
+	unsigned int gpio1b_iomux_l;
+	unsigned int gpio1b_iomux_h;
+	unsigned int gpio1c_iomux_l;
+	unsigned int gpio1c_iomux_h;
+	unsigned int gpio1d_iomux_l;
+	unsigned int gpio1d_iomux_h;
+	unsigned int gpio2a_iomux_l;
+	unsigned int gpio2a_iomux_h;
+	unsigned int gpio2b_iomux_l;
+	unsigned int gpio2b_iomux_h;
+	unsigned int gpio2c_iomux_l;
+	unsigned int gpio2c_iomux_h;
+	unsigned int gpio2d_iomux_l;
+	unsigned int gpio2d_iomux_h;
+	unsigned int gpio3a_iomux_l;
+	unsigned int gpio3a_iomux_h;
+	unsigned int gpio3b_iomux_l;
+	unsigned int gpio3b_iomux_h;
+	unsigned int gpio3c_iomux_l;
+	unsigned int gpio3c_iomux_h;
+	unsigned int gpio3d_iomux_l;
+	unsigned int gpio3d_iomux_h;
+	unsigned int gpio4a_iomux_l;
+	unsigned int gpio4a_iomux_h;
+	unsigned int gpio4b_iomux_l;
+	unsigned int gpio4b_iomux_h;
+	unsigned int gpio4c_iomux_l;
+	unsigned int gpio4c_iomux_h;
+	unsigned int gpio4d_iomux_l;
+	unsigned int reserved0[(0x0080 - 0x0078) / 4 - 1];
+	unsigned int gpio1a_p;
+	unsigned int gpio1b_p;
+	unsigned int gpio1c_p;
+	unsigned int gpio1d_p;
+	unsigned int gpio2a_p;
+	unsigned int gpio2b_p;
+	unsigned int gpio2c_p;
+	unsigned int gpio2d_p;
+	unsigned int gpio3a_p;
+	unsigned int gpio3b_p;
+	unsigned int gpio3c_p;
+	unsigned int gpio3d_p;
+	unsigned int gpio4a_p;
+	unsigned int gpio4b_p;
+	unsigned int gpio4c_p;
+	unsigned int gpio4d_p;
+	unsigned int gpio1a_ie;
+	unsigned int gpio1b_ie;
+	unsigned int gpio1c_ie;
+	unsigned int gpio1d_ie;
+	unsigned int gpio2a_ie;
+	unsigned int gpio2b_ie;
+	unsigned int gpio2c_ie;
+	unsigned int gpio2d_ie;
+	unsigned int gpio3a_ie;
+	unsigned int gpio3b_ie;
+	unsigned int gpio3c_ie;
+	unsigned int gpio3d_ie;
+	unsigned int gpio4a_ie;
+	unsigned int gpio4b_ie;
+	unsigned int gpio4c_ie;
+	unsigned int gpio4d_ie;
+	unsigned int gpio1a_opd;
+	unsigned int gpio1b_opd;
+	unsigned int gpio1c_opd;
+	unsigned int gpio1d_opd;
+	unsigned int gpio2a_opd;
+	unsigned int gpio2b_opd;
+	unsigned int gpio2c_opd;
+	unsigned int gpio2d_opd;
+	unsigned int gpio3a_opd;
+	unsigned int gpio3b_opd;
+	unsigned int gpio3c_opd;
+	unsigned int gpio3d_opd;
+	unsigned int gpio4a_opd;
+	unsigned int gpio4b_opd;
+	unsigned int gpio4c_opd;
+	unsigned int gpio4d_opd;
+	unsigned int gpio1a_sus;
+	unsigned int gpio1b_sus;
+	unsigned int gpio1c_sus;
+	unsigned int gpio1d_sus;
+	unsigned int gpio2a_sus;
+	unsigned int gpio2b_sus;
+	unsigned int gpio2c_sus;
+	unsigned int gpio2d_sus;
+	unsigned int gpio3a_sus;
+	unsigned int gpio3b_sus;
+	unsigned int gpio3c_sus;
+	unsigned int gpio3d_sus;
+	unsigned int gpio4a_sus;
+	unsigned int gpio4b_sus;
+	unsigned int gpio4c_sus;
+	unsigned int gpio4d_sus;
+	unsigned int gpio1a_sl;
+	unsigned int gpio1b_sl;
+	unsigned int gpio1c_sl;
+	unsigned int gpio1d_sl;
+	unsigned int gpio2a_sl;
+	unsigned int gpio2b_sl;
+	unsigned int gpio2c_sl;
+	unsigned int gpio2d_sl;
+	unsigned int gpio3a_sl;
+	unsigned int gpio3b_sl;
+	unsigned int gpio3c_sl;
+	unsigned int gpio3d_sl;
+	unsigned int gpio4a_sl;
+	unsigned int gpio4b_sl;
+	unsigned int gpio4c_sl;
+	unsigned int gpio4d_sl;
+	unsigned int reserved1[(0x0200 - 0x01bc) / 4 - 1];
+	unsigned int gpio1a_ds_0;
+	unsigned int gpio1a_ds_1;
+	unsigned int gpio1a_ds_2;
+	unsigned int gpio1a_ds_3;
+	unsigned int gpio1b_ds_0;
+	unsigned int gpio1b_ds_1;
+	unsigned int gpio1b_ds_2;
+	unsigned int gpio1b_ds_3;
+	unsigned int gpio1c_ds_0;
+	unsigned int gpio1c_ds_1;
+	unsigned int gpio1c_ds_2;
+	unsigned int gpio1c_ds_3;
+	unsigned int gpio1d_ds_0;
+	unsigned int gpio1d_ds_1;
+	unsigned int gpio1d_ds_2;
+	unsigned int gpio1d_ds_3;
+	unsigned int gpio2a_ds_0;
+	unsigned int gpio2a_ds_1;
+	unsigned int gpio2a_ds_2;
+	unsigned int gpio2a_ds_3;
+	unsigned int gpio2b_ds_0;
+	unsigned int gpio2b_ds_1;
+	unsigned int gpio2b_ds_2;
+	unsigned int gpio2b_ds_3;
+	unsigned int gpio2c_ds_0;
+	unsigned int gpio2c_ds_1;
+	unsigned int gpio2c_ds_2;
+	unsigned int gpio2c_ds_3;
+	unsigned int gpio2d_ds_0;
+	unsigned int gpio2d_ds_1;
+	unsigned int gpio2d_ds_2;
+	unsigned int gpio2d_ds_3;
+	unsigned int gpio3a_ds_0;
+	unsigned int gpio3a_ds_1;
+	unsigned int gpio3a_ds_2;
+	unsigned int gpio3a_ds_3;
+	unsigned int gpio3b_ds_0;
+	unsigned int gpio3b_ds_1;
+	unsigned int gpio3b_ds_2;
+	unsigned int gpio3b_ds_3;
+	unsigned int gpio3c_ds_0;
+	unsigned int gpio3c_ds_1;
+	unsigned int gpio3c_ds_2;
+	unsigned int gpio3c_ds_3;
+	unsigned int gpio3d_ds_0;
+	unsigned int gpio3d_ds_1;
+	unsigned int gpio3d_ds_2;
+	unsigned int gpio3d_ds_3;
+	unsigned int gpio4a_ds_0;
+	unsigned int gpio4a_ds_1;
+	unsigned int gpio4a_ds_2;
+	unsigned int gpio4a_ds_3;
+	unsigned int gpio4b_ds_0;
+	unsigned int gpio4b_ds_1;
+	unsigned int gpio4b_ds_2;
+	unsigned int gpio4b_ds_3;
+	unsigned int gpio4c_ds_0;
+	unsigned int gpio4c_ds_1;
+	unsigned int gpio4c_ds_2;
+	unsigned int gpio4c_ds_3;
+	unsigned int gpio4d_ds_0;
+	unsigned int gpio4d_ds_1;
+	unsigned int gpio4d_ds_2;
+	unsigned int gpio4d_ds_3;
+	unsigned int iofunc_sel0;
+	unsigned int iofunc_sel1;
+	unsigned int iofunc_sel2;
+	unsigned int iofunc_sel3;
+	unsigned int iofunc_sel4;
+	unsigned int iofunc_sel5;
+	unsigned int reserved2[(0x0340 - 0x0314) / 4 - 1];
+	unsigned int vi_con0;
+	unsigned int vi_con1;
+	unsigned int vi_status0;
+	unsigned int reserved3[(0x0360 - 0x0348) / 4 - 1];
+	unsigned int vo_con0;
+	unsigned int vo_con1;
+	unsigned int vo_con2;
+	unsigned int vo_con3;
+	unsigned int reserved4[(0x0380 - 0x036c) / 4 - 1];
+	unsigned int mac0_con0;
+	unsigned int mac0_con1;
+	unsigned int mac1_con0;
+	unsigned int mac1_con1;
+	unsigned int reserved5[(0x03a0 - 0x038c) / 4 - 1];
+	unsigned int biu_con0;
+	unsigned int biu_con1;
+	unsigned int biu_con2;
+	unsigned int reserved6[(0x03c0 - 0x03a8) / 4 - 1];
+	unsigned int gic_con0;
+	unsigned int gic_con1;
+	unsigned int gic_con2;
+	unsigned int reserved7[(0x03f0 - 0x03c8) / 4 - 1];
+	unsigned int gpu_con0;
+	unsigned int gpu_con1;
+	unsigned int reserved8[(0x0400 - 0x03f4) / 4 - 1];
+	unsigned int cpu_con0;
+	unsigned int reserved9[(0x0420 - 0x0400) / 4 - 1];
+	unsigned int cpu_status0;
+	unsigned int reserved10[(0x0500 - 0x0420) / 4 - 1];
+	unsigned int soc_con0;
+	unsigned int soc_con1;
+	unsigned int soc_con2;
+	unsigned int soc_con3;
+	unsigned int reserved11[(0x0514 - 0x050c) / 4 - 1];
+	unsigned int soc_con5;
+	unsigned int soc_con6;
+	unsigned int reserved12[(0x0580 - 0x0518) / 4 - 1];
+	unsigned int soc_status0;
+	unsigned int reserved13[(0x05c0 - 0x0580) / 4 - 1];
+	unsigned int ram_con;
+	unsigned int core_ram_con;
+	unsigned int reserved14[(0x0600 - 0x05c4) / 4 - 1];
+	unsigned int tsadc_con;
+	unsigned int reserved15[(0x0610 - 0x0600) / 4 - 1];
+	unsigned int saradc_con;
+	unsigned int reserved16[(0x0700 - 0x0610) / 4 - 1];
+	unsigned int gpupvtpll_con0;
+	unsigned int gpupvtpll_con1;
+	unsigned int gpupvtpll_con2;
+	unsigned int gpupvtpll_con3;
+	unsigned int reserved17[(0x0740 - 0x070c) / 4 - 1];
+	unsigned int npupvtpll_con0;
+	unsigned int npupvtpll_con1;
+	unsigned int npupvtpll_con2;
+	unsigned int npupvtpll_con3;
+	unsigned int reserved18[(0x0800 - 0x074c) / 4 - 1];
+	unsigned int chip_id;
+	unsigned int reserved19[(0x0840 - 0x0800) / 4 - 1];
+	unsigned int gpio1c5_ds;
+	unsigned int gpio2a2_ds;
+	unsigned int gpio2b0_ds;
+	unsigned int gpio3a0_ds;
+	unsigned int gpio3a6_ds;
+	unsigned int gpio4a0_ds;
+	unsigned int reserved20[(0x0900 - 0x0854) / 4 - 1];
+	unsigned int dmac0_con0;
+	unsigned int dmac0_con1;
+	unsigned int dmac0_con2;
+	unsigned int dmac0_con3;
+	unsigned int dmac0_con4;
+	unsigned int dmac0_con5;
+	unsigned int dmac0_con6;
+	unsigned int dmac0_con7;
+	unsigned int dmac0_con8;
+	unsigned int dmac0_con9;
+	unsigned int reserved21[(0x0940 - 0x0924) / 4 - 1];
+	unsigned int dmac1_con0;
+	unsigned int dmac1_con1;
+	unsigned int dmac1_con2;
+	unsigned int dmac1_con3;
+	unsigned int dmac1_con4;
+	unsigned int dmac1_con5;
+	unsigned int dmac1_con6;
+	unsigned int dmac1_con7;
+	unsigned int dmac1_con8;
+	unsigned int dmac1_con9;
+};
+
+check_member(rk3568_grf, dmac1_con9, 0x0964);
+
+struct rk3568_pmugrf {
+	unsigned int pmu_gpio0a_iomux_l;
+	unsigned int pmu_gpio0a_iomux_h;
+	unsigned int pmu_gpio0b_iomux_l;
+	unsigned int pmu_gpio0b_iomux_h;
+	unsigned int pmu_gpio0c_iomux_l;
+	unsigned int pmu_gpio0c_iomux_h;
+	unsigned int pmu_gpio0d_iomux_l;
+	unsigned int reserved0[(0x0020 - 0x0018) / 4 - 1];
+	unsigned int pmu_gpio0a_p;
+	unsigned int pmu_gpio0b_p;
+	unsigned int pmu_gpio0c_p;
+	unsigned int pmu_gpio0d_p;
+	unsigned int pmu_gpio0a_ie;
+	unsigned int pmu_gpio0b_ie;
+	unsigned int pmu_gpio0c_ie;
+	unsigned int pmu_gpio0d_ie;
+	unsigned int pmu_gpio0a_opd;
+	unsigned int pmu_gpio0b_opd;
+	unsigned int pmu_gpio0c_opd;
+	unsigned int pmu_gpio0d_opd;
+	unsigned int pmu_gpio0a_sus;
+	unsigned int pmu_gpio0b_sus;
+	unsigned int pmu_gpio0c_sus;
+	unsigned int pmu_gpio0d_sus;
+	unsigned int pmu_gpio0a_sl;
+	unsigned int pmu_gpio0b_sl;
+	unsigned int pmu_gpio0c_sl;
+	unsigned int pmu_gpio0d_sl;
+	unsigned int pmu_gpio0a_ds_0;
+	unsigned int pmu_gpio0a_ds_1;
+	unsigned int pmu_gpio0a_ds_2;
+	unsigned int pmu_gpio0a_ds_3;
+	unsigned int pmu_gpio0b_ds_0;
+	unsigned int pmu_gpio0b_ds_1;
+	unsigned int pmu_gpio0b_ds_2;
+	unsigned int pmu_gpio0b_ds_3;
+	unsigned int pmu_gpio0c_ds_0;
+	unsigned int pmu_gpio0c_ds_1;
+	unsigned int pmu_gpio0c_ds_2;
+	unsigned int pmu_gpio0c_ds_3;
+	unsigned int pmu_gpio0d_ds_0;
+	unsigned int pmu_gpio0d_ds_1;
+	unsigned int pmu_gpio0d_ds_2;
+	unsigned int pmu_gpio0d_ds_3;
+	unsigned int reserved1[(0x0100 - 0x00ac) / 4 - 1];
+	unsigned int pmu_soc_con0;
+	unsigned int pmu_soc_con1;
+	unsigned int pmu_soc_con2;
+	unsigned int pmu_soc_con3;
+	unsigned int pmu_soc_con4;
+	unsigned int pmu_soc_con5;
+	unsigned int reserved2[(0x0124 - 0x0114) / 4 - 1];
+	unsigned int pmu_io_vsel0;
+	unsigned int pmu_io_vsel1;
+	unsigned int pmu_io_vsel2;
+	unsigned int reserved3[(0x0180 - 0x012c) / 4 - 1];
+	unsigned int pmu_dll_con0;
+	unsigned int reserved4[(0x0200 - 0x0180) / 4 - 1];
+	unsigned int pmu_os_reg0;
+	unsigned int pmu_os_reg1;
+	unsigned int pmu_os_reg2;
+	unsigned int pmu_os_reg3;
+	unsigned int pmu_os_reg4;
+	unsigned int pmu_os_reg5;
+	unsigned int pmu_os_reg6;
+	unsigned int pmu_os_reg7;
+	unsigned int pmu_os_reg8;
+	unsigned int pmu_os_reg9;
+	unsigned int pmu_os_reg10;
+	unsigned int pmu_os_reg11;
+	unsigned int pmu_reset_function_status;
+	unsigned int pmu_reset_function_clr;
+	unsigned int reserved5[(0x0380 - 0x0234) / 4 - 1];
+	unsigned int pmu_sig_detect_con;
+	unsigned int reserved6[(0x0390 - 0x0380) / 4 - 1];
+	unsigned int pmu_sig_detect_status;
+	unsigned int reserved7[(0x03a0 - 0x0390) / 4 - 1];
+	unsigned int pmu_sig_detect_status_clear;
+	unsigned int reserved8[(0x03b0 - 0x03a0) / 4 - 1];
+	unsigned int pmu_sdmmc_det_counter;
+};
+
+check_member(rk3568_pmugrf, pmu_sdmmc_det_counter, 0x03b0);
+
+#endif
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 407bf3f..35bdef2 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -257,6 +257,23 @@ config ROCKCHIP_RK3399
 	  and video codec support. Peripherals include Gigabit Ethernet,
 	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
 
+config ROCKCHIP_RK3568
+	bool "Support Rockchip RK3568"
+	select ARM64
+	select CLK
+	select PINCTRL
+	select RAM
+	select REGMAP
+	select SYSCON
+	select BOARD_LATE_INIT
+	imply ROCKCHIP_COMMON_BOARD
+	help
+	  The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
+	  including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
+	  two video interfaces supporting HDMI and eDP, several DDR3 options
+	  and video codec support. Peripherals include Gigabit Ethernet,
+	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+
 config ROCKCHIP_RV1108
 	bool "Support Rockchip RV1108"
 	select CPU_V7A
@@ -386,5 +403,6 @@ source "arch/arm/mach-rockchip/rk3308/Kconfig"
 source "arch/arm/mach-rockchip/rk3328/Kconfig"
 source "arch/arm/mach-rockchip/rk3368/Kconfig"
 source "arch/arm/mach-rockchip/rk3399/Kconfig"
+source "arch/arm/mach-rockchip/rk3568/Kconfig"
 source "arch/arm/mach-rockchip/rv1108/Kconfig"
 endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 121f23a..00aef0e 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/
 obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
 obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
 obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
+obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
 obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
 
 # Clear out SPL objects, in case this is a TPL build
diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig
new file mode 100644
index 0000000..201c63c
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -0,0 +1,20 @@
+if ROCKCHIP_RK3568
+
+config TARGET_EVB_RK3568
+	bool "RK3568 evaluation board"
+	select BOARD_LATE_INIT
+	help
+	  RK3568 EVB is a evaluation board for Rockchp RK3568.
+
+config ROCKCHIP_BOOT_MODE_REG
+	default 0xfdc20200
+
+config SYS_SOC
+	default "rk3568"
+
+config SYS_MALLOC_F_LEN
+	default 0x2000
+
+source "board/rockchip/evb_rk3568/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rockchip/rk3568/Makefile b/arch/arm/mach-rockchip/rk3568/Makefile
new file mode 100644
index 0000000..28c1f4e
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3568/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2021 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += clk_rk3568.o
+obj-y += rk3568.o
+obj-y += syscon_rk3568.o
diff --git a/arch/arm/mach-rockchip/rk3568/clk_rk3568.c b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c
new file mode 100644
index 0000000..8917edc
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3568.h>
+#include <linux/err.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+	return uclass_get_device_by_driver(UCLASS_CLK,
+			DM_DRIVER_GET(rockchip_rk3568_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+	struct rk3568_clk_priv *priv;
+	struct udevice *dev;
+	int ret;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret)
+		return ERR_PTR(ret);
+
+	priv = dev_get_priv(dev);
+
+	return priv->cru;
+}
+
+static int rockchip_get_pmucruclk(struct udevice **devp)
+{
+	return uclass_get_device_by_driver(UCLASS_CLK,
+			DM_DRIVER_GET(rockchip_rk3568_pmucru), devp);
+}
+
+void *rockchip_get_pmucru(void)
+{
+	struct rk3568_pmuclk_priv *priv;
+	struct udevice *dev;
+	int ret;
+
+	ret = rockchip_get_pmucruclk(&dev);
+	if (ret)
+		return ERR_PTR(ret);
+
+	priv = dev_get_priv(dev);
+
+	return priv->pmucru;
+}
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
new file mode 100644
index 0000000..973b4f9
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/grf_rk3568.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <dt-bindings/clock/rk3568-cru.h>
+
+#define PMUGRF_BASE		0xfdc20000
+#define GRF_BASE		0xfdc60000
+
+/* PMU_GRF_GPIO0D_IOMUX_L */
+enum {
+	GPIO0D1_SHIFT		= 4,
+	GPIO0D1_MASK		= GENMASK(6, 4),
+	GPIO0D1_GPIO		= 0,
+	GPIO0D1_UART2_TXM0,
+
+	GPIO0D0_SHIFT		= 0,
+	GPIO0D0_MASK		= GENMASK(2, 0),
+	GPIO0D0_GPIO		= 0,
+	GPIO0D0_UART2_RXM0,
+};
+
+/* GRF_IOFUNC_SEL3 */
+enum {
+	UART2_IO_SEL_SHIFT	= 10,
+	UART2_IO_SEL_MASK	= GENMASK(11, 10),
+	UART2_IO_SEL_M0		= 0,
+};
+
+static struct mm_region rk3568_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0xf0000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xf0000000UL,
+		.phys = 0xf0000000UL,
+		.size = 0x10000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x300000000,
+		.phys = 0x300000000,
+		.size = 0x0c0c00000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = rk3568_mem_map;
+
+void board_debug_uart_init(void)
+{
+	static struct rk3568_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
+	static struct rk3568_grf * const grf = (void *)GRF_BASE;
+
+	/* UART2 M0 */
+	rk_clrsetreg(&grf->iofunc_sel3, UART2_IO_SEL_MASK,
+		     UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
+
+	/* Switch iomux */
+	rk_clrsetreg(&pmugrf->pmu_gpio0d_iomux_l,
+		     GPIO0D1_MASK | GPIO0D0_MASK,
+		     GPIO0D1_UART2_TXM0 << GPIO0D1_SHIFT |
+		     GPIO0D0_UART2_RXM0 << GPIO0D0_SHIFT);
+}
+
+int arch_cpu_init(void)
+{
+	return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c
new file mode 100644
index 0000000..20adfd1
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rk3568_syscon_ids[] = {
+	{ .compatible = "rockchip,rk3568-grf", .data = ROCKCHIP_SYSCON_GRF },
+	{ .compatible = "rockchip,rk3568-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
+	{ }
+};
+
+U_BOOT_DRIVER(syscon_rk3568) = {
+	.name = "rk3568_syscon",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3568_syscon_ids,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+	.bind = dm_scan_fdt_dev,
+#endif
+};
diff --git a/board/rockchip/evb_rk3568/Kconfig b/board/rockchip/evb_rk3568/Kconfig
new file mode 100644
index 0000000..f3d3a7e
--- /dev/null
+++ b/board/rockchip/evb_rk3568/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3568
+
+config SYS_BOARD
+	default "evb_rk3568"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_rk3568"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS
new file mode 100644
index 0000000..b6ea498
--- /dev/null
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3568
+M:      Joseph Chen <chenjh@rock-chips.com>
+S:      Maintained
+F:      board/rockchip/evb_rk3568
+F:      include/configs/evb_rk3568.h
+F:      configs/evb-rk3568_defconfig
diff --git a/board/rockchip/evb_rk3568/Makefile b/board/rockchip/evb_rk3568/Makefile
new file mode 100644
index 0000000..cbda95f
--- /dev/null
+++ b/board/rockchip/evb_rk3568/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2021 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb_rk3568.o
diff --git a/board/rockchip/evb_rk3568/evb_rk3568.c b/board/rockchip/evb_rk3568/evb_rk3568.c
new file mode 100644
index 0000000..c2fdf95
--- /dev/null
+++ b/board/rockchip/evb_rk3568/evb_rk3568.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
new file mode 100644
index 0000000..03511d7
--- /dev/null
+++ b/configs/evb-rk3568_defconfig
@@ -0,0 +1,35 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_TARGET_EVB_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig
index 63074a4..ce6b492 100644
--- a/configs/khadas-edge-captain-rk3399_defconfig
+++ b/configs/khadas-edge-captain-rk3399_defconfig
@@ -50,6 +50,8 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig
index cf5a6da..e52963e 100644
--- a/configs/khadas-edge-rk3399_defconfig
+++ b/configs/khadas-edge-rk3399_defconfig
@@ -49,6 +49,8 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig
index 197a6f6..5f61df8 100644
--- a/configs/khadas-edge-v-rk3399_defconfig
+++ b/configs/khadas-edge-v-rk3399_defconfig
@@ -50,6 +50,8 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 4cfcf83..913f611 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -14,4 +14,5 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
 obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
new file mode 100644
index 0000000..553c6c0
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -0,0 +1,2959 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#include <common.h>
+#include <bitfield.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/cru_rk3568.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/io.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rk3568-cru.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+struct rk3568_clk_plat {
+	struct dtd_rockchip_rk3568_cru dtd;
+};
+
+struct rk3568_pmuclk_plat {
+	struct dtd_rockchip_rk3568_pmucru dtd;
+};
+#endif
+
+#define RK3568_CPUCLK_RATE(_rate, _aclk_div, _pclk_div)		\
+{								\
+	.rate	= _rate##U,					\
+	.aclk_div = _aclk_div,					\
+	.pclk_div = _pclk_div,					\
+}
+
+#define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
+
+static struct rockchip_cpu_rate_table rk3568_cpu_rates[] = {
+	RK3568_CPUCLK_RATE(1416000000, 1, 5),
+	RK3568_CPUCLK_RATE(1296000000, 1, 5),
+	RK3568_CPUCLK_RATE(1200000000, 1, 3),
+	RK3568_CPUCLK_RATE(1104000000, 1, 3),
+	RK3568_CPUCLK_RATE(1008000000, 1, 3),
+	RK3568_CPUCLK_RATE(912000000, 1, 3),
+	RK3568_CPUCLK_RATE(816000000, 1, 3),
+	RK3568_CPUCLK_RATE(600000000, 1, 1),
+	RK3568_CPUCLK_RATE(408000000, 1, 1),
+	{ /* sentinel */ },
+};
+
+static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
+	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+	RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
+	RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
+	RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
+	RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
+	RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
+	RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
+	RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
+	RK3036_PLL_RATE(400000000, 1, 100, 6, 1, 1, 0),
+	RK3036_PLL_RATE(200000000, 1, 100, 6, 2, 1, 0),
+	RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
+	{ /* sentinel */ },
+};
+
+static struct rockchip_pll_clock rk3568_pll_clks[] = {
+	[APLL] = PLL(pll_rk3328, PLL_APLL, RK3568_PLL_CON(0),
+		     RK3568_MODE_CON, 0, 10, 0, rk3568_pll_rates),
+	[DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3568_PLL_CON(8),
+		     RK3568_MODE_CON, 2, 10, 0, NULL),
+	[CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3568_PLL_CON(24),
+		     RK3568_MODE_CON, 4, 10, 0, rk3568_pll_rates),
+	[GPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PLL_CON(16),
+		     RK3568_MODE_CON, 6, 10, 0, rk3568_pll_rates),
+	[NPLL] = PLL(pll_rk3328, PLL_NPLL, RK3568_PLL_CON(32),
+		     RK3568_MODE_CON, 10, 10, 0, rk3568_pll_rates),
+	[VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3568_PLL_CON(40),
+		     RK3568_MODE_CON, 12, 10, 0, rk3568_pll_rates),
+	[PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3568_PMU_PLL_CON(0),
+		     RK3568_PMU_MODE, 0, 10, 0, rk3568_pll_rates),
+	[HPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PMU_PLL_CON(16),
+		     RK3568_PMU_MODE, 2, 10, 0, rk3568_pll_rates),
+};
+
+#ifndef CONFIG_SPL_BUILD
+static ulong
+rk3568_pmu_pll_set_rate(struct rk3568_clk_priv *priv,
+			ulong pll_id, ulong rate)
+{
+	struct udevice *pmucru_dev;
+	struct rk3568_pmuclk_priv *pmu_priv;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_CLK,
+					  DM_DRIVER_GET(rockchip_rk3568_pmucru),
+					  &pmucru_dev);
+	if (ret) {
+		printf("%s: could not find pmucru device\n", __func__);
+		return ret;
+	}
+	pmu_priv = dev_get_priv(pmucru_dev);
+
+	rockchip_pll_set_rate(&rk3568_pll_clks[pll_id],
+			      pmu_priv->pmucru, pll_id, rate);
+
+	return 0;
+}
+#endif
+
+static ulong rk3568_pmu_pll_get_rate(struct rk3568_clk_priv *priv,
+				     ulong pll_id)
+{
+	struct udevice *pmucru_dev;
+	struct rk3568_pmuclk_priv *pmu_priv;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_CLK,
+					  DM_DRIVER_GET(rockchip_rk3568_pmucru),
+					  &pmucru_dev);
+	if (ret) {
+		printf("%s: could not find pmucru device\n", __func__);
+		return ret;
+	}
+	pmu_priv = dev_get_priv(pmucru_dev);
+
+	return rockchip_pll_get_rate(&rk3568_pll_clks[pll_id],
+				      pmu_priv->pmucru, pll_id);
+}
+
+/*
+ *
+ * rational_best_approximation(31415, 10000,
+ *		(1 << 8) - 1, (1 << 5) - 1, &n, &d);
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+static void rational_best_approximation(unsigned long given_numerator,
+					unsigned long given_denominator,
+					unsigned long max_numerator,
+					unsigned long max_denominator,
+					unsigned long *best_numerator,
+					unsigned long *best_denominator)
+{
+	unsigned long n, d, n0, d0, n1, d1;
+
+	n = given_numerator;
+	d = given_denominator;
+	n0 = 0;
+	d1 = 0;
+	n1 = 1;
+	d0 = 1;
+	for (;;) {
+		unsigned long t, a;
+
+		if (n1 > max_numerator || d1 > max_denominator) {
+			n1 = n0;
+			d1 = d0;
+			break;
+		}
+		if (d == 0)
+			break;
+		t = d;
+		a = n / d;
+		d = n % d;
+		n = t;
+		t = n0 + a * n1;
+		n0 = n1;
+		n1 = t;
+		t = d0 + a * d1;
+		d0 = d1;
+		d1 = t;
+	}
+	*best_numerator = n1;
+	*best_denominator = d1;
+}
+
+static ulong rk3568_rtc32k_get_pmuclk(struct rk3568_pmuclk_priv *priv)
+{
+	struct rk3568_pmucru *pmucru = priv->pmucru;
+	unsigned long m, n;
+	u32 fracdiv;
+
+	fracdiv = readl(&pmucru->pmu_clksel_con[1]);
+	m = fracdiv & RTC32K_FRAC_NUMERATOR_MASK;
+	m >>= RTC32K_FRAC_NUMERATOR_SHIFT;
+	n = fracdiv & RTC32K_FRAC_DENOMINATOR_MASK;
+	n >>= RTC32K_FRAC_DENOMINATOR_SHIFT;
+
+	return OSC_HZ * m / n;
+}
+
+static ulong rk3568_rtc32k_set_pmuclk(struct rk3568_pmuclk_priv *priv,
+				      ulong rate)
+{
+	struct rk3568_pmucru *pmucru = priv->pmucru;
+	unsigned long m, n, val;
+
+	rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK,
+		     RTC32K_SEL_OSC0_DIV32K << RTC32K_SEL_SHIFT);
+
+	rational_best_approximation(rate, OSC_HZ,
+				    GENMASK(16 - 1, 0),
+				    GENMASK(16 - 1, 0),
+				    &m, &n);
+	val = m << RTC32K_FRAC_NUMERATOR_SHIFT | n;
+	writel(val, &pmucru->pmu_clksel_con[1]);
+
+	return rk3568_rtc32k_get_pmuclk(priv);
+}
+
+static ulong rk3568_i2c_get_pmuclk(struct rk3568_pmuclk_priv *priv,
+				   ulong clk_id)
+{
+	struct rk3568_pmucru *pmucru = priv->pmucru;
+	u32 div, con;
+
+	switch (clk_id) {
+	case CLK_I2C0:
+		con = readl(&pmucru->pmu_clksel_con[3]);
+		div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return DIV_TO_RATE(priv->ppll_hz, div);
+}
+
+static ulong rk3568_i2c_set_pmuclk(struct rk3568_pmuclk_priv *priv,
+				   ulong clk_id, ulong rate)
+{
+	struct rk3568_pmucru *pmucru = priv->pmucru;
+	int src_clk_div;
+
+	src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate);
+	assert(src_clk_div - 1 <= 127);
+
+	switch (clk_id) {
+	case CLK_I2C0:
+		rk_clrsetreg(&pmucru->pmu_clksel_con[3], CLK_I2C0_DIV_MASK,
+			     (src_clk_div - 1) << CLK_I2C0_DIV_SHIFT);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rk3568_i2c_get_pmuclk(priv, clk_id);
+}
+
+static ulong rk3568_pwm_get_pmuclk(struct rk3568_pmuclk_priv *priv,
+				   ulong clk_id)
+{
+	struct rk3568_pmucru *pmucru = priv->pmucru;
+	u32 div, sel, con, parent;
+
+	switch (clk_id) {
+	case CLK_PWM0:
+		con = readl(&pmucru->pmu_clksel_con[6]);
+		sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT;
+		div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT;
+		if (sel == CLK_PWM0_SEL_XIN24M)
+			parent = OSC_HZ;
+		else
+			parent = priv->ppll_hz;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3568_pwm_set_pmuclk(struct rk3568_pmuclk_priv *priv,
+				   ulong clk_id, ulong rate)
+{
+	struct rk3568_pmucru *pmucru = priv->pmucru;
+	int src_clk_div;
+
+	switch (clk_id) {
+	case CLK_PWM0:
+		if (rate == OSC_HZ) {
+			rk_clrsetreg(&pmucru->pmu_clksel_con[6],
+				     CLK_PWM0_SEL_MASK | CLK_PWM0_DIV_MASK,
+				     (CLK_PWM0_SEL_XIN24M <<
+				      CLK_PWM0_SEL_SHIFT) |
+				     0 << CLK_PWM0_SEL_SHIFT);
+		} else {
+			src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate);
+			assert(src_clk_div - 1 <= 127);
+			rk_clrsetreg(&pmucru->pmu_clksel_con[6],
+				     CLK_PWM0_DIV_MASK | CLK_PWM0_DIV_MASK,
+				     (CLK_PWM0_SEL_PPLL << CLK_PWM0_SEL_SHIFT) |
+				     (src_clk_div - 1) << CLK_PWM0_DIV_SHIFT);
+		}
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rk3568_pwm_get_pmuclk(priv, clk_id);
+}
+
+static ulong rk3568_pmu_get_pmuclk(struct rk3568_pmuclk_priv *priv)
+{
+	struct rk3568_pmucru *pmucru = priv->pmucru;
+	u32 div, con, sel, parent;
+
+	con = readl(&pmucru->pmu_clksel_con[2]);
+	sel = (con & PCLK_PDPMU_SEL_MASK) >> PCLK_PDPMU_SEL_SHIFT;
+	div = (con & PCLK_PDPMU_DIV_MASK) >> PCLK_PDPMU_DIV_SHIFT;
+	if (sel)
+		parent = GPLL_HZ;
+	else
+		parent = priv->ppll_hz;
+
+	return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3568_pmu_set_pmuclk(struct rk3568_pmuclk_priv *priv,
+				   ulong rate)
+{
+	struct rk3568_pmucru *pmucru = priv->pmucru;
+	int src_clk_div;
+
+	src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate);
+	assert(src_clk_div - 1 <= 31);
+
+	rk_clrsetreg(&pmucru->pmu_clksel_con[2],
+		     PCLK_PDPMU_DIV_MASK | PCLK_PDPMU_SEL_MASK,
+		     (PCLK_PDPMU_SEL_PPLL << PCLK_PDPMU_SEL_SHIFT) |
+		     ((src_clk_div - 1) << PCLK_PDPMU_DIV_SHIFT));
+
+	return rk3568_pmu_get_pmuclk(priv);
+}
+
+static ulong rk3568_pmuclk_get_rate(struct clk *clk)
+{
+	struct rk3568_pmuclk_priv *priv = dev_get_priv(clk->dev);
+	ulong rate = 0;
+
+	if (!priv->ppll_hz) {
+		printf("%s ppll=%lu\n", __func__, priv->ppll_hz);
+		return -ENOENT;
+	}
+
+	debug("%s %ld\n", __func__, clk->id);
+	switch (clk->id) {
+	case PLL_PPLL:
+		rate = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL],
+					     priv->pmucru, PPLL);
+		break;
+	case PLL_HPLL:
+		rate = rockchip_pll_get_rate(&rk3568_pll_clks[HPLL],
+					     priv->pmucru, HPLL);
+		break;
+	case CLK_RTC_32K:
+	case CLK_RTC32K_FRAC:
+		rate = rk3568_rtc32k_get_pmuclk(priv);
+		break;
+	case CLK_I2C0:
+		rate = rk3568_i2c_get_pmuclk(priv, clk->id);
+		break;
+	case CLK_PWM0:
+		rate = rk3568_pwm_get_pmuclk(priv, clk->id);
+		break;
+	case PCLK_PMU:
+		rate = rk3568_pmu_get_pmuclk(priv);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rate;
+}
+
+static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate)
+{
+	struct rk3568_pmuclk_priv *priv = dev_get_priv(clk->dev);
+	ulong ret = 0;
+
+	if (!priv->ppll_hz) {
+		printf("%s ppll=%lu\n", __func__, priv->ppll_hz);
+		return -ENOENT;
+	}
+
+	debug("%s %ld %ld\n", __func__, clk->id, rate);
+	switch (clk->id) {
+	case PLL_PPLL:
+		ret = rockchip_pll_set_rate(&rk3568_pll_clks[PPLL],
+					    priv->pmucru, PPLL, rate);
+		priv->ppll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL],
+						      priv->pmucru, PPLL);
+		break;
+	case PLL_HPLL:
+		ret = rockchip_pll_set_rate(&rk3568_pll_clks[HPLL],
+					    priv->pmucru, HPLL, rate);
+		priv->hpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[HPLL],
+						      priv->pmucru, HPLL);
+		break;
+	case CLK_RTC_32K:
+	case CLK_RTC32K_FRAC:
+		ret = rk3568_rtc32k_set_pmuclk(priv, rate);
+		break;
+	case CLK_I2C0:
+		ret = rk3568_i2c_set_pmuclk(priv, clk->id, rate);
+		break;
+	case CLK_PWM0:
+		ret = rk3568_pwm_set_pmuclk(priv, clk->id, rate);
+		break;
+	case PCLK_PMU:
+		ret = rk3568_pmu_set_pmuclk(priv, rate);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return ret;
+}
+
+static int rk3568_rtc32k_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct rk3568_pmuclk_priv *priv = dev_get_priv(clk->dev);
+	struct rk3568_pmucru *pmucru = priv->pmucru;
+
+	if (parent->id == CLK_RTC32K_FRAC)
+		rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK,
+			     RTC32K_SEL_OSC0_DIV32K << RTC32K_SEL_SHIFT);
+	else
+		rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK,
+			     RTC32K_SEL_OSC1_32K << RTC32K_SEL_SHIFT);
+
+	return 0;
+}
+
+static int rk3568_pmuclk_set_parent(struct clk *clk, struct clk *parent)
+{
+	switch (clk->id) {
+	case CLK_RTC_32K:
+		return rk3568_rtc32k_set_parent(clk, parent);
+	default:
+		return -ENOENT;
+	}
+}
+
+static struct clk_ops rk3568_pmuclk_ops = {
+	.get_rate = rk3568_pmuclk_get_rate,
+	.set_rate = rk3568_pmuclk_set_rate,
+	.set_parent = rk3568_pmuclk_set_parent,
+};
+
+static int rk3568_pmuclk_probe(struct udevice *dev)
+{
+	struct rk3568_pmuclk_priv *priv = dev_get_priv(dev);
+	int ret = 0;
+
+	if (priv->ppll_hz != PPLL_HZ) {
+		ret = rockchip_pll_set_rate(&rk3568_pll_clks[PPLL],
+					    priv->pmucru,
+					    PPLL, PPLL_HZ);
+		if (!ret)
+			priv->ppll_hz = PPLL_HZ;
+	}
+
+	/* Ungate PCIe30phy refclk_m and refclk_n */
+	rk_clrsetreg(&priv->pmucru->pmu_clkgate_con[2], 0x3 << 13, 0 << 13);
+	return 0;
+}
+
+static int rk3568_pmuclk_ofdata_to_platdata(struct udevice *dev)
+{
+	struct rk3568_pmuclk_priv *priv = dev_get_priv(dev);
+
+	priv->pmucru = dev_read_addr_ptr(dev);
+
+	return 0;
+}
+
+static int rk3568_pmuclk_bind(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
+	int ret = 0;
+
+	ret = offsetof(struct rk3568_pmucru, pmu_softrst_con[0]);
+	ret = rockchip_reset_bind(dev, ret, 1);
+	if (ret)
+		debug("Warning: pmucru software reset driver bind faile\n");
+#endif
+
+	return 0;
+}
+
+static const struct udevice_id rk3568_pmuclk_ids[] = {
+	{ .compatible = "rockchip,rk3568-pmucru" },
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_rk3568_pmucru) = {
+	.name		= "rockchip_rk3568_pmucru",
+	.id		= UCLASS_CLK,
+	.of_match	= rk3568_pmuclk_ids,
+	.priv_auto = sizeof(struct rk3568_pmuclk_priv),
+	.of_to_plat = rk3568_pmuclk_ofdata_to_platdata,
+	.ops		= &rk3568_pmuclk_ops,
+	.bind		= rk3568_pmuclk_bind,
+	.probe		= rk3568_pmuclk_probe,
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	.plat_auto	= sizeof(struct rk3568_pmuclk_plat),
+#endif
+
+};
+
+static int rk3568_armclk_set_clk(struct rk3568_clk_priv *priv, ulong hz)
+{
+	struct rk3568_cru *cru = priv->cru;
+	const struct rockchip_cpu_rate_table *rate;
+	ulong old_rate;
+
+	rate = rockchip_get_cpu_settings(rk3568_cpu_rates, hz);
+	if (!rate) {
+		printf("%s unsupported rate\n", __func__);
+		return -EINVAL;
+	}
+
+	rk_clrsetreg(&cru->clksel_con[0],
+		     CLK_CORE_PRE_SEL_MASK,
+		     (CLK_CORE_PRE_SEL_SRC << CLK_CORE_PRE_SEL_SHIFT));
+	rk_clrsetreg(&cru->clksel_con[2],
+		     SCLK_CORE_PRE_SEL_MASK |
+		     SCLK_CORE_SRC_SEL_MASK |
+		     SCLK_CORE_SRC_DIV_MASK,
+		     (SCLK_CORE_PRE_SEL_SRC <<
+		      SCLK_CORE_PRE_SEL_SHIFT) |
+		     (SCLK_CORE_SRC_SEL_APLL <<
+		      SCLK_CORE_SRC_SEL_SHIFT) |
+		     (1 << SCLK_CORE_SRC_DIV_SHIFT));
+
+	/*
+	 * set up dependent divisors for DBG and ACLK clocks.
+	 */
+	old_rate = rockchip_pll_get_rate(&rk3568_pll_clks[APLL],
+					 priv->cru, APLL);
+	if (old_rate > hz) {
+		if (rockchip_pll_set_rate(&rk3568_pll_clks[APLL],
+					  priv->cru, APLL, hz))
+			return -EINVAL;
+		rk_clrsetreg(&cru->clksel_con[3],
+			     GICCLK_CORE_DIV_MASK | ATCLK_CORE_DIV_MASK,
+			     rate->pclk_div << GICCLK_CORE_DIV_SHIFT |
+			     rate->pclk_div << ATCLK_CORE_DIV_SHIFT);
+		rk_clrsetreg(&cru->clksel_con[4],
+			     PERIPHCLK_CORE_PRE_DIV_MASK |
+			     PCLK_CORE_PRE_DIV_MASK,
+			     rate->pclk_div << PCLK_CORE_PRE_DIV_SHIFT |
+			     rate->pclk_div << PERIPHCLK_CORE_PRE_DIV_SHIFT);
+		rk_clrsetreg(&cru->clksel_con[5],
+			     ACLK_CORE_NDFT_DIV_MASK,
+			     rate->aclk_div << ACLK_CORE_NDFT_DIV_SHIFT);
+	} else if (old_rate < hz) {
+		rk_clrsetreg(&cru->clksel_con[3],
+			     GICCLK_CORE_DIV_MASK | ATCLK_CORE_DIV_MASK,
+			     rate->pclk_div << GICCLK_CORE_DIV_SHIFT |
+			     rate->pclk_div << ATCLK_CORE_DIV_SHIFT);
+		rk_clrsetreg(&cru->clksel_con[4],
+			     PERIPHCLK_CORE_PRE_DIV_MASK |
+			     PCLK_CORE_PRE_DIV_MASK,
+			     rate->pclk_div << PCLK_CORE_PRE_DIV_SHIFT |
+			     rate->pclk_div << PERIPHCLK_CORE_PRE_DIV_SHIFT);
+		rk_clrsetreg(&cru->clksel_con[5],
+			     ACLK_CORE_NDFT_DIV_MASK,
+			     rate->aclk_div << ACLK_CORE_NDFT_DIV_SHIFT);
+		if (rockchip_pll_set_rate(&rk3568_pll_clks[APLL],
+					  priv->cru, APLL, hz))
+			return -EINVAL;
+	}
+
+	return 0;
+}
+
+static ulong rk3568_cpll_div_get_rate(struct rk3568_clk_priv *priv,
+				      ulong clk_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int div, mask, shift, con;
+
+	switch (clk_id) {
+	case CPLL_500M:
+		con = 78;
+		mask = CPLL_500M_DIV_MASK;
+		shift = CPLL_500M_DIV_SHIFT;
+		break;
+	case CPLL_333M:
+		con = 79;
+		mask = CPLL_333M_DIV_MASK;
+		shift = CPLL_333M_DIV_SHIFT;
+		break;
+	case CPLL_250M:
+		con = 79;
+		mask = CPLL_250M_DIV_MASK;
+		shift = CPLL_250M_DIV_SHIFT;
+		break;
+	case CPLL_125M:
+		con = 80;
+		mask = CPLL_125M_DIV_MASK;
+		shift = CPLL_125M_DIV_SHIFT;
+		break;
+	case CPLL_100M:
+		con = 82;
+		mask = CPLL_100M_DIV_MASK;
+		shift = CPLL_100M_DIV_SHIFT;
+		break;
+	case CPLL_62P5M:
+		con = 80;
+		mask = CPLL_62P5M_DIV_MASK;
+		shift = CPLL_62P5M_DIV_SHIFT;
+		break;
+	case CPLL_50M:
+		con = 81;
+		mask = CPLL_50M_DIV_MASK;
+		shift = CPLL_50M_DIV_SHIFT;
+		break;
+	case CPLL_25M:
+		con = 81;
+		mask = CPLL_25M_DIV_MASK;
+		shift = CPLL_25M_DIV_SHIFT;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	div = (readl(&cru->clksel_con[con]) & mask) >> shift;
+	return DIV_TO_RATE(priv->cpll_hz, div);
+}
+
+static ulong rk3568_cpll_div_set_rate(struct rk3568_clk_priv *priv,
+				      ulong clk_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int div, mask, shift, con;
+
+	switch (clk_id) {
+	case CPLL_500M:
+		con = 78;
+		mask = CPLL_500M_DIV_MASK;
+		shift = CPLL_500M_DIV_SHIFT;
+		break;
+	case CPLL_333M:
+		con = 79;
+		mask = CPLL_333M_DIV_MASK;
+		shift = CPLL_333M_DIV_SHIFT;
+		break;
+	case CPLL_250M:
+		con = 79;
+		mask = CPLL_250M_DIV_MASK;
+		shift = CPLL_250M_DIV_SHIFT;
+		break;
+	case CPLL_125M:
+		con = 80;
+		mask = CPLL_125M_DIV_MASK;
+		shift = CPLL_125M_DIV_SHIFT;
+		break;
+	case CPLL_100M:
+		con = 82;
+		mask = CPLL_100M_DIV_MASK;
+		shift = CPLL_100M_DIV_SHIFT;
+		break;
+	case CPLL_62P5M:
+		con = 80;
+		mask = CPLL_62P5M_DIV_MASK;
+		shift = CPLL_62P5M_DIV_SHIFT;
+		break;
+	case CPLL_50M:
+		con = 81;
+		mask = CPLL_50M_DIV_MASK;
+		shift = CPLL_50M_DIV_SHIFT;
+		break;
+	case CPLL_25M:
+		con = 81;
+		mask = CPLL_25M_DIV_MASK;
+		shift = CPLL_25M_DIV_SHIFT;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	div = DIV_ROUND_UP(priv->cpll_hz, rate);
+	assert(div - 1 <= 31);
+	rk_clrsetreg(&cru->clksel_con[con],
+		     mask, (div - 1) << shift);
+	return rk3568_cpll_div_get_rate(priv, clk_id);
+}
+
+static ulong rk3568_bus_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 con, sel, rate;
+
+	switch (clk_id) {
+	case ACLK_BUS:
+		con = readl(&cru->clksel_con[50]);
+		sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT;
+		if (sel == ACLK_BUS_SEL_200M)
+			rate = 200 * MHz;
+		else if (sel == ACLK_BUS_SEL_150M)
+			rate = 150 * MHz;
+		else if (sel == ACLK_BUS_SEL_100M)
+			rate = 100 * MHz;
+		else
+			rate = OSC_HZ;
+		break;
+	case PCLK_BUS:
+	case PCLK_WDT_NS:
+		con = readl(&cru->clksel_con[50]);
+		sel = (con & PCLK_BUS_SEL_MASK) >> PCLK_BUS_SEL_SHIFT;
+		if (sel == PCLK_BUS_SEL_100M)
+			rate = 100 * MHz;
+		else if (sel == PCLK_BUS_SEL_75M)
+			rate = 75 * MHz;
+		else if (sel == PCLK_BUS_SEL_50M)
+			rate = 50 * MHz;
+		else
+			rate = OSC_HZ;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rate;
+}
+
+static ulong rk3568_bus_set_clk(struct rk3568_clk_priv *priv,
+				ulong clk_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk;
+
+	switch (clk_id) {
+	case ACLK_BUS:
+		if (rate == 200 * MHz)
+			src_clk = ACLK_BUS_SEL_200M;
+		else if (rate == 150 * MHz)
+			src_clk = ACLK_BUS_SEL_150M;
+		else if (rate == 100 * MHz)
+			src_clk = ACLK_BUS_SEL_100M;
+		else
+			src_clk = ACLK_BUS_SEL_24M;
+		rk_clrsetreg(&cru->clksel_con[50],
+			     ACLK_BUS_SEL_MASK,
+			     src_clk << ACLK_BUS_SEL_SHIFT);
+		break;
+	case PCLK_BUS:
+	case PCLK_WDT_NS:
+		if (rate == 100 * MHz)
+			src_clk = PCLK_BUS_SEL_100M;
+		else if (rate == 75 * MHz)
+			src_clk = PCLK_BUS_SEL_75M;
+		else if (rate == 50 * MHz)
+			src_clk = PCLK_BUS_SEL_50M;
+		else
+			src_clk = PCLK_BUS_SEL_24M;
+		rk_clrsetreg(&cru->clksel_con[50],
+			     PCLK_BUS_SEL_MASK,
+			     src_clk << PCLK_BUS_SEL_SHIFT);
+		break;
+
+	default:
+		printf("do not support this bus freq\n");
+		return -EINVAL;
+	}
+
+	return rk3568_bus_get_clk(priv, clk_id);
+}
+
+static ulong rk3568_perimid_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 con, sel, rate;
+
+	switch (clk_id) {
+	case ACLK_PERIMID:
+		con = readl(&cru->clksel_con[10]);
+		sel = (con & ACLK_PERIMID_SEL_MASK) >> ACLK_PERIMID_SEL_SHIFT;
+		if (sel == ACLK_PERIMID_SEL_300M)
+			rate = 300 * MHz;
+		else if (sel == ACLK_PERIMID_SEL_200M)
+			rate = 200 * MHz;
+		else if (sel == ACLK_PERIMID_SEL_100M)
+			rate = 100 * MHz;
+		else
+			rate = OSC_HZ;
+		break;
+	case HCLK_PERIMID:
+		con = readl(&cru->clksel_con[10]);
+		sel = (con & HCLK_PERIMID_SEL_MASK) >> HCLK_PERIMID_SEL_SHIFT;
+		if (sel == HCLK_PERIMID_SEL_150M)
+			rate = 150 * MHz;
+		else if (sel == HCLK_PERIMID_SEL_100M)
+			rate = 100 * MHz;
+		else if (sel == HCLK_PERIMID_SEL_75M)
+			rate = 75 * MHz;
+		else
+			rate = OSC_HZ;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rate;
+}
+
+static ulong rk3568_perimid_set_clk(struct rk3568_clk_priv *priv,
+				    ulong clk_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk;
+
+	switch (clk_id) {
+	case ACLK_PERIMID:
+		if (rate == 300 * MHz)
+			src_clk = ACLK_PERIMID_SEL_300M;
+		else if (rate == 200 * MHz)
+			src_clk = ACLK_PERIMID_SEL_200M;
+		else if (rate == 100 * MHz)
+			src_clk = ACLK_PERIMID_SEL_100M;
+		else
+			src_clk = ACLK_PERIMID_SEL_24M;
+		rk_clrsetreg(&cru->clksel_con[10],
+			     ACLK_PERIMID_SEL_MASK,
+			     src_clk << ACLK_PERIMID_SEL_SHIFT);
+		break;
+	case HCLK_PERIMID:
+		if (rate == 150 * MHz)
+			src_clk = HCLK_PERIMID_SEL_150M;
+		else if (rate == 100 * MHz)
+			src_clk = HCLK_PERIMID_SEL_100M;
+		else if (rate == 75 * MHz)
+			src_clk = HCLK_PERIMID_SEL_75M;
+		else
+			src_clk = HCLK_PERIMID_SEL_24M;
+		rk_clrsetreg(&cru->clksel_con[10],
+			     HCLK_PERIMID_SEL_MASK,
+			     src_clk << HCLK_PERIMID_SEL_SHIFT);
+		break;
+
+	default:
+		printf("do not support this permid freq\n");
+		return -EINVAL;
+	}
+
+	return rk3568_perimid_get_clk(priv, clk_id);
+}
+
+static ulong rk3568_top_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 con, sel, rate;
+
+	switch (clk_id) {
+	case ACLK_TOP_HIGH:
+		con = readl(&cru->clksel_con[73]);
+		sel = (con & ACLK_TOP_HIGH_SEL_MASK) >> ACLK_TOP_HIGH_SEL_SHIFT;
+		if (sel == ACLK_TOP_HIGH_SEL_500M)
+			rate = 500 * MHz;
+		else if (sel == ACLK_TOP_HIGH_SEL_400M)
+			rate = 400 * MHz;
+		else if (sel == ACLK_TOP_HIGH_SEL_300M)
+			rate = 300 * MHz;
+		else
+			rate = OSC_HZ;
+		break;
+	case ACLK_TOP_LOW:
+		con = readl(&cru->clksel_con[73]);
+		sel = (con & ACLK_TOP_LOW_SEL_MASK) >> ACLK_TOP_LOW_SEL_SHIFT;
+		if (sel == ACLK_TOP_LOW_SEL_400M)
+			rate = 400 * MHz;
+		else if (sel == ACLK_TOP_LOW_SEL_300M)
+			rate = 300 * MHz;
+		else if (sel == ACLK_TOP_LOW_SEL_200M)
+			rate = 200 * MHz;
+		else
+			rate = OSC_HZ;
+		break;
+	case HCLK_TOP:
+		con = readl(&cru->clksel_con[73]);
+		sel = (con & HCLK_TOP_SEL_MASK) >> HCLK_TOP_SEL_SHIFT;
+		if (sel == HCLK_TOP_SEL_150M)
+			rate = 150 * MHz;
+		else if (sel == HCLK_TOP_SEL_100M)
+			rate = 100 * MHz;
+		else if (sel == HCLK_TOP_SEL_75M)
+			rate = 75 * MHz;
+		else
+			rate = OSC_HZ;
+		break;
+	case PCLK_TOP:
+		con = readl(&cru->clksel_con[73]);
+		sel = (con & PCLK_TOP_SEL_MASK) >> PCLK_TOP_SEL_SHIFT;
+		if (sel == PCLK_TOP_SEL_100M)
+			rate = 100 * MHz;
+		else if (sel == PCLK_TOP_SEL_75M)
+			rate = 75 * MHz;
+		else if (sel == PCLK_TOP_SEL_50M)
+			rate = 50 * MHz;
+		else
+			rate = OSC_HZ;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rate;
+}
+
+static ulong rk3568_top_set_clk(struct rk3568_clk_priv *priv,
+				ulong clk_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk;
+
+	switch (clk_id) {
+	case ACLK_TOP_HIGH:
+		if (rate == 500 * MHz)
+			src_clk = ACLK_TOP_HIGH_SEL_500M;
+		else if (rate == 400 * MHz)
+			src_clk = ACLK_TOP_HIGH_SEL_400M;
+		else if (rate == 300 * MHz)
+			src_clk = ACLK_TOP_HIGH_SEL_300M;
+		else
+			src_clk = ACLK_TOP_HIGH_SEL_24M;
+		rk_clrsetreg(&cru->clksel_con[73],
+			     ACLK_TOP_HIGH_SEL_MASK,
+			     src_clk << ACLK_TOP_HIGH_SEL_SHIFT);
+		break;
+	case ACLK_TOP_LOW:
+		if (rate == 400 * MHz)
+			src_clk = ACLK_TOP_LOW_SEL_400M;
+		else if (rate == 300 * MHz)
+			src_clk = ACLK_TOP_LOW_SEL_300M;
+		else if (rate == 200 * MHz)
+			src_clk = ACLK_TOP_LOW_SEL_200M;
+		else
+			src_clk = ACLK_TOP_LOW_SEL_24M;
+		rk_clrsetreg(&cru->clksel_con[73],
+			     ACLK_TOP_LOW_SEL_MASK,
+			     src_clk << ACLK_TOP_LOW_SEL_SHIFT);
+		break;
+	case HCLK_TOP:
+		if (rate == 150 * MHz)
+			src_clk = HCLK_TOP_SEL_150M;
+		else if (rate == 100 * MHz)
+			src_clk = HCLK_TOP_SEL_100M;
+		else if (rate == 75 * MHz)
+			src_clk = HCLK_TOP_SEL_75M;
+		else
+			src_clk = HCLK_TOP_SEL_24M;
+		rk_clrsetreg(&cru->clksel_con[73],
+			     HCLK_TOP_SEL_MASK,
+			     src_clk << HCLK_TOP_SEL_SHIFT);
+		break;
+	case PCLK_TOP:
+		if (rate == 100 * MHz)
+			src_clk = PCLK_TOP_SEL_100M;
+		else if (rate == 75 * MHz)
+			src_clk = PCLK_TOP_SEL_75M;
+		else if (rate == 50 * MHz)
+			src_clk = PCLK_TOP_SEL_50M;
+		else
+			src_clk = PCLK_TOP_SEL_24M;
+		rk_clrsetreg(&cru->clksel_con[73],
+			     PCLK_TOP_SEL_MASK,
+			     src_clk << PCLK_TOP_SEL_SHIFT);
+		break;
+
+	default:
+		printf("do not support this permid freq\n");
+		return -EINVAL;
+	}
+
+	return rk3568_top_get_clk(priv, clk_id);
+}
+
+static ulong rk3568_i2c_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 sel, con;
+	ulong rate;
+
+	switch (clk_id) {
+	case CLK_I2C1:
+	case CLK_I2C2:
+	case CLK_I2C3:
+	case CLK_I2C4:
+	case CLK_I2C5:
+		con = readl(&cru->clksel_con[71]);
+		sel = (con & CLK_I2C_SEL_MASK) >> CLK_I2C_SEL_SHIFT;
+		if (sel == CLK_I2C_SEL_200M)
+			rate = 200 * MHz;
+		else if (sel == CLK_I2C_SEL_100M)
+			rate = 100 * MHz;
+		else if (sel == CLK_I2C_SEL_CPLL_100M)
+			rate = 100 * MHz;
+		else
+			rate = OSC_HZ;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rate;
+}
+
+static ulong rk3568_i2c_set_clk(struct rk3568_clk_priv *priv, ulong clk_id,
+				ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk;
+
+	if (rate == 200 * MHz)
+		src_clk = CLK_I2C_SEL_200M;
+	else if (rate == 100 * MHz)
+		src_clk = CLK_I2C_SEL_100M;
+	else
+		src_clk = CLK_I2C_SEL_24M;
+
+	switch (clk_id) {
+	case CLK_I2C1:
+	case CLK_I2C2:
+	case CLK_I2C3:
+	case CLK_I2C4:
+	case CLK_I2C5:
+		rk_clrsetreg(&cru->clksel_con[71], CLK_I2C_SEL_MASK,
+			     src_clk << CLK_I2C_SEL_SHIFT);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rk3568_i2c_get_clk(priv, clk_id);
+}
+
+static ulong rk3568_spi_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 sel, con;
+
+	con = readl(&cru->clksel_con[72]);
+
+	switch (clk_id) {
+	case CLK_SPI0:
+		sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT;
+		break;
+	case CLK_SPI1:
+		sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT;
+		break;
+	case CLK_SPI2:
+		sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT;
+		break;
+	case CLK_SPI3:
+		sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	switch (sel) {
+	case CLK_SPI_SEL_200M:
+		return 200 * MHz;
+	case CLK_SPI_SEL_24M:
+		return OSC_HZ;
+	case CLK_SPI_SEL_CPLL_100M:
+		return 100 * MHz;
+	default:
+		return -ENOENT;
+	}
+}
+
+static ulong rk3568_spi_set_clk(struct rk3568_clk_priv *priv,
+				ulong clk_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk;
+
+	if (rate == 200 * MHz)
+		src_clk = CLK_SPI_SEL_200M;
+	else if (rate == 100 * MHz)
+		src_clk = CLK_SPI_SEL_CPLL_100M;
+	else
+		src_clk = CLK_SPI_SEL_24M;
+
+	switch (clk_id) {
+	case CLK_SPI0:
+		rk_clrsetreg(&cru->clksel_con[72],
+			     CLK_SPI0_SEL_MASK,
+			     src_clk << CLK_SPI0_SEL_SHIFT);
+		break;
+	case CLK_SPI1:
+		rk_clrsetreg(&cru->clksel_con[72],
+			     CLK_SPI1_SEL_MASK,
+			     src_clk << CLK_SPI1_SEL_SHIFT);
+		break;
+	case CLK_SPI2:
+		rk_clrsetreg(&cru->clksel_con[72],
+			     CLK_SPI2_SEL_MASK,
+			     src_clk << CLK_SPI2_SEL_SHIFT);
+		break;
+	case CLK_SPI3:
+		rk_clrsetreg(&cru->clksel_con[72],
+			     CLK_SPI3_SEL_MASK,
+			     src_clk << CLK_SPI3_SEL_SHIFT);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rk3568_spi_get_clk(priv, clk_id);
+}
+
+static ulong rk3568_pwm_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 sel, con;
+
+	con = readl(&cru->clksel_con[72]);
+
+	switch (clk_id) {
+	case CLK_PWM1:
+		sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
+		break;
+	case CLK_PWM2:
+		sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;
+		break;
+	case CLK_PWM3:
+		sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	switch (sel) {
+	case CLK_PWM_SEL_100M:
+		return 100 * MHz;
+	case CLK_PWM_SEL_24M:
+		return OSC_HZ;
+	case CLK_PWM_SEL_CPLL_100M:
+		return 100 * MHz;
+	default:
+		return -ENOENT;
+	}
+}
+
+static ulong rk3568_pwm_set_clk(struct rk3568_clk_priv *priv,
+				ulong clk_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk;
+
+	if (rate == 100 * MHz)
+		src_clk = CLK_PWM_SEL_100M;
+	else
+		src_clk = CLK_PWM_SEL_24M;
+
+	switch (clk_id) {
+	case CLK_PWM1:
+		rk_clrsetreg(&cru->clksel_con[72],
+			     CLK_PWM1_SEL_MASK,
+			     src_clk << CLK_PWM1_SEL_SHIFT);
+		break;
+	case CLK_PWM2:
+		rk_clrsetreg(&cru->clksel_con[72],
+			     CLK_PWM2_SEL_MASK,
+			     src_clk << CLK_PWM2_SEL_SHIFT);
+		break;
+	case CLK_PWM3:
+		rk_clrsetreg(&cru->clksel_con[72],
+			     CLK_PWM3_SEL_MASK,
+			     src_clk << CLK_PWM3_SEL_SHIFT);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rk3568_pwm_get_clk(priv, clk_id);
+}
+
+static ulong rk3568_adc_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 div, sel, con, prate;
+
+	switch (clk_id) {
+	case CLK_SARADC:
+		return OSC_HZ;
+	case CLK_TSADC_TSEN:
+		con = readl(&cru->clksel_con[51]);
+		div = (con & CLK_TSADC_TSEN_DIV_MASK) >>
+		      CLK_TSADC_TSEN_DIV_SHIFT;
+		sel = (con & CLK_TSADC_TSEN_SEL_MASK) >>
+		      CLK_TSADC_TSEN_SEL_SHIFT;
+		if (sel == CLK_TSADC_TSEN_SEL_24M)
+			prate = OSC_HZ;
+		else
+			prate = 100 * MHz;
+		return DIV_TO_RATE(prate, div);
+	case CLK_TSADC:
+		con = readl(&cru->clksel_con[51]);
+		div = (con & CLK_TSADC_DIV_MASK) >> CLK_TSADC_DIV_SHIFT;
+		prate = rk3568_adc_get_clk(priv, CLK_TSADC_TSEN);
+		return DIV_TO_RATE(prate, div);
+	default:
+		return -ENOENT;
+	}
+}
+
+static ulong rk3568_adc_set_clk(struct rk3568_clk_priv *priv,
+				ulong clk_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk_div;
+	ulong prate = 0;
+
+	switch (clk_id) {
+	case CLK_SARADC:
+		return OSC_HZ;
+	case CLK_TSADC_TSEN:
+		if (!(OSC_HZ % rate)) {
+			src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);
+			assert(src_clk_div - 1 <= 7);
+			rk_clrsetreg(&cru->clksel_con[51],
+				     CLK_TSADC_TSEN_SEL_MASK |
+				     CLK_TSADC_TSEN_DIV_MASK,
+				     (CLK_TSADC_TSEN_SEL_24M <<
+				      CLK_TSADC_TSEN_SEL_SHIFT) |
+				     (src_clk_div - 1) <<
+				     CLK_TSADC_TSEN_DIV_SHIFT);
+		} else {
+			src_clk_div = DIV_ROUND_UP(100 * MHz, rate);
+			assert(src_clk_div - 1 <= 7);
+			rk_clrsetreg(&cru->clksel_con[51],
+				     CLK_TSADC_TSEN_SEL_MASK |
+				     CLK_TSADC_TSEN_DIV_MASK,
+				     (CLK_TSADC_TSEN_SEL_100M <<
+				      CLK_TSADC_TSEN_SEL_SHIFT) |
+				     (src_clk_div - 1) <<
+				     CLK_TSADC_TSEN_DIV_SHIFT);
+		}
+		break;
+	case CLK_TSADC:
+			prate = rk3568_adc_get_clk(priv, CLK_TSADC_TSEN);
+			src_clk_div = DIV_ROUND_UP(prate, rate);
+			assert(src_clk_div - 1 <= 128);
+			rk_clrsetreg(&cru->clksel_con[51],
+				     CLK_TSADC_DIV_MASK,
+				     (src_clk_div - 1) << CLK_TSADC_DIV_SHIFT);
+		break;
+	default:
+		return -ENOENT;
+	}
+	return rk3568_adc_get_clk(priv, clk_id);
+}
+
+static ulong rk3568_crypto_get_rate(struct rk3568_clk_priv *priv, ulong clk_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 sel, con;
+
+	switch (clk_id) {
+	case ACLK_SECURE_FLASH:
+	case ACLK_CRYPTO_NS:
+		con = readl(&cru->clksel_con[27]);
+		sel = (con & ACLK_SECURE_FLASH_SEL_MASK) >>
+		      ACLK_SECURE_FLASH_SEL_SHIFT;
+		if (sel == ACLK_SECURE_FLASH_SEL_200M)
+			return 200 * MHz;
+		else if (sel == ACLK_SECURE_FLASH_SEL_150M)
+			return 150 * MHz;
+		else if (sel == ACLK_SECURE_FLASH_SEL_100M)
+			return 100 * MHz;
+		else
+			return 24 * MHz;
+	case HCLK_SECURE_FLASH:
+	case HCLK_CRYPTO_NS:
+	case CLK_CRYPTO_NS_RNG:
+		con = readl(&cru->clksel_con[27]);
+		sel = (con & HCLK_SECURE_FLASH_SEL_MASK) >>
+		      HCLK_SECURE_FLASH_SEL_SHIFT;
+		if (sel == HCLK_SECURE_FLASH_SEL_150M)
+			return 150 * MHz;
+		else if (sel == HCLK_SECURE_FLASH_SEL_100M)
+			return 100 * MHz;
+		else if (sel == HCLK_SECURE_FLASH_SEL_75M)
+			return 75 * MHz;
+		else
+			return 24 * MHz;
+	case CLK_CRYPTO_NS_CORE:
+		con = readl(&cru->clksel_con[27]);
+		sel = (con & CLK_CRYPTO_CORE_SEL_MASK) >>
+		      CLK_CRYPTO_CORE_SEL_SHIFT;
+		if (sel == CLK_CRYPTO_CORE_SEL_200M)
+			return 200 * MHz;
+		else if (sel == CLK_CRYPTO_CORE_SEL_150M)
+			return 150 * MHz;
+		else
+			return 100 * MHz;
+	case CLK_CRYPTO_NS_PKA:
+		con = readl(&cru->clksel_con[27]);
+		sel = (con & CLK_CRYPTO_PKA_SEL_MASK) >>
+		      CLK_CRYPTO_PKA_SEL_SHIFT;
+		if (sel == CLK_CRYPTO_PKA_SEL_300M)
+			return 300 * MHz;
+		else if (sel == CLK_CRYPTO_PKA_SEL_200M)
+			return 200 * MHz;
+		else
+			return 100 * MHz;
+	default:
+		return -ENOENT;
+	}
+}
+
+static ulong rk3568_crypto_set_rate(struct rk3568_clk_priv *priv,
+				    ulong clk_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 src_clk, mask, shift;
+
+	switch (clk_id) {
+	case ACLK_SECURE_FLASH:
+	case ACLK_CRYPTO_NS:
+		mask = ACLK_SECURE_FLASH_SEL_MASK;
+		shift = ACLK_SECURE_FLASH_SEL_SHIFT;
+		if (rate == 200 * MHz)
+			src_clk = ACLK_SECURE_FLASH_SEL_200M;
+		else if (rate == 150 * MHz)
+			src_clk = ACLK_SECURE_FLASH_SEL_150M;
+		else if (rate == 100 * MHz)
+			src_clk = ACLK_SECURE_FLASH_SEL_100M;
+		else
+			src_clk = ACLK_SECURE_FLASH_SEL_24M;
+		break;
+	case HCLK_SECURE_FLASH:
+	case HCLK_CRYPTO_NS:
+	case CLK_CRYPTO_NS_RNG:
+		mask = HCLK_SECURE_FLASH_SEL_MASK;
+		shift = HCLK_SECURE_FLASH_SEL_SHIFT;
+		if (rate == 150 * MHz)
+			src_clk = HCLK_SECURE_FLASH_SEL_150M;
+		else if (rate == 100 * MHz)
+			src_clk = HCLK_SECURE_FLASH_SEL_100M;
+		else if (rate == 75 * MHz)
+			src_clk = HCLK_SECURE_FLASH_SEL_75M;
+		else
+			src_clk = HCLK_SECURE_FLASH_SEL_24M;
+		break;
+	case CLK_CRYPTO_NS_CORE:
+		mask = CLK_CRYPTO_CORE_SEL_MASK;
+		shift = CLK_CRYPTO_CORE_SEL_SHIFT;
+		if (rate == 200 * MHz)
+			src_clk = CLK_CRYPTO_CORE_SEL_200M;
+		else if (rate == 150 * MHz)
+			src_clk = CLK_CRYPTO_CORE_SEL_150M;
+		else
+			src_clk = CLK_CRYPTO_CORE_SEL_100M;
+		break;
+	case CLK_CRYPTO_NS_PKA:
+		mask = CLK_CRYPTO_PKA_SEL_MASK;
+		shift = CLK_CRYPTO_PKA_SEL_SHIFT;
+		if (rate == 300 * MHz)
+			src_clk = CLK_CRYPTO_PKA_SEL_300M;
+		else if (rate == 200 * MHz)
+			src_clk = CLK_CRYPTO_PKA_SEL_200M;
+		else
+			src_clk = CLK_CRYPTO_PKA_SEL_100M;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	rk_clrsetreg(&cru->clksel_con[27], mask, src_clk << shift);
+
+	return rk3568_crypto_get_rate(priv, clk_id);
+}
+
+static ulong rk3568_sdmmc_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 sel, con;
+
+	switch (clk_id) {
+	case HCLK_SDMMC0:
+	case CLK_SDMMC0:
+		con = readl(&cru->clksel_con[30]);
+		sel = (con & CLK_SDMMC0_SEL_MASK) >> CLK_SDMMC0_SEL_SHIFT;
+		break;
+	case CLK_SDMMC1:
+		con = readl(&cru->clksel_con[30]);
+		sel = (con & CLK_SDMMC1_SEL_MASK) >> CLK_SDMMC1_SEL_SHIFT;
+		break;
+	case CLK_SDMMC2:
+		con = readl(&cru->clksel_con[32]);
+		sel = (con & CLK_SDMMC2_SEL_MASK) >> CLK_SDMMC2_SEL_SHIFT;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	switch (sel) {
+	case CLK_SDMMC_SEL_24M:
+		return OSC_HZ;
+	case CLK_SDMMC_SEL_400M:
+		return 400 * MHz;
+	case CLK_SDMMC_SEL_300M:
+		return 300 * MHz;
+	case CLK_SDMMC_SEL_100M:
+		return 100 * MHz;
+	case CLK_SDMMC_SEL_50M:
+		return 50 * MHz;
+	case CLK_SDMMC_SEL_750K:
+		return 750 * KHz;
+	default:
+		return -ENOENT;
+	}
+}
+
+static ulong rk3568_sdmmc_set_clk(struct rk3568_clk_priv *priv,
+				  ulong clk_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk;
+
+	switch (rate) {
+	case OSC_HZ:
+		src_clk = CLK_SDMMC_SEL_24M;
+		break;
+	case 400 * MHz:
+		src_clk = CLK_SDMMC_SEL_400M;
+		break;
+	case 300 * MHz:
+		src_clk = CLK_SDMMC_SEL_300M;
+		break;
+	case 100 * MHz:
+		src_clk = CLK_SDMMC_SEL_100M;
+		break;
+	case 52 * MHz:
+	case 50 * MHz:
+		src_clk = CLK_SDMMC_SEL_50M;
+		break;
+	case 750 * KHz:
+	case 400 * KHz:
+		src_clk = CLK_SDMMC_SEL_750K;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	switch (clk_id) {
+	case HCLK_SDMMC0:
+	case CLK_SDMMC0:
+		rk_clrsetreg(&cru->clksel_con[30],
+			     CLK_SDMMC0_SEL_MASK,
+			     src_clk << CLK_SDMMC0_SEL_SHIFT);
+		break;
+	case CLK_SDMMC1:
+		rk_clrsetreg(&cru->clksel_con[30],
+			     CLK_SDMMC1_SEL_MASK,
+			     src_clk << CLK_SDMMC1_SEL_SHIFT);
+		break;
+	case CLK_SDMMC2:
+		rk_clrsetreg(&cru->clksel_con[32],
+			     CLK_SDMMC2_SEL_MASK,
+			     src_clk << CLK_SDMMC2_SEL_SHIFT);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rk3568_sdmmc_get_clk(priv, clk_id);
+}
+
+static ulong rk3568_sfc_get_clk(struct rk3568_clk_priv *priv)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 sel, con;
+
+	con = readl(&cru->clksel_con[28]);
+	sel = (con & SCLK_SFC_SEL_MASK) >> SCLK_SFC_SEL_SHIFT;
+	switch (sel) {
+	case SCLK_SFC_SEL_24M:
+		return OSC_HZ;
+	case SCLK_SFC_SEL_50M:
+		return 50 * MHz;
+	case SCLK_SFC_SEL_75M:
+		return 75 * MHz;
+	case SCLK_SFC_SEL_100M:
+		return 100 * MHz;
+	case SCLK_SFC_SEL_125M:
+		return 125 * MHz;
+	case SCLK_SFC_SEL_150M:
+		return 150 * KHz;
+	default:
+		return -ENOENT;
+	}
+}
+
+static ulong rk3568_sfc_set_clk(struct rk3568_clk_priv *priv, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk;
+
+	switch (rate) {
+	case OSC_HZ:
+		src_clk = SCLK_SFC_SEL_24M;
+		break;
+	case 50 * MHz:
+		src_clk = SCLK_SFC_SEL_50M;
+		break;
+	case 75 * MHz:
+		src_clk = SCLK_SFC_SEL_75M;
+		break;
+	case 100 * MHz:
+		src_clk = SCLK_SFC_SEL_100M;
+		break;
+	case 125 * MHz:
+		src_clk = SCLK_SFC_SEL_125M;
+		break;
+	case 150 * KHz:
+		src_clk = SCLK_SFC_SEL_150M;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	rk_clrsetreg(&cru->clksel_con[28],
+		     SCLK_SFC_SEL_MASK,
+		     src_clk << SCLK_SFC_SEL_SHIFT);
+
+	return rk3568_sfc_get_clk(priv);
+}
+
+static ulong rk3568_nand_get_clk(struct rk3568_clk_priv *priv)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 sel, con;
+
+	con = readl(&cru->clksel_con[28]);
+	sel = (con & NCLK_NANDC_SEL_MASK) >> NCLK_NANDC_SEL_SHIFT;
+	switch (sel) {
+	case NCLK_NANDC_SEL_200M:
+		return 200 * MHz;
+	case NCLK_NANDC_SEL_150M:
+		return 150 * MHz;
+	case NCLK_NANDC_SEL_100M:
+		return 100 * MHz;
+	case NCLK_NANDC_SEL_24M:
+		return OSC_HZ;
+	default:
+		return -ENOENT;
+	}
+}
+
+static ulong rk3568_nand_set_clk(struct rk3568_clk_priv *priv, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk;
+
+	switch (rate) {
+	case OSC_HZ:
+		src_clk = NCLK_NANDC_SEL_24M;
+		break;
+	case 100 * MHz:
+		src_clk = NCLK_NANDC_SEL_100M;
+		break;
+	case 150 * MHz:
+		src_clk = NCLK_NANDC_SEL_150M;
+		break;
+	case 200 * MHz:
+		src_clk = NCLK_NANDC_SEL_200M;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	rk_clrsetreg(&cru->clksel_con[28],
+		     NCLK_NANDC_SEL_MASK,
+		     src_clk << NCLK_NANDC_SEL_SHIFT);
+
+	return rk3568_nand_get_clk(priv);
+}
+
+static ulong rk3568_emmc_get_clk(struct rk3568_clk_priv *priv)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 sel, con;
+
+	con = readl(&cru->clksel_con[28]);
+	sel = (con & CCLK_EMMC_SEL_MASK) >> CCLK_EMMC_SEL_SHIFT;
+	switch (sel) {
+	case CCLK_EMMC_SEL_200M:
+		return 200 * MHz;
+	case CCLK_EMMC_SEL_150M:
+		return 150 * MHz;
+	case CCLK_EMMC_SEL_100M:
+		return 100 * MHz;
+	case CCLK_EMMC_SEL_50M:
+		return 50 * MHz;
+	case CCLK_EMMC_SEL_375K:
+		return 375 * KHz;
+	case CCLK_EMMC_SEL_24M:
+		return OSC_HZ;
+	default:
+		return -ENOENT;
+	}
+}
+
+static ulong rk3568_emmc_set_clk(struct rk3568_clk_priv *priv, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk;
+
+	switch (rate) {
+	case OSC_HZ:
+		src_clk = CCLK_EMMC_SEL_24M;
+		break;
+	case 52 * MHz:
+	case 50 * MHz:
+		src_clk = CCLK_EMMC_SEL_50M;
+		break;
+	case 100 * MHz:
+		src_clk = CCLK_EMMC_SEL_100M;
+		break;
+	case 150 * MHz:
+		src_clk = CCLK_EMMC_SEL_150M;
+		break;
+	case 200 * MHz:
+		src_clk = CCLK_EMMC_SEL_200M;
+		break;
+	case 400 * KHz:
+	case 375 * KHz:
+		src_clk = CCLK_EMMC_SEL_375K;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	rk_clrsetreg(&cru->clksel_con[28],
+		     CCLK_EMMC_SEL_MASK,
+		     src_clk << CCLK_EMMC_SEL_SHIFT);
+
+	return rk3568_emmc_get_clk(priv);
+}
+
+static ulong rk3568_emmc_get_bclk(struct rk3568_clk_priv *priv)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 sel, con;
+
+	con = readl(&cru->clksel_con[28]);
+	sel = (con & BCLK_EMMC_SEL_MASK) >> BCLK_EMMC_SEL_SHIFT;
+	switch (sel) {
+	case BCLK_EMMC_SEL_200M:
+		return 200 * MHz;
+	case BCLK_EMMC_SEL_150M:
+		return 150 * MHz;
+	case BCLK_EMMC_SEL_125M:
+		return 125 * MHz;
+	default:
+		return -ENOENT;
+	}
+}
+
+static ulong rk3568_emmc_set_bclk(struct rk3568_clk_priv *priv, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk;
+
+	switch (rate) {
+	case 200 * MHz:
+		src_clk = BCLK_EMMC_SEL_200M;
+		break;
+	case 150 * MHz:
+		src_clk = BCLK_EMMC_SEL_150M;
+		break;
+	case 125 * MHz:
+		src_clk = BCLK_EMMC_SEL_125M;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	rk_clrsetreg(&cru->clksel_con[28],
+		     BCLK_EMMC_SEL_MASK,
+		     src_clk << BCLK_EMMC_SEL_SHIFT);
+
+	return rk3568_emmc_get_bclk(priv);
+}
+
+#ifndef CONFIG_SPL_BUILD
+static ulong rk3568_aclk_vop_get_clk(struct rk3568_clk_priv *priv)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 div, sel, con, parent;
+
+	con = readl(&cru->clksel_con[38]);
+	div = (con & ACLK_VOP_PRE_DIV_MASK) >> ACLK_VOP_PRE_DIV_SHIFT;
+	sel = (con & ACLK_VOP_PRE_SEL_MASK) >> ACLK_VOP_PRE_SEL_SHIFT;
+	if (sel == ACLK_VOP_PRE_SEL_GPLL)
+		parent = priv->gpll_hz;
+	else if (sel == ACLK_VOP_PRE_SEL_CPLL)
+		parent = priv->cpll_hz;
+	else if (sel == ACLK_VOP_PRE_SEL_VPLL)
+		parent = priv->vpll_hz;
+	else
+		parent = priv->hpll_hz;
+
+	return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3568_aclk_vop_set_clk(struct rk3568_clk_priv *priv, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk_div, src_clk_mux;
+
+	if ((priv->cpll_hz % rate) == 0) {
+		src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
+		src_clk_mux = ACLK_VOP_PRE_SEL_CPLL;
+	} else {
+		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+		src_clk_mux = ACLK_VOP_PRE_SEL_GPLL;
+	}
+	assert(src_clk_div - 1 <= 31);
+	rk_clrsetreg(&cru->clksel_con[38],
+		     ACLK_VOP_PRE_SEL_MASK | ACLK_VOP_PRE_DIV_MASK,
+		     src_clk_mux << ACLK_VOP_PRE_SEL_SHIFT |
+		     (src_clk_div - 1) << ACLK_VOP_PRE_DIV_SHIFT);
+
+	return rk3568_aclk_vop_get_clk(priv);
+}
+
+static ulong rk3568_dclk_vop_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 conid, div, sel, con, parent;
+
+	switch (clk_id) {
+	case DCLK_VOP0:
+		conid = 39;
+		break;
+	case DCLK_VOP1:
+		conid = 40;
+		break;
+	case DCLK_VOP2:
+		conid = 41;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	con = readl(&cru->clksel_con[conid]);
+	div = (con & DCLK0_VOP_DIV_MASK) >> DCLK0_VOP_DIV_SHIFT;
+	sel = (con & DCLK0_VOP_SEL_MASK) >> DCLK0_VOP_SEL_SHIFT;
+	if (sel == DCLK_VOP_SEL_HPLL)
+		parent = rk3568_pmu_pll_get_rate(priv, HPLL);
+	else if (sel == DCLK_VOP_SEL_VPLL)
+		parent = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL],
+					       priv->cru, VPLL);
+	else if (sel == DCLK_VOP_SEL_GPLL)
+		parent = priv->gpll_hz;
+	else if (sel == DCLK_VOP_SEL_CPLL)
+		parent = priv->cpll_hz;
+	else
+		return -ENOENT;
+
+	return DIV_TO_RATE(parent, div);
+}
+
+#define RK3568_VOP_PLL_LIMIT_FREQ 600000000
+
+static ulong rk3568_dclk_vop_set_clk(struct rk3568_clk_priv *priv,
+				     ulong clk_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	ulong pll_rate, now, best_rate = 0;
+	u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;
+
+	switch (clk_id) {
+	case DCLK_VOP0:
+		conid = 39;
+		break;
+	case DCLK_VOP1:
+		conid = 40;
+		break;
+	case DCLK_VOP2:
+		conid = 41;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	con = readl(&cru->clksel_con[conid]);
+	sel = (con & DCLK0_VOP_SEL_MASK) >> DCLK0_VOP_SEL_SHIFT;
+
+	if (sel == DCLK_VOP_SEL_HPLL) {
+		div = 1;
+		rk_clrsetreg(&cru->clksel_con[conid],
+			     DCLK0_VOP_DIV_MASK | DCLK0_VOP_SEL_MASK,
+			     (DCLK_VOP_SEL_HPLL << DCLK0_VOP_SEL_SHIFT) |
+			     ((div - 1) << DCLK0_VOP_DIV_SHIFT));
+		rk3568_pmu_pll_set_rate(priv, HPLL, div * rate);
+	} else if (sel == DCLK_VOP_SEL_VPLL) {
+		div = DIV_ROUND_UP(RK3568_VOP_PLL_LIMIT_FREQ, rate);
+		rk_clrsetreg(&cru->clksel_con[conid],
+			     DCLK0_VOP_DIV_MASK | DCLK0_VOP_SEL_MASK,
+			     (DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT) |
+			     ((div - 1) << DCLK0_VOP_DIV_SHIFT));
+		rockchip_pll_set_rate(&rk3568_pll_clks[VPLL],
+				      priv->cru, VPLL, div * rate);
+	} else {
+		for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) {
+			switch (i) {
+			case DCLK_VOP_SEL_GPLL:
+				pll_rate = priv->gpll_hz;
+				break;
+			case DCLK_VOP_SEL_CPLL:
+				pll_rate = priv->cpll_hz;
+				break;
+			default:
+				printf("do not support this vop pll sel\n");
+				return -EINVAL;
+			}
+
+			div = DIV_ROUND_UP(pll_rate, rate);
+			if (div > 255)
+				continue;
+			now = pll_rate / div;
+			if (abs(rate - now) < abs(rate - best_rate)) {
+				best_rate = now;
+				best_div = div;
+				best_sel = i;
+			}
+			debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n",
+			      pll_rate, best_rate, best_div, best_sel);
+		}
+
+		if (best_rate) {
+			rk_clrsetreg(&cru->clksel_con[conid],
+				     DCLK0_VOP_DIV_MASK | DCLK0_VOP_SEL_MASK,
+				     best_sel << DCLK0_VOP_SEL_SHIFT |
+				     (best_div - 1) << DCLK0_VOP_DIV_SHIFT);
+		} else {
+			printf("do not support this vop freq %lu\n", rate);
+			return -EINVAL;
+		}
+	}
+	return rk3568_dclk_vop_get_clk(priv, clk_id);
+}
+
+static ulong rk3568_gmac_src_get_clk(struct rk3568_clk_priv *priv,
+				     ulong mac_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 sel, con;
+
+	con = readl(&cru->clksel_con[31 + mac_id * 2]);
+	sel = (con & CLK_MAC0_2TOP_SEL_MASK) >> CLK_MAC0_2TOP_SEL_SHIFT;
+
+	switch (sel) {
+	case CLK_MAC0_2TOP_SEL_125M:
+		return 125 * MHz;
+	case CLK_MAC0_2TOP_SEL_50M:
+		return 50 * MHz;
+	case CLK_MAC0_2TOP_SEL_25M:
+		return 25 * MHz;
+	case CLK_MAC0_2TOP_SEL_PPLL:
+		return rk3568_pmu_pll_get_rate(priv, HPLL);
+	default:
+		return -ENOENT;
+	}
+}
+
+static ulong rk3568_gmac_src_set_clk(struct rk3568_clk_priv *priv,
+				     ulong mac_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk;
+
+	switch (rate) {
+	case 125 * MHz:
+		src_clk = CLK_MAC0_2TOP_SEL_125M;
+		break;
+	case 50 * MHz:
+		src_clk = CLK_MAC0_2TOP_SEL_50M;
+		break;
+	case 25 * MHz:
+		src_clk = CLK_MAC0_2TOP_SEL_25M;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	rk_clrsetreg(&cru->clksel_con[31 + mac_id * 2],
+		     CLK_MAC0_2TOP_SEL_MASK,
+		     src_clk << CLK_MAC0_2TOP_SEL_SHIFT);
+
+	return rk3568_gmac_src_get_clk(priv, mac_id);
+}
+
+static ulong rk3568_gmac_out_get_clk(struct rk3568_clk_priv *priv,
+				     ulong mac_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 sel, con;
+
+	con = readl(&cru->clksel_con[31 + mac_id * 2]);
+	sel = (con & CLK_MAC0_OUT_SEL_MASK) >> CLK_MAC0_OUT_SEL_SHIFT;
+
+	switch (sel) {
+	case CLK_MAC0_OUT_SEL_125M:
+		return 125 * MHz;
+	case CLK_MAC0_OUT_SEL_50M:
+		return 50 * MHz;
+	case CLK_MAC0_OUT_SEL_25M:
+		return 25 * MHz;
+	case CLK_MAC0_OUT_SEL_24M:
+		return OSC_HZ;
+	default:
+		return -ENOENT;
+	}
+}
+
+static ulong rk3568_gmac_out_set_clk(struct rk3568_clk_priv *priv,
+				     ulong mac_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk;
+
+	switch (rate) {
+	case 125 * MHz:
+		src_clk = CLK_MAC0_OUT_SEL_125M;
+		break;
+	case 50 * MHz:
+		src_clk = CLK_MAC0_OUT_SEL_50M;
+		break;
+	case 25 * MHz:
+		src_clk = CLK_MAC0_OUT_SEL_25M;
+		break;
+	case 24 * MHz:
+		src_clk = CLK_MAC0_OUT_SEL_24M;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	rk_clrsetreg(&cru->clksel_con[31 + mac_id * 2],
+		     CLK_MAC0_OUT_SEL_MASK,
+		     src_clk << CLK_MAC0_OUT_SEL_SHIFT);
+
+	return rk3568_gmac_out_get_clk(priv, mac_id);
+}
+
+static ulong rk3568_gmac_ptp_ref_get_clk(struct rk3568_clk_priv *priv,
+					 ulong mac_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 sel, con;
+
+	con = readl(&cru->clksel_con[31 + mac_id * 2]);
+	sel = (con & CLK_GMAC0_PTP_REF_SEL_MASK) >> CLK_GMAC0_PTP_REF_SEL_SHIFT;
+
+	switch (sel) {
+	case CLK_GMAC0_PTP_REF_SEL_62_5M:
+		return 62500 * KHz;
+	case CLK_GMAC0_PTP_REF_SEL_100M:
+		return 100 * MHz;
+	case CLK_GMAC0_PTP_REF_SEL_50M:
+		return 50 * MHz;
+	case CLK_GMAC0_PTP_REF_SEL_24M:
+		return OSC_HZ;
+	default:
+		return -ENOENT;
+	}
+}
+
+static ulong rk3568_gmac_ptp_ref_set_clk(struct rk3568_clk_priv *priv,
+					 ulong mac_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk;
+
+	switch (rate) {
+	case 62500 * KHz:
+		src_clk = CLK_GMAC0_PTP_REF_SEL_62_5M;
+		break;
+	case 100 * MHz:
+		src_clk = CLK_GMAC0_PTP_REF_SEL_100M;
+		break;
+	case 50 * MHz:
+		src_clk = CLK_GMAC0_PTP_REF_SEL_50M;
+		break;
+	case 24 * MHz:
+		src_clk = CLK_GMAC0_PTP_REF_SEL_24M;
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	rk_clrsetreg(&cru->clksel_con[31 + mac_id * 2],
+		     CLK_GMAC0_PTP_REF_SEL_MASK,
+		     src_clk << CLK_GMAC0_PTP_REF_SEL_SHIFT);
+
+	return rk3568_gmac_ptp_ref_get_clk(priv, mac_id);
+}
+
+static ulong rk3568_gmac_tx_rx_set_clk(struct rk3568_clk_priv *priv,
+				       ulong mac_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 con, sel, div_sel;
+
+	con = readl(&cru->clksel_con[31 + mac_id * 2]);
+	sel = (con & RMII0_MODE_MASK) >> RMII0_MODE_SHIFT;
+
+	if (sel == RMII0_MODE_SEL_RGMII) {
+		if (rate == 2500000)
+			div_sel = RGMII0_CLK_SEL_2_5M;
+		else if (rate == 25000000)
+			div_sel = RGMII0_CLK_SEL_25M;
+		else
+			div_sel = RGMII0_CLK_SEL_125M;
+		rk_clrsetreg(&cru->clksel_con[31 + mac_id * 2],
+			     RGMII0_CLK_SEL_MASK,
+			     div_sel << RGMII0_CLK_SEL_SHIFT);
+	} else if (sel == RMII0_MODE_SEL_RMII) {
+		if (rate == 2500000)
+			div_sel = RMII0_CLK_SEL_2_5M;
+		else
+			div_sel = RMII0_CLK_SEL_25M;
+		rk_clrsetreg(&cru->clksel_con[31 + mac_id * 2],
+			     RMII0_CLK_SEL_MASK,
+			     div_sel << RMII0_CLK_SEL_SHIFT);
+	}
+
+	return 0;
+}
+
+static ulong rk3568_ebc_get_clk(struct rk3568_clk_priv *priv)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 con, div, p_rate;
+
+	con = readl(&cru->clksel_con[79]);
+	div = (con & CPLL_333M_DIV_MASK) >> CPLL_333M_DIV_SHIFT;
+	p_rate = DIV_TO_RATE(priv->cpll_hz, div);
+
+	con = readl(&cru->clksel_con[43]);
+	div = (con & DCLK_EBC_SEL_MASK) >> DCLK_EBC_SEL_SHIFT;
+	switch (div) {
+	case DCLK_EBC_SEL_GPLL_400M:
+		return 400 * MHz;
+	case DCLK_EBC_SEL_CPLL_333M:
+		return p_rate;
+	case DCLK_EBC_SEL_GPLL_200M:
+		return 200 * MHz;
+	default:
+		return -ENOENT;
+	}
+}
+
+static ulong rk3568_ebc_set_clk(struct rk3568_clk_priv *priv, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk_div;
+
+	src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
+	assert(src_clk_div - 1 <= 31);
+	rk_clrsetreg(&cru->clksel_con[79],
+		     CPLL_333M_DIV_MASK,
+		     (src_clk_div - 1) << CPLL_333M_DIV_SHIFT);
+	rk_clrsetreg(&cru->clksel_con[43],
+		     DCLK_EBC_SEL_MASK,
+		     DCLK_EBC_SEL_CPLL_333M << DCLK_EBC_SEL_SHIFT);
+
+	return rk3568_ebc_get_clk(priv);
+}
+
+static ulong rk3568_rkvdec_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 con, div, src, p_rate;
+
+	switch (clk_id) {
+	case ACLK_RKVDEC_PRE:
+	case ACLK_RKVDEC:
+		con = readl(&cru->clksel_con[47]);
+		src = (con & ACLK_RKVDEC_SEL_MASK) >> ACLK_RKVDEC_SEL_SHIFT;
+		div = (con & ACLK_RKVDEC_DIV_MASK) >> ACLK_RKVDEC_DIV_SHIFT;
+		if (src == ACLK_RKVDEC_SEL_CPLL)
+			p_rate = priv->cpll_hz;
+		else
+			p_rate = priv->gpll_hz;
+		return DIV_TO_RATE(p_rate, div);
+	case CLK_RKVDEC_CORE:
+		con = readl(&cru->clksel_con[49]);
+		src = (con & CLK_RKVDEC_CORE_SEL_MASK)
+		      >> CLK_RKVDEC_CORE_SEL_SHIFT;
+		div = (con & CLK_RKVDEC_CORE_DIV_MASK)
+		      >> CLK_RKVDEC_CORE_DIV_SHIFT;
+		if (src == CLK_RKVDEC_CORE_SEL_CPLL)
+			p_rate = priv->cpll_hz;
+		else if (src == CLK_RKVDEC_CORE_SEL_NPLL)
+			p_rate = priv->npll_hz;
+		else if (src == CLK_RKVDEC_CORE_SEL_VPLL)
+			p_rate = priv->vpll_hz;
+		else
+			p_rate = priv->gpll_hz;
+		return DIV_TO_RATE(p_rate, div);
+	default:
+		return -ENOENT;
+	}
+}
+
+static ulong rk3568_rkvdec_set_clk(struct rk3568_clk_priv *priv,
+				   ulong clk_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	int src_clk_div, src, p_rate;
+
+	switch (clk_id) {
+	case ACLK_RKVDEC_PRE:
+	case ACLK_RKVDEC:
+		src = (readl(&cru->clksel_con[47]) & ACLK_RKVDEC_SEL_MASK)
+		      >> ACLK_RKVDEC_SEL_SHIFT;
+		if (src == ACLK_RKVDEC_SEL_CPLL)
+			p_rate = priv->cpll_hz;
+		else
+			p_rate = priv->gpll_hz;
+		src_clk_div = DIV_ROUND_UP(p_rate, rate);
+		assert(src_clk_div - 1 <= 31);
+		rk_clrsetreg(&cru->clksel_con[47],
+			     ACLK_RKVDEC_SEL_MASK |
+			     ACLK_RKVDEC_DIV_MASK,
+			     (src << ACLK_RKVDEC_SEL_SHIFT) |
+			     (src_clk_div - 1) << ACLK_RKVDEC_DIV_SHIFT);
+		break;
+	case CLK_RKVDEC_CORE:
+		src = (readl(&cru->clksel_con[49]) & CLK_RKVDEC_CORE_SEL_MASK)
+		      >> CLK_RKVDEC_CORE_SEL_SHIFT;
+		if (src == CLK_RKVDEC_CORE_SEL_CPLL)
+			p_rate = priv->cpll_hz;
+		else if (src == CLK_RKVDEC_CORE_SEL_NPLL)
+			p_rate = priv->npll_hz;
+		else if (src == CLK_RKVDEC_CORE_SEL_VPLL)
+			p_rate = priv->vpll_hz;
+		else
+			p_rate = priv->gpll_hz;
+		src_clk_div = DIV_ROUND_UP(p_rate, rate);
+		assert(src_clk_div - 1 <= 31);
+		rk_clrsetreg(&cru->clksel_con[49],
+			     CLK_RKVDEC_CORE_SEL_MASK |
+			     CLK_RKVDEC_CORE_DIV_MASK,
+			     (src << CLK_RKVDEC_CORE_SEL_SHIFT) |
+			     (src_clk_div - 1) << CLK_RKVDEC_CORE_DIV_SHIFT);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rk3568_rkvdec_get_clk(priv, clk_id);
+}
+
+static ulong rk3568_uart_get_rate(struct rk3568_clk_priv *priv, ulong clk_id)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 reg, con, fracdiv, div, src, p_src, p_rate;
+	unsigned long m, n;
+
+	switch (clk_id) {
+	case SCLK_UART1:
+		reg = 52;
+		break;
+	case SCLK_UART2:
+		reg = 54;
+		break;
+	case SCLK_UART3:
+		reg = 56;
+		break;
+	case SCLK_UART4:
+		reg = 58;
+		break;
+	case SCLK_UART5:
+		reg = 60;
+		break;
+	case SCLK_UART6:
+		reg = 62;
+		break;
+	case SCLK_UART7:
+		reg = 64;
+		break;
+	case SCLK_UART8:
+		reg = 66;
+		break;
+	case SCLK_UART9:
+		reg = 68;
+		break;
+	default:
+		return -ENOENT;
+	}
+	con = readl(&cru->clksel_con[reg]);
+	src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT;
+	div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT;
+	p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT;
+	if (p_src == CLK_UART_SRC_SEL_GPLL)
+		p_rate = priv->gpll_hz;
+	else if (p_src == CLK_UART_SRC_SEL_CPLL)
+		p_rate = priv->cpll_hz;
+	else
+		p_rate = 480000000;
+	if (src == CLK_UART_SEL_SRC) {
+		return DIV_TO_RATE(p_rate, div);
+	} else if (src == CLK_UART_SEL_FRAC) {
+		fracdiv = readl(&cru->clksel_con[reg + 1]);
+		n = fracdiv & CLK_UART_FRAC_NUMERATOR_MASK;
+		n >>= CLK_UART_FRAC_NUMERATOR_SHIFT;
+		m = fracdiv & CLK_UART_FRAC_DENOMINATOR_MASK;
+		m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;
+		return DIV_TO_RATE(p_rate, div) * n / m;
+	} else {
+		return OSC_HZ;
+	}
+}
+
+static ulong rk3568_uart_set_rate(struct rk3568_clk_priv *priv,
+				  ulong clk_id, ulong rate)
+{
+	struct rk3568_cru *cru = priv->cru;
+	u32 reg, clk_src, uart_src, div;
+	unsigned long m = 0, n = 0, val;
+
+	if (priv->gpll_hz % rate == 0) {
+		clk_src = CLK_UART_SRC_SEL_GPLL;
+		uart_src = CLK_UART_SEL_SRC;
+		div = DIV_ROUND_UP(priv->gpll_hz, rate);
+	} else if (priv->cpll_hz % rate == 0) {
+		clk_src = CLK_UART_SRC_SEL_CPLL;
+		uart_src = CLK_UART_SEL_SRC;
+		div = DIV_ROUND_UP(priv->gpll_hz, rate);
+	} else if (rate == OSC_HZ) {
+		clk_src = CLK_UART_SRC_SEL_GPLL;
+		uart_src = CLK_UART_SEL_XIN24M;
+		div = 2;
+	} else {
+		clk_src = CLK_UART_SRC_SEL_GPLL;
+		uart_src = CLK_UART_SEL_FRAC;
+		div = 2;
+		rational_best_approximation(rate, priv->gpll_hz / div,
+					    GENMASK(16 - 1, 0),
+					    GENMASK(16 - 1, 0),
+					    &m, &n);
+	}
+
+	switch (clk_id) {
+	case SCLK_UART1:
+		reg = 52;
+		break;
+	case SCLK_UART2:
+		reg = 54;
+		break;
+	case SCLK_UART3:
+		reg = 56;
+		break;
+	case SCLK_UART4:
+		reg = 58;
+		break;
+	case SCLK_UART5:
+		reg = 60;
+		break;
+	case SCLK_UART6:
+		reg = 62;
+		break;
+	case SCLK_UART7:
+		reg = 64;
+		break;
+	case SCLK_UART8:
+		reg = 66;
+		break;
+	case SCLK_UART9:
+		reg = 68;
+		break;
+	default:
+		return -ENOENT;
+	}
+	rk_clrsetreg(&cru->clksel_con[reg],
+		     CLK_UART_SEL_MASK | CLK_UART_SRC_SEL_MASK |
+		     CLK_UART_SRC_DIV_MASK,
+		     (clk_src << CLK_UART_SRC_SEL_SHIFT) |
+		     (uart_src << CLK_UART_SEL_SHIFT) |
+		     ((div - 1) << CLK_UART_SRC_DIV_SHIFT));
+	if (m && n) {
+		val = m << CLK_UART_FRAC_NUMERATOR_SHIFT | n;
+		writel(val, &cru->clksel_con[reg + 1]);
+	}
+
+	return rk3568_uart_get_rate(priv, clk_id);
+}
+#endif
+
+static ulong rk3568_clk_get_rate(struct clk *clk)
+{
+	struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong rate = 0;
+
+	if (!priv->gpll_hz) {
+		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
+		return -ENOENT;
+	}
+
+	switch (clk->id) {
+	case PLL_APLL:
+	case ARMCLK:
+		rate = rockchip_pll_get_rate(&rk3568_pll_clks[APLL], priv->cru,
+					     APLL);
+		break;
+	case PLL_CPLL:
+		rate = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL], priv->cru,
+					     CPLL);
+		break;
+	case PLL_GPLL:
+		rate = rockchip_pll_get_rate(&rk3568_pll_clks[GPLL], priv->cru,
+					     GPLL);
+		break;
+	case PLL_NPLL:
+		rate = rockchip_pll_get_rate(&rk3568_pll_clks[NPLL], priv->cru,
+					     NPLL);
+		break;
+	case PLL_VPLL:
+		rate = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL], priv->cru,
+					     VPLL);
+		break;
+	case PLL_DPLL:
+		rate = rockchip_pll_get_rate(&rk3568_pll_clks[DPLL], priv->cru,
+					     DPLL);
+		break;
+	case ACLK_BUS:
+	case PCLK_BUS:
+	case PCLK_WDT_NS:
+		rate = rk3568_bus_get_clk(priv, clk->id);
+		break;
+	case ACLK_PERIMID:
+	case HCLK_PERIMID:
+		rate = rk3568_perimid_get_clk(priv, clk->id);
+		break;
+	case ACLK_TOP_HIGH:
+	case ACLK_TOP_LOW:
+	case HCLK_TOP:
+	case PCLK_TOP:
+		rate = rk3568_top_get_clk(priv, clk->id);
+		break;
+	case CLK_I2C1:
+	case CLK_I2C2:
+	case CLK_I2C3:
+	case CLK_I2C4:
+	case CLK_I2C5:
+		rate = rk3568_i2c_get_clk(priv, clk->id);
+		break;
+	case CLK_SPI0:
+	case CLK_SPI1:
+	case CLK_SPI2:
+	case CLK_SPI3:
+		rate = rk3568_spi_get_clk(priv, clk->id);
+		break;
+	case CLK_PWM1:
+	case CLK_PWM2:
+	case CLK_PWM3:
+		rate = rk3568_pwm_get_clk(priv, clk->id);
+		break;
+	case CLK_SARADC:
+	case CLK_TSADC_TSEN:
+	case CLK_TSADC:
+		rate = rk3568_adc_get_clk(priv, clk->id);
+		break;
+	case HCLK_SDMMC0:
+	case CLK_SDMMC0:
+	case CLK_SDMMC1:
+	case CLK_SDMMC2:
+		rate = rk3568_sdmmc_get_clk(priv, clk->id);
+		break;
+	case SCLK_SFC:
+		rate = rk3568_sfc_get_clk(priv);
+		break;
+	case NCLK_NANDC:
+		rate = rk3568_nand_get_clk(priv);
+		break;
+	case CCLK_EMMC:
+		rate = rk3568_emmc_get_clk(priv);
+		break;
+	case BCLK_EMMC:
+		rate = rk3568_emmc_get_bclk(priv);
+		break;
+#ifndef CONFIG_SPL_BUILD
+	case ACLK_VOP:
+		rate = rk3568_aclk_vop_get_clk(priv);
+		break;
+	case DCLK_VOP0:
+	case DCLK_VOP1:
+	case DCLK_VOP2:
+		rate = rk3568_dclk_vop_get_clk(priv, clk->id);
+		break;
+	case SCLK_GMAC0:
+	case CLK_MAC0_2TOP:
+	case CLK_MAC0_REFOUT:
+		rate = rk3568_gmac_src_get_clk(priv, 0);
+		break;
+	case CLK_MAC0_OUT:
+		rate = rk3568_gmac_out_get_clk(priv, 0);
+		break;
+	case CLK_GMAC0_PTP_REF:
+		rate = rk3568_gmac_ptp_ref_get_clk(priv, 0);
+		break;
+	case SCLK_GMAC1:
+	case CLK_MAC1_2TOP:
+	case CLK_MAC1_REFOUT:
+		rate = rk3568_gmac_src_get_clk(priv, 1);
+		break;
+	case CLK_MAC1_OUT:
+		rate = rk3568_gmac_out_get_clk(priv, 1);
+		break;
+	case CLK_GMAC1_PTP_REF:
+		rate = rk3568_gmac_ptp_ref_get_clk(priv, 1);
+		break;
+	case DCLK_EBC:
+		rate = rk3568_ebc_get_clk(priv);
+		break;
+	case ACLK_RKVDEC_PRE:
+	case ACLK_RKVDEC:
+	case CLK_RKVDEC_CORE:
+		rate = rk3568_rkvdec_get_clk(priv, clk->id);
+		break;
+	case TCLK_WDT_NS:
+		rate = OSC_HZ;
+		break;
+	case SCLK_UART1:
+	case SCLK_UART2:
+	case SCLK_UART3:
+	case SCLK_UART4:
+	case SCLK_UART5:
+	case SCLK_UART6:
+	case SCLK_UART7:
+	case SCLK_UART8:
+	case SCLK_UART9:
+		rate = rk3568_uart_get_rate(priv, clk->id);
+		break;
+#endif
+	case ACLK_SECURE_FLASH:
+	case ACLK_CRYPTO_NS:
+	case HCLK_SECURE_FLASH:
+	case HCLK_CRYPTO_NS:
+	case CLK_CRYPTO_NS_RNG:
+	case CLK_CRYPTO_NS_CORE:
+	case CLK_CRYPTO_NS_PKA:
+		rate = rk3568_crypto_get_rate(priv, clk->id);
+		break;
+	case CPLL_500M:
+	case CPLL_333M:
+	case CPLL_250M:
+	case CPLL_125M:
+	case CPLL_100M:
+	case CPLL_62P5M:
+	case CPLL_50M:
+	case CPLL_25M:
+		rate = rk3568_cpll_div_get_rate(priv, clk->id);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rate;
+};
+
+static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong ret = 0;
+
+	if (!priv->gpll_hz) {
+		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
+		return -ENOENT;
+	}
+
+	switch (clk->id) {
+	case PLL_APLL:
+	case ARMCLK:
+		if (priv->armclk_hz)
+			rk3568_armclk_set_clk(priv, rate);
+		priv->armclk_hz = rate;
+		break;
+	case PLL_CPLL:
+		ret = rockchip_pll_set_rate(&rk3568_pll_clks[CPLL], priv->cru,
+					    CPLL, rate);
+		priv->cpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL],
+						      priv->cru, CPLL);
+		break;
+	case PLL_GPLL:
+		ret = rockchip_pll_set_rate(&rk3568_pll_clks[GPLL], priv->cru,
+					    GPLL, rate);
+		priv->gpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[GPLL],
+						      priv->cru, GPLL);
+		break;
+	case PLL_NPLL:
+		ret = rockchip_pll_set_rate(&rk3568_pll_clks[NPLL], priv->cru,
+					    NPLL, rate);
+		break;
+	case PLL_VPLL:
+		ret = rockchip_pll_set_rate(&rk3568_pll_clks[VPLL], priv->cru,
+					    VPLL, rate);
+		priv->vpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL],
+						      priv->cru,
+						      VPLL);
+		break;
+	case ACLK_BUS:
+	case PCLK_BUS:
+	case PCLK_WDT_NS:
+		ret = rk3568_bus_set_clk(priv, clk->id, rate);
+		break;
+	case ACLK_PERIMID:
+	case HCLK_PERIMID:
+		ret = rk3568_perimid_set_clk(priv, clk->id, rate);
+		break;
+	case ACLK_TOP_HIGH:
+	case ACLK_TOP_LOW:
+	case HCLK_TOP:
+	case PCLK_TOP:
+		ret = rk3568_top_set_clk(priv, clk->id, rate);
+		break;
+	case CLK_I2C1:
+	case CLK_I2C2:
+	case CLK_I2C3:
+	case CLK_I2C4:
+	case CLK_I2C5:
+		ret = rk3568_i2c_set_clk(priv, clk->id, rate);
+		break;
+	case CLK_SPI0:
+	case CLK_SPI1:
+	case CLK_SPI2:
+	case CLK_SPI3:
+		ret = rk3568_spi_set_clk(priv, clk->id, rate);
+		break;
+	case CLK_PWM1:
+	case CLK_PWM2:
+	case CLK_PWM3:
+		ret = rk3568_pwm_set_clk(priv, clk->id, rate);
+		break;
+	case CLK_SARADC:
+	case CLK_TSADC_TSEN:
+	case CLK_TSADC:
+		ret = rk3568_adc_set_clk(priv, clk->id, rate);
+		break;
+	case HCLK_SDMMC0:
+	case CLK_SDMMC0:
+	case CLK_SDMMC1:
+	case CLK_SDMMC2:
+		ret = rk3568_sdmmc_set_clk(priv, clk->id, rate);
+		break;
+	case SCLK_SFC:
+		ret = rk3568_sfc_set_clk(priv, rate);
+		break;
+	case NCLK_NANDC:
+		ret = rk3568_nand_set_clk(priv, rate);
+		break;
+	case CCLK_EMMC:
+		ret = rk3568_emmc_set_clk(priv, rate);
+		break;
+	case BCLK_EMMC:
+		ret = rk3568_emmc_set_bclk(priv, rate);
+		break;
+#ifndef CONFIG_SPL_BUILD
+	case ACLK_VOP:
+		ret = rk3568_aclk_vop_set_clk(priv, rate);
+		break;
+	case DCLK_VOP0:
+	case DCLK_VOP1:
+	case DCLK_VOP2:
+		ret = rk3568_dclk_vop_set_clk(priv, clk->id, rate);
+		break;
+	case SCLK_GMAC0:
+	case CLK_MAC0_2TOP:
+	case CLK_MAC0_REFOUT:
+		ret = rk3568_gmac_src_set_clk(priv, 0, rate);
+		break;
+	case CLK_MAC0_OUT:
+		ret = rk3568_gmac_out_set_clk(priv, 0, rate);
+		break;
+	case SCLK_GMAC0_RX_TX:
+		ret = rk3568_gmac_tx_rx_set_clk(priv, 0, rate);
+		break;
+	case CLK_GMAC0_PTP_REF:
+		ret = rk3568_gmac_ptp_ref_set_clk(priv, 0, rate);
+		break;
+	case SCLK_GMAC1:
+	case CLK_MAC1_2TOP:
+	case CLK_MAC1_REFOUT:
+		ret = rk3568_gmac_src_set_clk(priv, 1, rate);
+		break;
+	case CLK_MAC1_OUT:
+		ret = rk3568_gmac_out_set_clk(priv, 1, rate);
+		break;
+	case SCLK_GMAC1_RX_TX:
+		ret = rk3568_gmac_tx_rx_set_clk(priv, 1, rate);
+		break;
+	case CLK_GMAC1_PTP_REF:
+		ret = rk3568_gmac_ptp_ref_set_clk(priv, 1, rate);
+		break;
+	case DCLK_EBC:
+		ret = rk3568_ebc_set_clk(priv, rate);
+		break;
+	case ACLK_RKVDEC_PRE:
+	case ACLK_RKVDEC:
+	case CLK_RKVDEC_CORE:
+		ret = rk3568_rkvdec_set_clk(priv, clk->id, rate);
+		break;
+	case TCLK_WDT_NS:
+		ret = OSC_HZ;
+		break;
+	case SCLK_UART1:
+	case SCLK_UART2:
+	case SCLK_UART3:
+	case SCLK_UART4:
+	case SCLK_UART5:
+	case SCLK_UART6:
+	case SCLK_UART7:
+	case SCLK_UART8:
+	case SCLK_UART9:
+		ret = rk3568_uart_set_rate(priv, clk->id, rate);
+		break;
+#endif
+	case ACLK_SECURE_FLASH:
+	case ACLK_CRYPTO_NS:
+	case HCLK_SECURE_FLASH:
+	case HCLK_CRYPTO_NS:
+	case CLK_CRYPTO_NS_RNG:
+	case CLK_CRYPTO_NS_CORE:
+	case CLK_CRYPTO_NS_PKA:
+		ret = rk3568_crypto_set_rate(priv, clk->id, rate);
+		break;
+	case CPLL_500M:
+	case CPLL_333M:
+	case CPLL_250M:
+	case CPLL_125M:
+	case CPLL_100M:
+	case CPLL_62P5M:
+	case CPLL_50M:
+	case CPLL_25M:
+		ret = rk3568_cpll_div_set_rate(priv, clk->id, rate);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return ret;
+};
+
+#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
+static int rk3568_gmac0_src_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
+	struct rk3568_cru *cru = priv->cru;
+
+	if (parent->id == CLK_MAC0_2TOP)
+		rk_clrsetreg(&cru->clksel_con[31],
+			     RMII0_EXTCLK_SEL_MASK,
+			     RMII0_EXTCLK_SEL_MAC0_TOP <<
+			     RMII0_EXTCLK_SEL_SHIFT);
+	else
+		rk_clrsetreg(&cru->clksel_con[31],
+			     RMII0_EXTCLK_SEL_MASK,
+			     RMII0_EXTCLK_SEL_IO << RMII0_EXTCLK_SEL_SHIFT);
+	return 0;
+}
+
+static int rk3568_gmac1_src_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
+	struct rk3568_cru *cru = priv->cru;
+
+	if (parent->id == CLK_MAC1_2TOP)
+		rk_clrsetreg(&cru->clksel_con[33],
+			     RMII0_EXTCLK_SEL_MASK,
+			     RMII0_EXTCLK_SEL_MAC0_TOP <<
+			     RMII0_EXTCLK_SEL_SHIFT);
+	else
+		rk_clrsetreg(&cru->clksel_con[33],
+			     RMII0_EXTCLK_SEL_MASK,
+			     RMII0_EXTCLK_SEL_IO << RMII0_EXTCLK_SEL_SHIFT);
+	return 0;
+}
+
+static int rk3568_gmac0_tx_rx_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
+	struct rk3568_cru *cru = priv->cru;
+
+	if (parent->id == SCLK_GMAC0_RGMII_SPEED)
+		rk_clrsetreg(&cru->clksel_con[31],
+			     RMII0_MODE_MASK,
+			     RMII0_MODE_SEL_RGMII << RMII0_MODE_SHIFT);
+	else if (parent->id == SCLK_GMAC0_RMII_SPEED)
+		rk_clrsetreg(&cru->clksel_con[31],
+			     RMII0_MODE_MASK,
+			     RMII0_MODE_SEL_RMII << RMII0_MODE_SHIFT);
+	else
+		rk_clrsetreg(&cru->clksel_con[31],
+			     RMII0_MODE_MASK,
+			     RMII0_MODE_SEL_GMII << RMII0_MODE_SHIFT);
+
+	return 0;
+}
+
+static int rk3568_gmac1_tx_rx_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
+	struct rk3568_cru *cru = priv->cru;
+
+	if (parent->id == SCLK_GMAC1_RGMII_SPEED)
+		rk_clrsetreg(&cru->clksel_con[33],
+			     RMII0_MODE_MASK,
+			     RMII0_MODE_SEL_RGMII << RMII0_MODE_SHIFT);
+	else if (parent->id == SCLK_GMAC1_RMII_SPEED)
+		rk_clrsetreg(&cru->clksel_con[33],
+			     RMII0_MODE_MASK,
+			     RMII0_MODE_SEL_RMII << RMII0_MODE_SHIFT);
+	else
+		rk_clrsetreg(&cru->clksel_con[33],
+			     RMII0_MODE_MASK,
+			     RMII0_MODE_SEL_GMII << RMII0_MODE_SHIFT);
+
+	return 0;
+}
+
+static int rk3568_dclk_vop_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
+	struct rk3568_cru *cru = priv->cru;
+	u32 con_id;
+
+	switch (clk->id) {
+	case DCLK_VOP0:
+		con_id = 39;
+		break;
+	case DCLK_VOP1:
+		con_id = 40;
+		break;
+	case DCLK_VOP2:
+		con_id = 41;
+		break;
+	default:
+		return -EINVAL;
+	}
+	if (parent->id == PLL_VPLL) {
+		rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
+			     DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT);
+	} else {
+		rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
+			     DCLK_VOP_SEL_HPLL << DCLK0_VOP_SEL_SHIFT);
+	}
+
+	return 0;
+}
+
+static int rk3568_rkvdec_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
+	struct rk3568_cru *cru = priv->cru;
+	u32 con_id, mask, shift;
+
+	switch (clk->id) {
+	case ACLK_RKVDEC_PRE:
+		con_id = 47;
+		mask = ACLK_RKVDEC_SEL_MASK;
+		shift = ACLK_RKVDEC_SEL_SHIFT;
+		break;
+	case CLK_RKVDEC_CORE:
+		con_id = 49;
+		mask = CLK_RKVDEC_CORE_SEL_MASK;
+		shift = CLK_RKVDEC_CORE_SEL_SHIFT;
+		break;
+	default:
+		return -EINVAL;
+	}
+	if (parent->id == PLL_CPLL) {
+		rk_clrsetreg(&cru->clksel_con[con_id], mask,
+			     ACLK_RKVDEC_SEL_CPLL << shift);
+	} else {
+		rk_clrsetreg(&cru->clksel_con[con_id], mask,
+			     ACLK_RKVDEC_SEL_GPLL << shift);
+	}
+
+	return 0;
+}
+
+static int rk3568_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	switch (clk->id) {
+	case SCLK_GMAC0:
+		return rk3568_gmac0_src_set_parent(clk, parent);
+	case SCLK_GMAC1:
+		return rk3568_gmac1_src_set_parent(clk, parent);
+	case SCLK_GMAC0_RX_TX:
+		return rk3568_gmac0_tx_rx_set_parent(clk, parent);
+	case SCLK_GMAC1_RX_TX:
+		return rk3568_gmac1_tx_rx_set_parent(clk, parent);
+	case DCLK_VOP0:
+	case DCLK_VOP1:
+	case DCLK_VOP2:
+		return rk3568_dclk_vop_set_parent(clk, parent);
+	case ACLK_RKVDEC_PRE:
+	case CLK_RKVDEC_CORE:
+		return rk3568_rkvdec_set_parent(clk, parent);
+	default:
+		return -ENOENT;
+	}
+
+	return 0;
+}
+#endif
+
+static struct clk_ops rk3568_clk_ops = {
+	.get_rate = rk3568_clk_get_rate,
+	.set_rate = rk3568_clk_set_rate,
+#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
+	.set_parent = rk3568_clk_set_parent,
+#endif
+};
+
+static void rk3568_clk_init(struct rk3568_clk_priv *priv)
+{
+	int ret;
+
+	priv->sync_kernel = false;
+	if (!priv->armclk_enter_hz) {
+		priv->armclk_enter_hz =
+			rockchip_pll_get_rate(&rk3568_pll_clks[APLL],
+					      priv->cru, APLL);
+		priv->armclk_init_hz = priv->armclk_enter_hz;
+	}
+
+	if (priv->armclk_init_hz != APLL_HZ) {
+		ret = rk3568_armclk_set_clk(priv, APLL_HZ);
+		if (!ret)
+			priv->armclk_init_hz = APLL_HZ;
+	}
+	if (priv->cpll_hz != CPLL_HZ) {
+		ret = rockchip_pll_set_rate(&rk3568_pll_clks[CPLL], priv->cru,
+					    CPLL, CPLL_HZ);
+		if (!ret)
+			priv->cpll_hz = CPLL_HZ;
+	}
+	if (priv->gpll_hz != GPLL_HZ) {
+		ret = rockchip_pll_set_rate(&rk3568_pll_clks[GPLL], priv->cru,
+					    GPLL, GPLL_HZ);
+		if (!ret)
+			priv->gpll_hz = GPLL_HZ;
+	}
+
+#ifdef CONFIG_SPL_BUILD
+	ret = rk3568_bus_set_clk(priv, ACLK_BUS, 150000000);
+	if (ret < 0)
+		printf("Fail to set the ACLK_BUS clock.\n");
+#endif
+
+	priv->ppll_hz = rk3568_pmu_pll_get_rate(priv, PPLL);
+	priv->hpll_hz = rk3568_pmu_pll_get_rate(priv, HPLL);
+}
+
+static int rk3568_clk_probe(struct udevice *dev)
+{
+	struct rk3568_clk_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (IS_ERR(priv->grf))
+		return PTR_ERR(priv->grf);
+
+	rk3568_clk_init(priv);
+
+	/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
+	ret = clk_set_defaults(dev, 1);
+	if (ret)
+		debug("%s clk_set_defaults failed %d\n", __func__, ret);
+	else
+		priv->sync_kernel = true;
+
+	return 0;
+}
+
+static int rk3568_clk_ofdata_to_platdata(struct udevice *dev)
+{
+	struct rk3568_clk_priv *priv = dev_get_priv(dev);
+
+	priv->cru = dev_read_addr_ptr(dev);
+
+	return 0;
+}
+
+static int rk3568_clk_bind(struct udevice *dev)
+{
+	int ret;
+	struct udevice *sys_child;
+	struct sysreset_reg *priv;
+
+	/* The reset driver does not have a device node, so bind it here */
+	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+				 &sys_child);
+	if (ret) {
+		debug("Warning: No sysreset driver: ret=%d\n", ret);
+	} else {
+		priv = malloc(sizeof(struct sysreset_reg));
+		priv->glb_srst_fst_value = offsetof(struct rk3568_cru,
+						    glb_srst_fst);
+		priv->glb_srst_snd_value = offsetof(struct rk3568_cru,
+						    glb_srsr_snd);
+	}
+
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
+	ret = offsetof(struct rk3568_cru, softrst_con[0]);
+	ret = rockchip_reset_bind(dev, ret, 30);
+	if (ret)
+		debug("Warning: software reset driver bind faile\n");
+#endif
+
+	return 0;
+}
+
+static const struct udevice_id rk3568_clk_ids[] = {
+	{ .compatible = "rockchip,rk3568-cru" },
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_rk3568_cru) = {
+	.name		= "rockchip_rk3568_cru",
+	.id		= UCLASS_CLK,
+	.of_match	= rk3568_clk_ids,
+	.priv_auto = sizeof(struct rk3568_clk_priv),
+	.of_to_plat = rk3568_clk_ofdata_to_platdata,
+	.ops		= &rk3568_clk_ops,
+	.bind		= rk3568_clk_bind,
+	.probe		= rk3568_clk_probe,
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	.plat_auto	= sizeof(struct rk3568_clk_plat),
+#endif
+};
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index ed151ee..a901ce5 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -333,6 +333,22 @@ config CORTINA_NAND
 	  The controller supports a maximum 8k page size and supports
 	  a maximum 40-bit error correction per sector of 1024 bytes.
 
+config ROCKCHIP_NAND
+	bool "Support for NAND controller on Rockchip SoCs"
+	depends on ARCH_ROCKCHIP
+	select SYS_NAND_SELF_INIT
+	select DM_MTD
+	imply CMD_NAND
+	help
+	  Enables support for NAND Flash chips on Rockchip SoCs platform.
+	  This controller is found on Rockchip SoCs.
+	  There are four different versions of NAND FLASH Controllers,
+	  including:
+	    NFC v600: RK2928, RK3066, RK3188
+	    NFC v622: RK3036, RK3128
+	    NFC v800: RK3308, RV1108
+	    NFC v900: PX30, RK3326
+
 comment "Generic NAND options"
 
 config SYS_NAND_BLOCK_SIZE
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index f3f0e15..a5ed2c5 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -70,6 +70,7 @@ obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
 obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
 obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o
 obj-$(CONFIG_CORTINA_NAND) += cortina_nand.o
+obj-$(CONFIG_ROCKCHIP_NAND) += rockchip_nfc.o
 
 else  # minimal SPL drivers
 
diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c b/drivers/mtd/nand/raw/rockchip_nfc.c
new file mode 100644
index 0000000..21776f3
--- /dev/null
+++ b/drivers/mtd/nand/raw/rockchip_nfc.c
@@ -0,0 +1,1253 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Rockchip NAND Flash controller driver.
+ * Copyright (C) 2021 Rockchip Inc.
+ * Author: Yifeng Zhao <yifeng.zhao@rock-chips.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <fdtdec.h>
+#include <inttypes.h>
+#include <linux/delay.h>
+#include <linux/dma-direction.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <memalign.h>
+#include <nand.h>
+
+/*
+ * NFC Page Data Layout:
+ *	1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data +
+ *	1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data +
+ *	......
+ * NAND Page Data Layout:
+ *	1024 * n data + m Bytes oob
+ * Original Bad Block Mask Location:
+ *	First byte of oob(spare).
+ * nand_chip->oob_poi data layout:
+ *	4Bytes sys data + .... + 4Bytes sys data + ECC data.
+ */
+
+/* NAND controller register definition */
+#define NFC_READ			(0)
+#define NFC_WRITE			(1)
+
+#define NFC_FMCTL			(0x00)
+#define   FMCTL_CE_SEL_M		0xFF
+#define   FMCTL_CE_SEL(x)		(1 << (x))
+#define   FMCTL_WP			BIT(8)
+#define   FMCTL_RDY			BIT(9)
+
+#define NFC_FMWAIT			(0x04)
+#define   FLCTL_RST			BIT(0)
+#define   FLCTL_WR			(1)	/* 0: read, 1: write */
+#define   FLCTL_XFER_ST			BIT(2)
+#define   FLCTL_XFER_EN			BIT(3)
+#define   FLCTL_ACORRECT		BIT(10) /* Auto correct error bits. */
+#define   FLCTL_XFER_READY		BIT(20)
+#define   FLCTL_XFER_SECTOR		(22)
+#define   FLCTL_TOG_FIX			BIT(29)
+
+#define   BCHCTL_BANK_M			(7 << 5)
+#define   BCHCTL_BANK			(5)
+
+#define   DMA_ST			BIT(0)
+#define   DMA_WR			(1)	/* 0: write, 1: read */
+#define   DMA_EN			BIT(2)
+#define   DMA_AHB_SIZE			(3)	/* 0: 1, 1: 2, 2: 4 */
+#define   DMA_BURST_SIZE		(6)	/* 0: 1, 3: 4, 5: 8, 7: 16 */
+#define   DMA_INC_NUM			(9)	/* 1 - 16 */
+
+#define ECC_ERR_CNT(x, e) ((((x) >> (e).low) & (e).low_mask) |\
+		(((x) >> (e).high) & (e).high_mask) << (e).low_bn)
+#define   INT_DMA			BIT(0)
+#define NFC_BANK			(0x800)
+#define NFC_BANK_STEP			(0x100)
+#define   BANK_DATA			(0x00)
+#define   BANK_ADDR			(0x04)
+#define   BANK_CMD			(0x08)
+#define NFC_SRAM0			(0x1000)
+#define NFC_SRAM1			(0x1400)
+#define NFC_SRAM_SIZE			(0x400)
+#define NFC_TIMEOUT_MS			(500)
+#define NFC_MAX_OOB_PER_STEP		128
+#define NFC_MIN_OOB_PER_STEP		64
+#define MAX_DATA_SIZE			0xFFFC
+#define MAX_ADDRESS_CYC			6
+#define NFC_ECC_MAX_MODES		4
+#define NFC_RB_DELAY_US			50
+#define NFC_MAX_PAGE_SIZE		(16 * 1024)
+#define NFC_MAX_OOB_SIZE		(16 * 128)
+#define NFC_MAX_NSELS			(8) /* Some Socs only have 1 or 2 CSs. */
+#define NFC_SYS_DATA_SIZE		(4) /* 4 bytes sys data in oob pre 1024 data.*/
+#define RK_DEFAULT_CLOCK_RATE		(150 * 1000 * 1000) /* 150 Mhz */
+#define ACCTIMING(csrw, rwpw, rwcs)	((csrw) << 12 | (rwpw) << 5 | (rwcs))
+
+enum nfc_type {
+	NFC_V6,
+	NFC_V8,
+	NFC_V9,
+};
+
+/**
+ * struct rk_ecc_cnt_status: represent a ecc status data.
+ * @err_flag_bit: error flag bit index at register.
+ * @low: ECC count low bit index at register.
+ * @low_mask: mask bit.
+ * @low_bn: ECC count low bit number.
+ * @high: ECC count high bit index at register.
+ * @high_mask: mask bit
+ */
+struct ecc_cnt_status {
+	u8 err_flag_bit;
+	u8 low;
+	u8 low_mask;
+	u8 low_bn;
+	u8 high;
+	u8 high_mask;
+};
+
+/**
+ * @type: NFC version
+ * @ecc_strengths: ECC strengths
+ * @ecc_cfgs: ECC config values
+ * @flctl_off: FLCTL register offset
+ * @bchctl_off: BCHCTL register offset
+ * @dma_data_buf_off: DMA_DATA_BUF register offset
+ * @dma_oob_buf_off: DMA_OOB_BUF register offset
+ * @dma_cfg_off: DMA_CFG register offset
+ * @dma_st_off: DMA_ST register offset
+ * @bch_st_off: BCG_ST register offset
+ * @randmz_off: RANDMZ register offset
+ * @int_en_off: interrupt enable register offset
+ * @int_clr_off: interrupt clean register offset
+ * @int_st_off: interrupt status register offset
+ * @oob0_off: oob0 register offset
+ * @oob1_off: oob1 register offset
+ * @ecc0: represent ECC0 status data
+ * @ecc1: represent ECC1 status data
+ */
+struct nfc_cfg {
+	enum nfc_type type;
+	u8 ecc_strengths[NFC_ECC_MAX_MODES];
+	u32 ecc_cfgs[NFC_ECC_MAX_MODES];
+	u32 flctl_off;
+	u32 bchctl_off;
+	u32 dma_cfg_off;
+	u32 dma_data_buf_off;
+	u32 dma_oob_buf_off;
+	u32 dma_st_off;
+	u32 bch_st_off;
+	u32 randmz_off;
+	u32 int_en_off;
+	u32 int_clr_off;
+	u32 int_st_off;
+	u32 oob0_off;
+	u32 oob1_off;
+	struct ecc_cnt_status ecc0;
+	struct ecc_cnt_status ecc1;
+};
+
+struct rk_nfc_nand_chip {
+	struct nand_chip chip;
+
+	u16 boot_blks;
+	u16 metadata_size;
+	u32 boot_ecc;
+	u32 timing;
+
+	u8 nsels;
+	u8 sels[0];
+	/* Nothing after this field. */
+};
+
+struct rk_nfc {
+	struct nand_hw_control controller;
+	const struct nfc_cfg *cfg;
+	struct udevice *dev;
+
+	struct clk *nfc_clk;
+	struct clk *ahb_clk;
+	void __iomem *regs;
+
+	int selected_bank;
+	u32 band_offset;
+	u32 cur_ecc;
+	u32 cur_timing;
+
+	u8 *page_buf;
+	u32 *oob_buf;
+
+	unsigned long assigned_cs;
+};
+
+static inline struct rk_nfc_nand_chip *rk_nfc_to_rknand(struct nand_chip *chip)
+{
+	return container_of(chip, struct rk_nfc_nand_chip, chip);
+}
+
+static inline u8 *rk_nfc_buf_to_data_ptr(struct nand_chip *chip, const u8 *p, int i)
+{
+	return (u8 *)p + i * chip->ecc.size;
+}
+
+static inline u8 *rk_nfc_buf_to_oob_ptr(struct nand_chip *chip, int i)
+{
+	u8 *poi;
+
+	poi = chip->oob_poi + i * NFC_SYS_DATA_SIZE;
+
+	return poi;
+}
+
+static inline u8 *rk_nfc_buf_to_oob_ecc_ptr(struct nand_chip *chip, int i)
+{
+	struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
+	u8 *poi;
+
+	poi = chip->oob_poi + rknand->metadata_size + chip->ecc.bytes * i;
+
+	return poi;
+}
+
+static inline int rk_nfc_data_len(struct nand_chip *chip)
+{
+	return chip->ecc.size + chip->ecc.bytes + NFC_SYS_DATA_SIZE;
+}
+
+static inline u8 *rk_nfc_data_ptr(struct nand_chip *chip, int i)
+{
+	struct rk_nfc *nfc = nand_get_controller_data(chip);
+
+	return nfc->page_buf + i * rk_nfc_data_len(chip);
+}
+
+static inline u8 *rk_nfc_oob_ptr(struct nand_chip *chip, int i)
+{
+	struct rk_nfc *nfc = nand_get_controller_data(chip);
+
+	return nfc->page_buf + i * rk_nfc_data_len(chip) + chip->ecc.size;
+}
+
+static int rk_nfc_hw_ecc_setup(struct nand_chip *chip, u32 strength)
+{
+	struct rk_nfc *nfc = nand_get_controller_data(chip);
+	u32 reg, i;
+
+	for (i = 0; i < NFC_ECC_MAX_MODES; i++) {
+		if (strength == nfc->cfg->ecc_strengths[i]) {
+			reg = nfc->cfg->ecc_cfgs[i];
+			break;
+		}
+	}
+
+	if (i >= NFC_ECC_MAX_MODES)
+		return -EINVAL;
+
+	writel(reg, nfc->regs + nfc->cfg->bchctl_off);
+
+	/* Save chip ECC setting */
+	nfc->cur_ecc = strength;
+
+	return 0;
+}
+
+static void rk_nfc_select_chip(struct mtd_info *mtd, int cs)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct rk_nfc *nfc = nand_get_controller_data(chip);
+	struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+	u32 val;
+
+	if (cs < 0) {
+		nfc->selected_bank = -1;
+		/* Deselect the currently selected target. */
+		val = readl(nfc->regs + NFC_FMCTL);
+		val &= ~FMCTL_CE_SEL_M;
+		writel(val, nfc->regs + NFC_FMCTL);
+		return;
+	}
+
+	nfc->selected_bank = rknand->sels[cs];
+	nfc->band_offset = NFC_BANK + nfc->selected_bank * NFC_BANK_STEP;
+
+	val = readl(nfc->regs + NFC_FMCTL);
+	val &= ~FMCTL_CE_SEL_M;
+	val |= FMCTL_CE_SEL(nfc->selected_bank);
+
+	writel(val, nfc->regs + NFC_FMCTL);
+
+	/*
+	 * Compare current chip timing with selected chip timing and
+	 * change if needed.
+	 */
+	if (nfc->cur_timing != rknand->timing) {
+		writel(rknand->timing, nfc->regs + NFC_FMWAIT);
+		nfc->cur_timing = rknand->timing;
+	}
+
+	/*
+	 * Compare current chip ECC setting with selected chip ECC setting and
+	 * change if needed.
+	 */
+	if (nfc->cur_ecc != ecc->strength)
+		rk_nfc_hw_ecc_setup(chip, ecc->strength);
+}
+
+static inline int rk_nfc_wait_ioready(struct rk_nfc *nfc)
+{
+	u32 timeout = (CONFIG_SYS_HZ * NFC_TIMEOUT_MS) / 1000;
+	u32 time_start;
+
+	time_start = get_timer(0);
+	do {
+		if (readl(nfc->regs + NFC_FMCTL) & FMCTL_RDY)
+			return 0;
+	} while (get_timer(time_start) < timeout);
+
+	dev_err(nfc->dev, "wait for io ready timedout\n");
+	return -ETIMEDOUT;
+}
+
+static void rk_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct rk_nfc *nfc = nand_get_controller_data(chip);
+	void __iomem *bank_base;
+	int i = 0;
+
+	bank_base = nfc->regs + nfc->band_offset + BANK_DATA;
+
+	for (i = 0; i < len; i++)
+		buf[i] = readl(bank_base);
+}
+
+static void rk_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct rk_nfc *nfc = nand_get_controller_data(chip);
+	void __iomem *bank_base;
+	int i = 0;
+
+	bank_base = nfc->regs + nfc->band_offset + BANK_DATA;
+
+	for (i = 0; i < len; i++)
+		writel(buf[i], bank_base);
+}
+
+static void rk_nfc_cmd(struct mtd_info *mtd, int dat, unsigned int ctrl)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct rk_nfc *nfc = nand_get_controller_data(chip);
+	void __iomem *bank_base;
+
+	bank_base = nfc->regs + nfc->band_offset;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if (ctrl & NAND_ALE)
+			bank_base += BANK_ADDR;
+		else if (ctrl & NAND_CLE)
+			bank_base += BANK_CMD;
+		chip->IO_ADDR_W = bank_base;
+	}
+
+	if (dat != NAND_CMD_NONE)
+		writel(dat & 0xFF, chip->IO_ADDR_W);
+}
+
+static uint8_t rockchip_nand_read_byte(struct mtd_info *mtd)
+{
+	uint8_t ret;
+
+	rk_nfc_read_buf(mtd, &ret, 1);
+
+	return ret;
+}
+
+static int rockchip_nand_dev_ready(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct rk_nfc *nfc = nand_get_controller_data(chip);
+
+	if (readl(nfc->regs + NFC_FMCTL) & FMCTL_RDY)
+		return 1;
+
+	return 0;
+}
+
+static void rk_nfc_xfer_start(struct rk_nfc *nfc, u8 rw, u8 n_KB,
+			      dma_addr_t dma_data, dma_addr_t dma_oob)
+{
+	u32 dma_reg, fl_reg, bch_reg;
+
+	dma_reg = DMA_ST | ((!rw) << DMA_WR) | DMA_EN | (2 << DMA_AHB_SIZE) |
+	      (7 << DMA_BURST_SIZE) | (16 << DMA_INC_NUM);
+
+	fl_reg = (rw << FLCTL_WR) | FLCTL_XFER_EN | FLCTL_ACORRECT |
+		 (n_KB << FLCTL_XFER_SECTOR) | FLCTL_TOG_FIX;
+
+	if (nfc->cfg->type == NFC_V6 || nfc->cfg->type == NFC_V8) {
+		bch_reg = readl_relaxed(nfc->regs + nfc->cfg->bchctl_off);
+		bch_reg = (bch_reg & (~BCHCTL_BANK_M)) |
+			  (nfc->selected_bank << BCHCTL_BANK);
+		writel(bch_reg, nfc->regs + nfc->cfg->bchctl_off);
+	}
+
+	writel(dma_reg, nfc->regs + nfc->cfg->dma_cfg_off);
+	writel((u32)dma_data, nfc->regs + nfc->cfg->dma_data_buf_off);
+	writel((u32)dma_oob, nfc->regs + nfc->cfg->dma_oob_buf_off);
+	writel(fl_reg, nfc->regs + nfc->cfg->flctl_off);
+	fl_reg |= FLCTL_XFER_ST;
+	writel(fl_reg, nfc->regs + nfc->cfg->flctl_off);
+}
+
+static int rk_nfc_wait_for_xfer_done(struct rk_nfc *nfc)
+{
+	unsigned long timeout = (CONFIG_SYS_HZ * NFC_TIMEOUT_MS) / 1000;
+	void __iomem *ptr = nfc->regs + nfc->cfg->flctl_off;
+	u32 time_start;
+
+	time_start = get_timer(0);
+
+	do {
+		if (readl(ptr) & FLCTL_XFER_READY)
+			return 0;
+	} while (get_timer(time_start) < timeout);
+
+	dev_err(nfc->dev, "wait for io ready timedout\n");
+	return -ETIMEDOUT;
+}
+
+static int rk_nfc_write_page_raw(struct mtd_info *mtd,
+				 struct nand_chip *chip,
+				 const u8 *buf,
+				 int oob_required,
+				 int page)
+{
+	struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
+	struct rk_nfc *nfc = nand_get_controller_data(chip);
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+	int i, pages_per_blk;
+
+	pages_per_blk = mtd->erasesize / mtd->writesize;
+	if ((page < (pages_per_blk * rknand->boot_blks)) &&
+	    rknand->boot_ecc != ecc->strength) {
+		/*
+		 * There's currently no method to notify the MTD framework that
+		 * a different ECC strength is in use for the boot blocks.
+		 */
+		return -EIO;
+	}
+
+	if (!buf)
+		memset(nfc->page_buf, 0xff, mtd->writesize + mtd->oobsize);
+
+	for (i = 0; i < ecc->steps; i++) {
+		/* Copy data to the NFC buffer. */
+		if (buf)
+			memcpy(rk_nfc_data_ptr(chip, i),
+			       rk_nfc_buf_to_data_ptr(chip, buf, i),
+			       ecc->size);
+		/*
+		 * The first four bytes of OOB are reserved for the
+		 * boot ROM. In some debugging cases, such as with a
+		 * read, erase and write back test these 4 bytes stored
+		 * in OOB also need to be written back.
+		 *
+		 * The function nand_block_bad detects bad blocks like:
+		 *
+		 * bad = chip->oob_poi[chip->badblockpos];
+		 *
+		 * chip->badblockpos == 0 for a large page NAND Flash,
+		 * so chip->oob_poi[0] is the bad block mask (BBM).
+		 *
+		 * The OOB data layout on the NFC is:
+		 *
+		 *    PA0  PA1  PA2  PA3  | BBM OOB1 OOB2 OOB3 | ...
+		 *
+		 * or
+		 *
+		 *    0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ...
+		 *
+		 * The code here just swaps the first 4 bytes with the last
+		 * 4 bytes without losing any data.
+		 *
+		 * The chip->oob_poi data layout:
+		 *
+		 *    BBM  OOB1 OOB2 OOB3 |......|  PA0  PA1  PA2  PA3
+		 *
+		 * The rk_nfc_ooblayout_free() function already has reserved
+		 * these 4 bytes with:
+		 *
+		 * oob_region->offset = NFC_SYS_DATA_SIZE + 2;
+		 */
+		if (!i)
+			memcpy(rk_nfc_oob_ptr(chip, i),
+			       rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1),
+			       NFC_SYS_DATA_SIZE);
+		else
+			memcpy(rk_nfc_oob_ptr(chip, i),
+			       rk_nfc_buf_to_oob_ptr(chip, i - 1),
+			       NFC_SYS_DATA_SIZE);
+		/* Copy ECC data to the NFC buffer. */
+		memcpy(rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE,
+		       rk_nfc_buf_to_oob_ecc_ptr(chip, i),
+		       ecc->bytes);
+	}
+
+	nand_prog_page_begin_op(chip, page, 0, NULL, 0);
+	rk_nfc_write_buf(mtd, buf, mtd->writesize + mtd->oobsize);
+	return nand_prog_page_end_op(chip);
+}
+
+static int rk_nfc_write_page_hwecc(struct mtd_info *mtd,
+				   struct nand_chip *chip,
+				   const u8 *buf,
+				   int oob_required,
+				   int page)
+{
+	struct rk_nfc *nfc = nand_get_controller_data(chip);
+	struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+	int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP :
+			NFC_MIN_OOB_PER_STEP;
+	int pages_per_blk = mtd->erasesize / mtd->writesize;
+	int ret = 0, i, boot_rom_mode = 0;
+	dma_addr_t dma_data, dma_oob;
+	u32 reg;
+	u8 *oob;
+
+	nand_prog_page_begin_op(chip, page, 0, NULL, 0);
+
+	if (buf)
+		memcpy(nfc->page_buf, buf, mtd->writesize);
+	else
+		memset(nfc->page_buf, 0xFF, mtd->writesize);
+
+	/*
+	 * The first blocks (4, 8 or 16 depending on the device) are used
+	 * by the boot ROM and the first 32 bits of OOB need to link to
+	 * the next page address in the same block. We can't directly copy
+	 * OOB data from the MTD framework, because this page address
+	 * conflicts for example with the bad block marker (BBM),
+	 * so we shift all OOB data including the BBM with 4 byte positions.
+	 * As a consequence the OOB size available to the MTD framework is
+	 * also reduced with 4 bytes.
+	 *
+	 *    PA0  PA1  PA2  PA3 | BBM OOB1 OOB2 OOB3 | ...
+	 *
+	 * If a NAND is not a boot medium or the page is not a boot block,
+	 * the first 4 bytes are left untouched by writing 0xFF to them.
+	 *
+	 *   0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ...
+	 *
+	 * Configure the ECC algorithm supported by the boot ROM.
+	 */
+	if (page < (pages_per_blk * rknand->boot_blks)) {
+		boot_rom_mode = 1;
+		if (rknand->boot_ecc != ecc->strength)
+			rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc);
+	}
+
+	for (i = 0; i < ecc->steps; i++) {
+		if (!i) {
+			reg = 0xFFFFFFFF;
+		} else {
+			oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
+			reg = oob[0] | oob[1] << 8 | oob[2] << 16 |
+			      oob[3] << 24;
+		}
+
+		if (!i && boot_rom_mode)
+			reg = (page & (pages_per_blk - 1)) * 4;
+
+		if (nfc->cfg->type == NFC_V9)
+			nfc->oob_buf[i] = reg;
+		else
+			nfc->oob_buf[i * (oob_step / 4)] = reg;
+	}
+
+	dma_data = dma_map_single((void *)nfc->page_buf,
+				  mtd->writesize, DMA_TO_DEVICE);
+	dma_oob = dma_map_single(nfc->oob_buf,
+				 ecc->steps * oob_step,
+				 DMA_TO_DEVICE);
+
+	rk_nfc_xfer_start(nfc, NFC_WRITE, ecc->steps, dma_data,
+			  dma_oob);
+	ret = rk_nfc_wait_for_xfer_done(nfc);
+
+	dma_unmap_single(dma_data, mtd->writesize,
+			 DMA_TO_DEVICE);
+	dma_unmap_single(dma_oob, ecc->steps * oob_step,
+			 DMA_TO_DEVICE);
+
+	if (boot_rom_mode && rknand->boot_ecc != ecc->strength)
+		rk_nfc_hw_ecc_setup(chip, ecc->strength);
+
+	if (ret) {
+		dev_err(nfc->dev, "write: wait transfer done timeout.\n");
+		return -ETIMEDOUT;
+	}
+
+	return nand_prog_page_end_op(chip);
+}
+
+static int rk_nfc_write_oob(struct mtd_info *mtd,
+			    struct nand_chip *chip, int page)
+{
+	return rk_nfc_write_page_hwecc(mtd, chip, NULL, 1, page);
+}
+
+static int rk_nfc_read_page_raw(struct mtd_info *mtd,
+				struct nand_chip *chip,
+				u8 *buf,
+				int oob_required,
+				int page)
+{
+	struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
+	struct rk_nfc *nfc = nand_get_controller_data(chip);
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+	int i, pages_per_blk;
+
+	pages_per_blk = mtd->erasesize / mtd->writesize;
+	if ((page < (pages_per_blk * rknand->boot_blks)) &&
+	    nfc->selected_bank == 0 &&
+	    rknand->boot_ecc != ecc->strength) {
+		/*
+		 * There's currently no method to notify the MTD framework that
+		 * a different ECC strength is in use for the boot blocks.
+		 */
+		return -EIO;
+	}
+
+	nand_read_page_op(chip, page, 0, NULL, 0);
+	rk_nfc_read_buf(mtd, nfc->page_buf, mtd->writesize + mtd->oobsize);
+	for (i = 0; i < ecc->steps; i++) {
+		/*
+		 * The first four bytes of OOB are reserved for the
+		 * boot ROM. In some debugging cases, such as with a read,
+		 * erase and write back test, these 4 bytes also must be
+		 * saved somewhere, otherwise this information will be
+		 * lost during a write back.
+		 */
+		if (!i)
+			memcpy(rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1),
+			       rk_nfc_oob_ptr(chip, i),
+			       NFC_SYS_DATA_SIZE);
+		else
+			memcpy(rk_nfc_buf_to_oob_ptr(chip, i - 1),
+			       rk_nfc_oob_ptr(chip, i),
+			       NFC_SYS_DATA_SIZE);
+
+		/* Copy ECC data from the NFC buffer. */
+		memcpy(rk_nfc_buf_to_oob_ecc_ptr(chip, i),
+		       rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE,
+		       ecc->bytes);
+
+		/* Copy data from the NFC buffer. */
+		if (buf)
+			memcpy(rk_nfc_buf_to_data_ptr(chip, buf, i),
+			       rk_nfc_data_ptr(chip, i),
+			       ecc->size);
+	}
+
+	return 0;
+}
+
+static int rk_nfc_read_page_hwecc(struct mtd_info *mtd,
+				  struct nand_chip *chip,
+				  u8 *buf,
+				  int oob_required,
+				  int page)
+{
+	struct rk_nfc *nfc = nand_get_controller_data(chip);
+	struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+	int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP :
+			NFC_MIN_OOB_PER_STEP;
+	int pages_per_blk = mtd->erasesize / mtd->writesize;
+	dma_addr_t dma_data, dma_oob;
+	int ret = 0, i, cnt, boot_rom_mode = 0;
+	int max_bitflips = 0, bch_st, ecc_fail = 0;
+	u8 *oob;
+	u32 tmp;
+
+	nand_read_page_op(chip, page, 0, NULL, 0);
+
+	dma_data = dma_map_single(nfc->page_buf,
+				  mtd->writesize,
+				  DMA_FROM_DEVICE);
+	dma_oob = dma_map_single(nfc->oob_buf,
+				 ecc->steps * oob_step,
+				 DMA_FROM_DEVICE);
+
+	/*
+	 * The first blocks (4, 8 or 16 depending on the device)
+	 * are used by the boot ROM.
+	 * Configure the ECC algorithm supported by the boot ROM.
+	 */
+	if (page < (pages_per_blk * rknand->boot_blks) &&
+	    nfc->selected_bank == 0) {
+		boot_rom_mode = 1;
+		if (rknand->boot_ecc != ecc->strength)
+			rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc);
+	}
+
+	rk_nfc_xfer_start(nfc, NFC_READ, ecc->steps, dma_data,
+			  dma_oob);
+	ret = rk_nfc_wait_for_xfer_done(nfc);
+
+	dma_unmap_single(dma_data, mtd->writesize,
+			 DMA_FROM_DEVICE);
+	dma_unmap_single(dma_oob, ecc->steps * oob_step,
+			 DMA_FROM_DEVICE);
+
+	if (ret) {
+		ret = -ETIMEDOUT;
+		dev_err(nfc->dev, "read: wait transfer done timeout.\n");
+		goto timeout_err;
+	}
+
+	for (i = 1; i < ecc->steps; i++) {
+		oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
+		if (nfc->cfg->type == NFC_V9)
+			tmp = nfc->oob_buf[i];
+		else
+			tmp = nfc->oob_buf[i * (oob_step / 4)];
+		*oob++ = (u8)tmp;
+		*oob++ = (u8)(tmp >> 8);
+		*oob++ = (u8)(tmp >> 16);
+		*oob++ = (u8)(tmp >> 24);
+	}
+
+	for (i = 0; i < (ecc->steps / 2); i++) {
+		bch_st = readl_relaxed(nfc->regs +
+				       nfc->cfg->bch_st_off + i * 4);
+		if (bch_st & BIT(nfc->cfg->ecc0.err_flag_bit) ||
+		    bch_st & BIT(nfc->cfg->ecc1.err_flag_bit)) {
+			mtd->ecc_stats.failed++;
+			ecc_fail = 1;
+		} else {
+			cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc0);
+			mtd->ecc_stats.corrected += cnt;
+			max_bitflips = max_t(u32, max_bitflips, cnt);
+
+			cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc1);
+			mtd->ecc_stats.corrected += cnt;
+			max_bitflips = max_t(u32, max_bitflips, cnt);
+		}
+	}
+
+	if (buf)
+		memcpy(buf, nfc->page_buf, mtd->writesize);
+
+timeout_err:
+	if (boot_rom_mode && rknand->boot_ecc != ecc->strength)
+		rk_nfc_hw_ecc_setup(chip, ecc->strength);
+
+	if (ret)
+		return ret;
+
+	if (ecc_fail) {
+		dev_err(nfc->dev, "read page: %x ecc error!\n", page);
+		return 0;
+	}
+
+	return max_bitflips;
+}
+
+static int rk_nfc_read_oob(struct mtd_info *mtd,
+			   struct nand_chip *chip, int page)
+{
+	return rk_nfc_read_page_hwecc(mtd, chip, NULL, 1, page);
+}
+
+static inline void rk_nfc_hw_init(struct rk_nfc *nfc)
+{
+	/* Disable flash wp. */
+	writel(FMCTL_WP, nfc->regs + NFC_FMCTL);
+	/* Config default timing 40ns at 150 Mhz NFC clock. */
+	writel(0x1081, nfc->regs + NFC_FMWAIT);
+	nfc->cur_timing = 0x1081;
+	/* Disable randomizer and DMA. */
+	writel(0, nfc->regs + nfc->cfg->randmz_off);
+	writel(0, nfc->regs + nfc->cfg->dma_cfg_off);
+	writel(FLCTL_RST, nfc->regs + nfc->cfg->flctl_off);
+}
+
+static int rk_nfc_enable_clks(struct udevice *dev, struct rk_nfc *nfc)
+{
+	int ret;
+
+	if (!IS_ERR(nfc->nfc_clk)) {
+		ret = clk_prepare_enable(nfc->nfc_clk);
+		if (ret)
+			dev_err(dev, "failed to enable NFC clk\n");
+	}
+
+	ret = clk_prepare_enable(nfc->ahb_clk);
+	if (ret) {
+		dev_err(dev, "failed to enable ahb clk\n");
+		if (!IS_ERR(nfc->nfc_clk))
+			clk_disable_unprepare(nfc->nfc_clk);
+	}
+
+	return 0;
+}
+
+static void rk_nfc_disable_clks(struct rk_nfc *nfc)
+{
+	if (!IS_ERR(nfc->nfc_clk))
+		clk_disable_unprepare(nfc->nfc_clk);
+	clk_disable_unprepare(nfc->ahb_clk);
+}
+
+static int rk_nfc_ooblayout_free(struct mtd_info *mtd, int section,
+				 struct mtd_oob_region *oob_region)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
+
+	if (section)
+		return -ERANGE;
+
+	/*
+	 * The beginning of the OOB area stores the reserved data for the NFC,
+	 * the size of the reserved data is NFC_SYS_DATA_SIZE bytes.
+	 */
+	oob_region->length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2;
+	oob_region->offset = NFC_SYS_DATA_SIZE + 2;
+
+	return 0;
+}
+
+static int rk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
+				struct mtd_oob_region *oob_region)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
+
+	if (section)
+		return -ERANGE;
+
+	oob_region->length = mtd->oobsize - rknand->metadata_size;
+	oob_region->offset = rknand->metadata_size;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops rk_nfc_ooblayout_ops = {
+	.rfree = rk_nfc_ooblayout_free,
+	.ecc = rk_nfc_ooblayout_ecc,
+};
+
+static int rk_nfc_ecc_init(struct rk_nfc *nfc, struct nand_chip *chip)
+{
+	const u8 *strengths = nfc->cfg->ecc_strengths;
+	struct mtd_info *mtd = nand_to_mtd(chip);
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+	u8 max_strength, nfc_max_strength;
+	int i;
+
+	nfc_max_strength = nfc->cfg->ecc_strengths[0];
+	/* If optional dt settings not present. */
+	if (!ecc->size || !ecc->strength ||
+	    ecc->strength > nfc_max_strength) {
+		chip->ecc.size = 1024;
+		ecc->steps = mtd->writesize / ecc->size;
+
+		/*
+		 * HW ECC always requests the number of ECC bytes per 1024 byte
+		 * blocks. The first 4 OOB bytes are reserved for sys data.
+		 */
+		max_strength = ((mtd->oobsize / ecc->steps) - 4) * 8 /
+				 fls(8 * 1024);
+		if (max_strength > nfc_max_strength)
+			max_strength = nfc_max_strength;
+
+		for (i = 0; i < 4; i++) {
+			if (max_strength >= strengths[i])
+				break;
+		}
+
+		if (i >= 4) {
+			dev_err(nfc->dev, "unsupported ECC strength\n");
+			return -EOPNOTSUPP;
+		}
+
+		ecc->strength = strengths[i];
+	}
+	ecc->steps = mtd->writesize / ecc->size;
+	ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * chip->ecc.size), 8);
+
+	return 0;
+}
+
+static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc *nfc, int devnum)
+{
+	struct rk_nfc_nand_chip *rknand;
+	struct udevice *dev = nfc->dev;
+	struct nand_ecc_ctrl *ecc;
+	struct nand_chip *chip;
+	struct mtd_info *mtd;
+	u32 cs[NFC_MAX_NSELS];
+	int nsels, i, ret;
+	u32 tmp;
+
+	if (!ofnode_get_property(node, "reg", &nsels))
+		return -ENODEV;
+	nsels /= sizeof(u32);
+	if (!nsels || nsels > NFC_MAX_NSELS) {
+		dev_err(dev, "invalid reg property size %d\n", nsels);
+		return -EINVAL;
+	}
+
+	rknand = kzalloc(sizeof(*rknand) + nsels * sizeof(u8), GFP_KERNEL);
+	if (!rknand)
+		return -ENOMEM;
+
+	rknand->nsels = nsels;
+	rknand->timing = nfc->cur_timing;
+
+	ret = ofnode_read_u32_array(node, "reg", cs, nsels);
+	if (ret < 0) {
+		dev_err(dev, "Could not retrieve reg property\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < nsels; i++) {
+		if (cs[i] >= NFC_MAX_NSELS) {
+			dev_err(dev, "invalid CS: %u\n", cs[i]);
+			return -EINVAL;
+		}
+
+		if (test_and_set_bit(cs[i], &nfc->assigned_cs)) {
+			dev_err(dev, "CS %u already assigned\n", cs[i]);
+			return -EINVAL;
+		}
+
+		rknand->sels[i] = cs[i];
+	}
+
+	chip = &rknand->chip;
+	ecc = &chip->ecc;
+	ecc->mode = NAND_ECC_HW_SYNDROME;
+
+	ret = ofnode_read_u32(node, "nand-ecc-strength", &tmp);
+	ecc->strength = ret ? 0 : tmp;
+
+	ret = ofnode_read_u32(node, "nand-ecc-step-size", &tmp);
+	ecc->size = ret ? 0 : tmp;
+
+	mtd = nand_to_mtd(chip);
+	mtd->owner = THIS_MODULE;
+	mtd->dev->parent = dev;
+
+	nand_set_controller_data(chip, nfc);
+
+	chip->chip_delay = NFC_RB_DELAY_US;
+	chip->select_chip = rk_nfc_select_chip;
+	chip->cmd_ctrl = rk_nfc_cmd;
+	chip->read_buf = rk_nfc_read_buf;
+	chip->write_buf = rk_nfc_write_buf;
+	chip->read_byte = rockchip_nand_read_byte;
+	chip->dev_ready = rockchip_nand_dev_ready;
+	chip->controller = &nfc->controller;
+
+	chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
+	chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
+
+	mtd_set_ooblayout(mtd, &rk_nfc_ooblayout_ops);
+	rk_nfc_hw_init(nfc);
+	ret = nand_scan_ident(mtd, nsels, NULL);
+	if (ret)
+		return ret;
+
+	ret = rk_nfc_ecc_init(nfc, chip);
+	if (ret) {
+		dev_err(dev, "rk_nfc_ecc_init failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = ofnode_read_u32(node, "rockchip,boot-blks", &tmp);
+	rknand->boot_blks = ret ? 0 : tmp;
+
+	ret = ofnode_read_u32(node, "rockchip,boot-ecc-strength", &tmp);
+	rknand->boot_ecc = ret ? ecc->strength : tmp;
+
+	rknand->metadata_size = NFC_SYS_DATA_SIZE * ecc->steps;
+
+	if (rknand->metadata_size < NFC_SYS_DATA_SIZE + 2) {
+		dev_err(dev,
+			"driver needs at least %d bytes of meta data\n",
+			NFC_SYS_DATA_SIZE + 2);
+		return -EIO;
+	}
+
+	if (!nfc->page_buf) {
+		nfc->page_buf = kzalloc(NFC_MAX_PAGE_SIZE, GFP_KERNEL);
+		if (!nfc->page_buf)
+			return -ENOMEM;
+	}
+
+	if (!nfc->oob_buf) {
+		nfc->oob_buf = kzalloc(NFC_MAX_OOB_SIZE, GFP_KERNEL);
+		if (!nfc->oob_buf) {
+			kfree(nfc->page_buf);
+			nfc->page_buf = NULL;
+			return -ENOMEM;
+		}
+	}
+
+	ecc->read_page = rk_nfc_read_page_hwecc;
+	ecc->read_page_raw = rk_nfc_read_page_raw;
+	ecc->read_oob = rk_nfc_read_oob;
+	ecc->write_page = rk_nfc_write_page_hwecc;
+	ecc->write_page_raw = rk_nfc_write_page_raw;
+	ecc->write_oob = rk_nfc_write_oob;
+
+	ret = nand_scan_tail(mtd);
+	if (ret) {
+		dev_err(dev, "nand_scan_tail failed: %d\n", ret);
+		return ret;
+	}
+
+	return nand_register(devnum, mtd);
+}
+
+static int rk_nfc_nand_chips_init(struct udevice *dev, struct rk_nfc *nfc)
+{
+	int ret, i = 0;
+	ofnode child;
+
+	ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+		ret = rk_nfc_nand_chip_init(child, nfc, i++);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static struct nfc_cfg nfc_v6_cfg = {
+		.type			= NFC_V6,
+		.ecc_strengths		= {60, 40, 24, 16},
+		.ecc_cfgs		= {
+			0x00040011, 0x00040001, 0x00000011, 0x00000001,
+		},
+		.flctl_off		= 0x08,
+		.bchctl_off		= 0x0C,
+		.dma_cfg_off		= 0x10,
+		.dma_data_buf_off	= 0x14,
+		.dma_oob_buf_off	= 0x18,
+		.dma_st_off		= 0x1C,
+		.bch_st_off		= 0x20,
+		.randmz_off		= 0x150,
+		.int_en_off		= 0x16C,
+		.int_clr_off		= 0x170,
+		.int_st_off		= 0x174,
+		.oob0_off		= 0x200,
+		.oob1_off		= 0x230,
+		.ecc0			= {
+			.err_flag_bit	= 2,
+			.low		= 3,
+			.low_mask	= 0x1F,
+			.low_bn		= 5,
+			.high		= 27,
+			.high_mask	= 0x1,
+		},
+		.ecc1			= {
+			.err_flag_bit	= 15,
+			.low		= 16,
+			.low_mask	= 0x1F,
+			.low_bn		= 5,
+			.high		= 29,
+			.high_mask	= 0x1,
+		},
+};
+
+static struct nfc_cfg nfc_v8_cfg = {
+		.type			= NFC_V8,
+		.ecc_strengths		= {16, 16, 16, 16},
+		.ecc_cfgs		= {
+			0x00000001, 0x00000001, 0x00000001, 0x00000001,
+		},
+		.flctl_off		= 0x08,
+		.bchctl_off		= 0x0C,
+		.dma_cfg_off		= 0x10,
+		.dma_data_buf_off	= 0x14,
+		.dma_oob_buf_off	= 0x18,
+		.dma_st_off		= 0x1C,
+		.bch_st_off		= 0x20,
+		.randmz_off		= 0x150,
+		.int_en_off		= 0x16C,
+		.int_clr_off		= 0x170,
+		.int_st_off		= 0x174,
+		.oob0_off		= 0x200,
+		.oob1_off		= 0x230,
+		.ecc0			= {
+			.err_flag_bit	= 2,
+			.low		= 3,
+			.low_mask	= 0x1F,
+			.low_bn		= 5,
+			.high		= 27,
+			.high_mask	= 0x1,
+		},
+		.ecc1			= {
+			.err_flag_bit	= 15,
+			.low		= 16,
+			.low_mask	= 0x1F,
+			.low_bn		= 5,
+			.high		= 29,
+			.high_mask	= 0x1,
+		},
+};
+
+static struct nfc_cfg nfc_v9_cfg = {
+		.type			= NFC_V9,
+		.ecc_strengths		= {70, 60, 40, 16},
+		.ecc_cfgs		= {
+			0x00000001, 0x06000001, 0x04000001, 0x02000001,
+		},
+		.flctl_off		= 0x10,
+		.bchctl_off		= 0x20,
+		.dma_cfg_off		= 0x30,
+		.dma_data_buf_off	= 0x34,
+		.dma_oob_buf_off	= 0x38,
+		.dma_st_off		= 0x3C,
+		.bch_st_off		= 0x150,
+		.randmz_off		= 0x208,
+		.int_en_off		= 0x120,
+		.int_clr_off		= 0x124,
+		.int_st_off		= 0x128,
+		.oob0_off		= 0x200,
+		.oob1_off		= 0x204,
+		.ecc0			= {
+			.err_flag_bit	= 2,
+			.low		= 3,
+			.low_mask	= 0x7F,
+			.low_bn		= 7,
+			.high		= 0,
+			.high_mask	= 0x0,
+		},
+		.ecc1			= {
+			.err_flag_bit	= 18,
+			.low		= 19,
+			.low_mask	= 0x7F,
+			.low_bn		= 7,
+			.high		= 0,
+			.high_mask	= 0x0,
+		},
+};
+
+static const struct udevice_id rk_nfc_id_table[] = {
+	{
+		.compatible = "rockchip,px30-nfc",
+		.data = (unsigned long)&nfc_v9_cfg
+	},
+	{
+		.compatible = "rockchip,rk2928-nfc",
+		.data = (unsigned long)&nfc_v6_cfg
+	},
+	{
+		.compatible = "rockchip,rv1108-nfc",
+		.data = (unsigned long)&nfc_v8_cfg
+	},
+	{
+		.compatible = "rockchip,rk3308-nfc",
+		.data = (unsigned long)&nfc_v8_cfg
+	},
+	{ /* sentinel */ }
+};
+
+static int rk_nfc_probe(struct udevice *dev)
+{
+	struct rk_nfc *nfc = dev_get_priv(dev);
+	int ret = 0;
+
+	nfc->cfg = (void *)dev_get_driver_data(dev);
+	nfc->dev = dev;
+
+	nfc->regs = (void *)dev_read_addr(dev);
+	if (IS_ERR(nfc->regs)) {
+		ret = PTR_ERR(nfc->regs);
+		goto release_nfc;
+	}
+
+	nfc->nfc_clk = devm_clk_get(dev, "nfc");
+	if (IS_ERR(nfc->nfc_clk)) {
+		dev_dbg(dev, "no NFC clk\n");
+		/* Some earlier models, such as rk3066, have no NFC clk. */
+	}
+
+	nfc->ahb_clk = devm_clk_get(dev, "ahb");
+	if (IS_ERR(nfc->ahb_clk)) {
+		dev_err(dev, "no ahb clk\n");
+		ret = PTR_ERR(nfc->ahb_clk);
+		goto release_nfc;
+	}
+
+	ret = rk_nfc_enable_clks(dev, nfc);
+	if (ret)
+		goto release_nfc;
+
+	spin_lock_init(&nfc->controller.lock);
+	init_waitqueue_head(&nfc->controller.wq);
+
+	rk_nfc_hw_init(nfc);
+
+	ret = rk_nfc_nand_chips_init(dev, nfc);
+	if (ret) {
+		dev_err(dev, "failed to init NAND chips\n");
+		goto clk_disable;
+	}
+	return 0;
+
+clk_disable:
+	rk_nfc_disable_clks(nfc);
+release_nfc:
+	return ret;
+}
+
+U_BOOT_DRIVER(rockchip_nfc) = {
+	.name = "rockchip_nfc",
+	.id = UCLASS_MTD,
+	.of_match = rk_nfc_id_table,
+	.probe = rk_nfc_probe,
+	.priv_auto = sizeof(struct rk_nfc),
+};
+
+void board_nand_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_MTD,
+					  DM_DRIVER_GET(rockchip_nfc),
+					  &dev);
+	if (ret && ret != -ENODEV)
+		log_err("Failed to initialize ROCKCHIP NAND controller. (error %d)\n",
+			ret);
+}
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+	struct mtd_info *mtd;
+	size_t length = size;
+
+	mtd = get_nand_dev_by_index(0);
+	return nand_read_skip_bad(mtd, offs, &length, NULL, size, (u_char *)dst);
+}
+
+void nand_deselect(void) {}
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index bc22af4..9322e73 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -61,13 +61,13 @@ struct rk_pcie {
 #define PCIE_CLIENT_DBF_EN		0xffff0003
 
 /* Parameters for the waiting for #perst signal */
-#define PERST_WAIT_MS			1000
+#define MACRO_US			1000
 
 static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
 {
 	if ((uintptr_t)addr & (size - 1)) {
 		*val = 0;
-		return PCIBIOS_UNSUPPORTED;
+		return -EOPNOTSUPP;
 	}
 
 	if (size == 4) {
@@ -87,7 +87,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
 static int rk_pcie_write(void __iomem *addr, int size, u32 val)
 {
 	if ((uintptr_t)addr & (size - 1))
-		return PCIBIOS_UNSUPPORTED;
+		return -EOPNOTSUPP;
 
 	if (size == 4)
 		writel(val, addr);
@@ -158,8 +158,6 @@ static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg,
  */
 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
 {
-	u32 val;
-
 	dw_pcie_dbi_write_enable(&pci->dw, true);
 
 	clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
@@ -251,7 +249,7 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
 		 * some wired devices need much more, such as 600ms.
 		 * Add a enough delay to cover all cases.
 		 */
-		msleep(PERST_WAIT_MS);
+		udelay(MACRO_US * 1000);
 		dm_gpio_set_value(&priv->rst_gpio, 1);
 	}
 
@@ -273,12 +271,12 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
 		dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
 			 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
 		rk_pcie_debug_dump(priv);
-		msleep(1000);
+		udelay(MACRO_US * 1000);
 	}
 
 	dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));
 	/* Link maybe in Gen switch recovery but we need to wait more 1s */
-	msleep(1000);
+	udelay(MACRO_US * 1000);
 	return -EIO;
 }
 
@@ -298,7 +296,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
 		}
 	}
 
-	msleep(1000);
+	udelay(MACRO_US * 1000);
 
 	ret = generic_phy_init(&priv->phy);
 	if (ret) {
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index c3ec89a..ca1c289 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -12,4 +12,5 @@ obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
 obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
 obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o
diff --git a/drivers/ram/rockchip/sdram_rk3568.c b/drivers/ram/rockchip/sdram_rk3568.c
new file mode 100644
index 0000000..0ac4b54
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3568.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3568.h>
+#include <asm/arch-rockchip/sdram.h>
+
+struct dram_info {
+	struct ram_info info;
+	struct rk3568_pmugrf *pmugrf;
+};
+
+static int rk3568_dmc_probe(struct udevice *dev)
+{
+	struct dram_info *priv = dev_get_priv(dev);
+
+	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+	priv->info.base = CONFIG_SYS_SDRAM_BASE;
+	priv->info.size =
+		rockchip_sdram_size((phys_addr_t)&priv->pmugrf->pmu_os_reg2);
+
+	return 0;
+}
+
+static int rk3568_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+	struct dram_info *priv = dev_get_priv(dev);
+
+	*info = priv->info;
+
+	return 0;
+}
+
+static struct ram_ops rk3568_dmc_ops = {
+	.get_info = rk3568_dmc_get_info,
+};
+
+static const struct udevice_id rk3568_dmc_ids[] = {
+	{ .compatible = "rockchip,rk3568-dmc" },
+	{ }
+};
+
+U_BOOT_DRIVER(dmc_rk3568) = {
+	.name = "rockchip_rk3568_dmc",
+	.id = UCLASS_RAM,
+	.of_match = rk3568_dmc_ids,
+	.ops = &rk3568_dmc_ops,
+	.probe = rk3568_dmc_probe,
+	.priv_auto = sizeof(struct dram_info),
+};
diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h
index b7e8503..492b7b4 100644
--- a/include/configs/evb_rk3399.h
+++ b/include/configs/evb_rk3399.h
@@ -15,4 +15,7 @@
 
 #define SDRAM_BANK_SIZE			(2UL << 30)
 
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2
+
 #endif
diff --git a/include/configs/evb_rk3568.h b/include/configs/evb_rk3568.h
new file mode 100644
index 0000000..2b255a1
--- /dev/null
+++ b/include/configs/evb_rk3568.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __EVB_RK3568_H
+#define __EVB_RK3568_H
+
+#include <configs/rk3568_common.h>
+
+#define CONFIG_SUPPORT_EMMC_RPMB
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+			"stdout=serial,vidconsole\0" \
+			"stderr=serial,vidconsole\0"
+
+#endif
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index b37ed5c..6d710da 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -51,6 +51,7 @@
 	"script_size_f=0x2000\0" \
 	"pxefile_addr_r=0x00600000\0" \
 	"fdt_addr_r=0x01f00000\0" \
+	"fdtoverlay_addr_r=0x02000000\0" \
 	"kernel_addr_r=0x02080000\0" \
 	"ramdisk_addr_r=0x06000000\0" \
 	"kernel_comp_addr_r=0x08000000\0" \
diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h
new file mode 100644
index 0000000..b656891
--- /dev/null
+++ b/include/configs/rk3568_common.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_RK3568_COMMON_H
+#define __CONFIG_RK3568_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define COUNTER_FREQUENCY               24000000
+#define CONFIG_ROCKCHIP_STIMER_BASE	0xfdd1c020
+
+#define CONFIG_IRAM_BASE		0xfdcc0000
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x00c00000
+#define CONFIG_SYS_LOAD_ADDR		0x00c00800
+#define CONFIG_SYS_BOOTM_LEN		(64 << 20)	/* 64M */
+
+#define CONFIG_SYS_SDRAM_BASE		0
+#define SDRAM_MAX_SIZE			0xf0000000
+
+#ifndef CONFIG_SPL_BUILD
+#define ENV_MEM_LAYOUT_SETTINGS		\
+	"scriptaddr=0x00c00000\0"	\
+	"pxefile_addr_r=0x00e00000\0"	\
+	"fdt_addr_r=0x0a100000\0"	\
+	"kernel_addr_r=0x02080000\0"	\
+	"ramdisk_addr_r=0x0a200000\0"
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	ENV_MEM_LAYOUT_SETTINGS			\
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"partitions=" PARTS_DEFAULT		\
+	ROCKCHIP_DEVICE_SETTINGS		\
+	BOOTENV
+#endif
+
+#endif
diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h
new file mode 100644
index 0000000..c194242
--- /dev/null
+++ b/include/dt-bindings/clock/rk3568-cru.h
@@ -0,0 +1,925 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
+
+/* pmucru-clocks indices */
+
+/* pmucru plls */
+#define PLL_PPLL		1
+#define PLL_HPLL		2
+
+/* pmucru clocks */
+#define XIN_OSC0_DIV		4
+#define CLK_RTC_32K		5
+#define CLK_PMU			6
+#define CLK_I2C0		7
+#define CLK_RTC32K_FRAC		8
+#define CLK_UART0_DIV		9
+#define CLK_UART0_FRAC		10
+#define SCLK_UART0		11
+#define DBCLK_GPIO0		12
+#define CLK_PWM0		13
+#define CLK_CAPTURE_PWM0_NDFT	14
+#define CLK_PMUPVTM		15
+#define CLK_CORE_PMUPVTM	16
+#define CLK_REF24M		17
+#define XIN_OSC0_USBPHY0_G	18
+#define CLK_USBPHY0_REF		19
+#define XIN_OSC0_USBPHY1_G	20
+#define CLK_USBPHY1_REF		21
+#define XIN_OSC0_MIPIDSIPHY0_G	22
+#define CLK_MIPIDSIPHY0_REF	23
+#define XIN_OSC0_MIPIDSIPHY1_G	24
+#define CLK_MIPIDSIPHY1_REF	25
+#define CLK_WIFI_DIV		26
+#define CLK_WIFI_OSC0		27
+#define CLK_WIFI		28
+#define CLK_PCIEPHY0_DIV	29
+#define CLK_PCIEPHY0_OSC0	30
+#define CLK_PCIEPHY0_REF	31
+#define CLK_PCIEPHY1_DIV	32
+#define CLK_PCIEPHY1_OSC0	33
+#define CLK_PCIEPHY1_REF	34
+#define CLK_PCIEPHY2_DIV	35
+#define CLK_PCIEPHY2_OSC0	36
+#define CLK_PCIEPHY2_REF	37
+#define CLK_PCIE30PHY_REF_M	38
+#define CLK_PCIE30PHY_REF_N	39
+#define CLK_HDMI_REF		40
+#define XIN_OSC0_EDPPHY_G	41
+#define PCLK_PDPMU		42
+#define PCLK_PMU		43
+#define PCLK_UART0		44
+#define PCLK_I2C0		45
+#define PCLK_GPIO0		46
+#define PCLK_PMUPVTM		47
+#define PCLK_PWM0		48
+#define CLK_PDPMU		49
+#define SCLK_32K_IOE		50
+
+#define CLKPMU_NR_CLKS		(SCLK_32K_IOE + 1)
+
+/* cru-clocks indices */
+
+/* cru plls */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_CPLL		3
+#define PLL_GPLL		4
+#define PLL_VPLL		5
+#define PLL_NPLL		6
+
+/* cru clocks */
+#define CPLL_333M		9
+#define ARMCLK			10
+#define USB480M			11
+#define ACLK_CORE_NIU2BUS	18
+#define CLK_CORE_PVTM		19
+#define CLK_CORE_PVTM_CORE	20
+#define CLK_CORE_PVTPLL		21
+#define CLK_GPU_SRC		22
+#define CLK_GPU_PRE_NDFT	23
+#define CLK_GPU_PRE_MUX		24
+#define ACLK_GPU_PRE		25
+#define PCLK_GPU_PRE		26
+#define CLK_GPU			27
+#define CLK_GPU_NP5		28
+#define PCLK_GPU_PVTM		29
+#define CLK_GPU_PVTM		30
+#define CLK_GPU_PVTM_CORE	31
+#define CLK_GPU_PVTPLL		32
+#define CLK_NPU_SRC		33
+#define CLK_NPU_PRE_NDFT	34
+#define CLK_NPU			35
+#define CLK_NPU_NP5		36
+#define HCLK_NPU_PRE		37
+#define PCLK_NPU_PRE		38
+#define ACLK_NPU_PRE		39
+#define ACLK_NPU		40
+#define HCLK_NPU		41
+#define PCLK_NPU_PVTM		42
+#define CLK_NPU_PVTM		43
+#define CLK_NPU_PVTM_CORE	44
+#define CLK_NPU_PVTPLL		45
+#define CLK_DDRPHY1X_SRC	46
+#define CLK_DDRPHY1X_HWFFC_SRC	47
+#define CLK_DDR1X		48
+#define CLK_MSCH		49
+#define CLK24_DDRMON		50
+#define ACLK_GIC_AUDIO		51
+#define HCLK_GIC_AUDIO		52
+#define HCLK_SDMMC_BUFFER	53
+#define DCLK_SDMMC_BUFFER	54
+#define ACLK_GIC600		55
+#define ACLK_SPINLOCK		56
+#define HCLK_I2S0_8CH		57
+#define HCLK_I2S1_8CH		58
+#define HCLK_I2S2_2CH		59
+#define HCLK_I2S3_2CH		60
+#define CLK_I2S0_8CH_TX_SRC	61
+#define CLK_I2S0_8CH_TX_FRAC	62
+#define MCLK_I2S0_8CH_TX	63
+#define I2S0_MCLKOUT_TX		64
+#define CLK_I2S0_8CH_RX_SRC	65
+#define CLK_I2S0_8CH_RX_FRAC	66
+#define MCLK_I2S0_8CH_RX	67
+#define I2S0_MCLKOUT_RX		68
+#define CLK_I2S1_8CH_TX_SRC	69
+#define CLK_I2S1_8CH_TX_FRAC	70
+#define MCLK_I2S1_8CH_TX	71
+#define I2S1_MCLKOUT_TX		72
+#define CLK_I2S1_8CH_RX_SRC	73
+#define CLK_I2S1_8CH_RX_FRAC	74
+#define MCLK_I2S1_8CH_RX	75
+#define I2S1_MCLKOUT_RX		76
+#define CLK_I2S2_2CH_SRC	77
+#define CLK_I2S2_2CH_FRAC	78
+#define MCLK_I2S2_2CH		79
+#define I2S2_MCLKOUT		80
+#define CLK_I2S3_2CH_TX_SRC	81
+#define CLK_I2S3_2CH_TX_FRAC	82
+#define MCLK_I2S3_2CH_TX	83
+#define I2S3_MCLKOUT_TX		84
+#define CLK_I2S3_2CH_RX_SRC	85
+#define CLK_I2S3_2CH_RX_FRAC	86
+#define MCLK_I2S3_2CH_RX	87
+#define I2S3_MCLKOUT_RX		88
+#define HCLK_PDM		89
+#define MCLK_PDM		90
+#define HCLK_VAD		91
+#define HCLK_SPDIF_8CH		92
+#define MCLK_SPDIF_8CH_SRC	93
+#define MCLK_SPDIF_8CH_FRAC	94
+#define MCLK_SPDIF_8CH		95
+#define HCLK_AUDPWM		96
+#define SCLK_AUDPWM_SRC		97
+#define SCLK_AUDPWM_FRAC	98
+#define SCLK_AUDPWM		99
+#define HCLK_ACDCDIG		100
+#define CLK_ACDCDIG_I2C		101
+#define CLK_ACDCDIG_DAC		102
+#define CLK_ACDCDIG_ADC		103
+#define ACLK_SECURE_FLASH	104
+#define HCLK_SECURE_FLASH	105
+#define ACLK_CRYPTO_NS		106
+#define HCLK_CRYPTO_NS		107
+#define CLK_CRYPTO_NS_CORE	108
+#define CLK_CRYPTO_NS_PKA	109
+#define CLK_CRYPTO_NS_RNG	110
+#define HCLK_TRNG_NS		111
+#define CLK_TRNG_NS		112
+#define PCLK_OTPC_NS		113
+#define CLK_OTPC_NS_SBPI	114
+#define CLK_OTPC_NS_USR		115
+#define HCLK_NANDC		116
+#define NCLK_NANDC		117
+#define HCLK_SFC		118
+#define HCLK_SFC_XIP		119
+#define SCLK_SFC		120
+#define ACLK_EMMC		121
+#define HCLK_EMMC		122
+#define BCLK_EMMC		123
+#define CCLK_EMMC		124
+#define TCLK_EMMC		125
+#define ACLK_PIPE		126
+#define PCLK_PIPE		127
+#define PCLK_PIPE_GRF		128
+#define ACLK_PCIE20_MST		129
+#define ACLK_PCIE20_SLV		130
+#define ACLK_PCIE20_DBI		131
+#define PCLK_PCIE20		132
+#define CLK_PCIE20_AUX_NDFT	133
+#define CLK_PCIE20_AUX_DFT	134
+#define CLK_PCIE20_PIPE_DFT	135
+#define ACLK_PCIE30X1_MST	136
+#define ACLK_PCIE30X1_SLV	137
+#define ACLK_PCIE30X1_DBI	138
+#define PCLK_PCIE30X1		139
+#define CLK_PCIE30X1_AUX_NDFT	140
+#define CLK_PCIE30X1_AUX_DFT	141
+#define CLK_PCIE30X1_PIPE_DFT	142
+#define ACLK_PCIE30X2_MST	143
+#define ACLK_PCIE30X2_SLV	144
+#define ACLK_PCIE30X2_DBI	145
+#define PCLK_PCIE30X2		146
+#define CLK_PCIE30X2_AUX_NDFT	147
+#define CLK_PCIE30X2_AUX_DFT	148
+#define CLK_PCIE30X2_PIPE_DFT	149
+#define ACLK_SATA0		150
+#define CLK_SATA0_PMALIVE	151
+#define CLK_SATA0_RXOOB		152
+#define CLK_SATA0_PIPE_NDFT	153
+#define CLK_SATA0_PIPE_DFT	154
+#define ACLK_SATA1		155
+#define CLK_SATA1_PMALIVE	156
+#define CLK_SATA1_RXOOB		157
+#define CLK_SATA1_PIPE_NDFT	158
+#define CLK_SATA1_PIPE_DFT	159
+#define ACLK_SATA2		160
+#define CLK_SATA2_PMALIVE	161
+#define CLK_SATA2_RXOOB		162
+#define CLK_SATA2_PIPE_NDFT	163
+#define CLK_SATA2_PIPE_DFT	164
+#define ACLK_USB3OTG0		165
+#define CLK_USB3OTG0_REF	166
+#define CLK_USB3OTG0_SUSPEND	167
+#define ACLK_USB3OTG1		168
+#define CLK_USB3OTG1_REF	169
+#define CLK_USB3OTG1_SUSPEND	170
+#define CLK_XPCS_EEE		171
+#define PCLK_XPCS		172
+#define ACLK_PHP		173
+#define HCLK_PHP		174
+#define PCLK_PHP		175
+#define HCLK_SDMMC0		176
+#define CLK_SDMMC0		177
+#define HCLK_SDMMC1		178
+#define CLK_SDMMC1		179
+#define ACLK_GMAC0		180
+#define PCLK_GMAC0		181
+#define CLK_MAC0_2TOP		182
+#define CLK_MAC0_OUT		183
+#define CLK_MAC0_REFOUT		184
+#define CLK_GMAC0_PTP_REF	185
+#define ACLK_USB		186
+#define HCLK_USB		187
+#define PCLK_USB		188
+#define HCLK_USB2HOST0		189
+#define HCLK_USB2HOST0_ARB	190
+#define HCLK_USB2HOST1		191
+#define HCLK_USB2HOST1_ARB	192
+#define HCLK_SDMMC2		193
+#define CLK_SDMMC2		194
+#define ACLK_GMAC1		195
+#define PCLK_GMAC1		196
+#define CLK_MAC1_2TOP		197
+#define CLK_MAC1_OUT		198
+#define CLK_MAC1_REFOUT		199
+#define CLK_GMAC1_PTP_REF	200
+#define ACLK_PERIMID		201
+#define HCLK_PERIMID		202
+#define ACLK_VI			203
+#define HCLK_VI			204
+#define PCLK_VI			205
+#define ACLK_VICAP		206
+#define HCLK_VICAP		207
+#define DCLK_VICAP		208
+#define ICLK_VICAP_G		209
+#define ACLK_ISP		210
+#define HCLK_ISP		211
+#define CLK_ISP			212
+#define PCLK_CSI2HOST1		213
+#define CLK_CIF_OUT		214
+#define CLK_CAM0_OUT		215
+#define CLK_CAM1_OUT		216
+#define ACLK_VO			217
+#define HCLK_VO			218
+#define PCLK_VO			219
+#define ACLK_VOP_PRE		220
+#define ACLK_VOP		221
+#define HCLK_VOP		222
+#define DCLK_VOP0		223
+#define DCLK_VOP1		224
+#define DCLK_VOP2		225
+#define CLK_VOP_PWM		226
+#define ACLK_HDCP		227
+#define HCLK_HDCP		228
+#define PCLK_HDCP		229
+#define PCLK_HDMI_HOST		230
+#define CLK_HDMI_SFR		231
+#define PCLK_DSITX_0		232
+#define PCLK_DSITX_1		233
+#define PCLK_EDP_CTRL		234
+#define CLK_EDP_200M		235
+#define ACLK_VPU_PRE		236
+#define HCLK_VPU_PRE		237
+#define ACLK_VPU		238
+#define HCLK_VPU		239
+#define ACLK_RGA_PRE		240
+#define HCLK_RGA_PRE		241
+#define PCLK_RGA_PRE		242
+#define ACLK_RGA		243
+#define HCLK_RGA		244
+#define CLK_RGA_CORE		245
+#define ACLK_IEP		246
+#define HCLK_IEP		247
+#define CLK_IEP_CORE		248
+#define HCLK_EBC		249
+#define DCLK_EBC		250
+#define ACLK_JDEC		251
+#define HCLK_JDEC		252
+#define ACLK_JENC		253
+#define HCLK_JENC		254
+#define PCLK_EINK		255
+#define HCLK_EINK		256
+#define ACLK_RKVENC_PRE		257
+#define HCLK_RKVENC_PRE		258
+#define ACLK_RKVENC		259
+#define HCLK_RKVENC		260
+#define CLK_RKVENC_CORE		261
+#define ACLK_RKVDEC_PRE		262
+#define HCLK_RKVDEC_PRE		263
+#define ACLK_RKVDEC		264
+#define HCLK_RKVDEC		265
+#define CLK_RKVDEC_CA		266
+#define CLK_RKVDEC_CORE		267
+#define CLK_RKVDEC_HEVC_CA	268
+#define ACLK_BUS		269
+#define PCLK_BUS		270
+#define PCLK_TSADC		271
+#define CLK_TSADC_TSEN		272
+#define CLK_TSADC		273
+#define PCLK_SARADC		274
+#define CLK_SARADC		275
+#define PCLK_SCR		276
+#define PCLK_WDT_NS		277
+#define TCLK_WDT_NS		278
+#define ACLK_DMAC0		279
+#define ACLK_DMAC1		280
+#define ACLK_MCU		281
+#define PCLK_INTMUX		282
+#define PCLK_MAILBOX		283
+#define PCLK_UART1		284
+#define CLK_UART1_SRC		285
+#define CLK_UART1_FRAC		286
+#define SCLK_UART1		287
+#define PCLK_UART2		288
+#define CLK_UART2_SRC		289
+#define CLK_UART2_FRAC		290
+#define SCLK_UART2		291
+#define PCLK_UART3		292
+#define CLK_UART3_SRC		293
+#define CLK_UART3_FRAC		294
+#define SCLK_UART3		295
+#define PCLK_UART4		296
+#define CLK_UART4_SRC		297
+#define CLK_UART4_FRAC		298
+#define SCLK_UART4		299
+#define PCLK_UART5		300
+#define CLK_UART5_SRC		301
+#define CLK_UART5_FRAC		302
+#define SCLK_UART5		303
+#define PCLK_UART6		304
+#define CLK_UART6_SRC		305
+#define CLK_UART6_FRAC		306
+#define SCLK_UART6		307
+#define PCLK_UART7		308
+#define CLK_UART7_SRC		309
+#define CLK_UART7_FRAC		310
+#define SCLK_UART7		311
+#define PCLK_UART8		312
+#define CLK_UART8_SRC		313
+#define CLK_UART8_FRAC		314
+#define SCLK_UART8		315
+#define PCLK_UART9		316
+#define CLK_UART9_SRC		317
+#define CLK_UART9_FRAC		318
+#define SCLK_UART9		319
+#define PCLK_CAN0		320
+#define CLK_CAN0		321
+#define PCLK_CAN1		322
+#define CLK_CAN1		323
+#define PCLK_CAN2		324
+#define CLK_CAN2		325
+#define CLK_I2C			326
+#define PCLK_I2C1		327
+#define CLK_I2C1		328
+#define PCLK_I2C2		329
+#define CLK_I2C2		330
+#define PCLK_I2C3		331
+#define CLK_I2C3		332
+#define PCLK_I2C4		333
+#define CLK_I2C4		334
+#define PCLK_I2C5		335
+#define CLK_I2C5		336
+#define PCLK_SPI0		337
+#define CLK_SPI0		338
+#define PCLK_SPI1		339
+#define CLK_SPI1		340
+#define PCLK_SPI2		341
+#define CLK_SPI2		342
+#define PCLK_SPI3		343
+#define CLK_SPI3		344
+#define PCLK_PWM1		345
+#define CLK_PWM1		346
+#define CLK_PWM1_CAPTURE	347
+#define PCLK_PWM2		348
+#define CLK_PWM2		349
+#define CLK_PWM2_CAPTURE	350
+#define PCLK_PWM3		351
+#define CLK_PWM3		352
+#define CLK_PWM3_CAPTURE	353
+#define DBCLK_GPIO		354
+#define PCLK_GPIO1		355
+#define DBCLK_GPIO1		356
+#define PCLK_GPIO2		357
+#define DBCLK_GPIO2		358
+#define PCLK_GPIO3		359
+#define DBCLK_GPIO3		360
+#define PCLK_GPIO4		361
+#define DBCLK_GPIO4		362
+#define OCC_SCAN_CLK_GPIO	363
+#define PCLK_TIMER		364
+#define CLK_TIMER0		365
+#define CLK_TIMER1		366
+#define CLK_TIMER2		367
+#define CLK_TIMER3		368
+#define CLK_TIMER4		369
+#define CLK_TIMER5		370
+#define ACLK_TOP_HIGH		371
+#define ACLK_TOP_LOW		372
+#define HCLK_TOP		373
+#define PCLK_TOP		374
+#define PCLK_PCIE30PHY		375
+#define CLK_OPTC_ARB		376
+#define PCLK_MIPICSIPHY		377
+#define PCLK_MIPIDSIPHY0	378
+#define PCLK_MIPIDSIPHY1	379
+#define PCLK_PIPEPHY0		380
+#define PCLK_PIPEPHY1		381
+#define PCLK_PIPEPHY2		382
+#define PCLK_CPU_BOOST		383
+#define CLK_CPU_BOOST		384
+#define PCLK_OTPPHY		385
+#define SCLK_GMAC0		386
+#define SCLK_GMAC0_RGMII_SPEED	387
+#define SCLK_GMAC0_RMII_SPEED	388
+#define SCLK_GMAC0_RX_TX	389
+#define SCLK_GMAC1		390
+#define SCLK_GMAC1_RGMII_SPEED	391
+#define SCLK_GMAC1_RMII_SPEED	392
+#define SCLK_GMAC1_RX_TX	393
+#define SCLK_SDMMC0_DRV		394
+#define SCLK_SDMMC0_SAMPLE	395
+#define SCLK_SDMMC1_DRV		396
+#define SCLK_SDMMC1_SAMPLE	397
+#define SCLK_SDMMC2_DRV		398
+#define SCLK_SDMMC2_SAMPLE	399
+#define SCLK_EMMC_DRV		400
+#define SCLK_EMMC_SAMPLE	401
+#define PCLK_EDPPHY_GRF		402
+#define CLK_HDMI_CEC            403
+#define CLK_I2S0_8CH_TX		404
+#define CLK_I2S0_8CH_RX		405
+#define CLK_I2S1_8CH_TX		406
+#define CLK_I2S1_8CH_RX		407
+#define CLK_I2S2_2CH		408
+#define CLK_I2S3_2CH_TX		409
+#define CLK_I2S3_2CH_RX		410
+#define CPLL_500M		411
+#define CPLL_250M		412
+#define CPLL_125M		413
+#define CPLL_62P5M		414
+#define CPLL_50M		415
+#define CPLL_25M		416
+#define CPLL_100M		417
+
+#define PCLK_CORE_PVTM		450
+
+#define CLK_NR_CLKS		(PCLK_CORE_PVTM + 1)
+
+/* pmu soft-reset indices */
+/* pmucru_softrst_con0 */
+#define SRST_P_PDPMU_NIU	0
+#define SRST_P_PMUCRU		1
+#define SRST_P_PMUGRF		2
+#define SRST_P_I2C0		3
+#define SRST_I2C0		4
+#define SRST_P_UART0		5
+#define SRST_S_UART0		6
+#define SRST_P_PWM0		7
+#define SRST_PWM0		8
+#define SRST_P_GPIO0		9
+#define SRST_GPIO0		10
+#define SRST_P_PMUPVTM		11
+#define SRST_PMUPVTM		12
+
+/* soft-reset indices */
+
+/* cru_softrst_con0 */
+#define SRST_NCORERESET0	0
+#define SRST_NCORERESET1	1
+#define SRST_NCORERESET2	2
+#define SRST_NCORERESET3	3
+#define SRST_NCPUPORESET0	4
+#define SRST_NCPUPORESET1	5
+#define SRST_NCPUPORESET2	6
+#define SRST_NCPUPORESET3	7
+#define SRST_NSRESET		8
+#define SRST_NSPORESET		9
+#define SRST_NATRESET		10
+#define SRST_NGICRESET		11
+#define SRST_NPRESET		12
+#define SRST_NPERIPHRESET	13
+
+/* cru_softrst_con1 */
+#define SRST_A_CORE_NIU2DDR	16
+#define SRST_A_CORE_NIU2BUS	17
+#define SRST_P_DBG_NIU		18
+#define SRST_P_DBG		19
+#define SRST_P_DBG_DAPLITE	20
+#define SRST_DAP		21
+#define SRST_A_ADB400_CORE2GIC	22
+#define SRST_A_ADB400_GIC2CORE	23
+#define SRST_P_CORE_GRF		24
+#define SRST_P_CORE_PVTM	25
+#define SRST_CORE_PVTM		26
+#define SRST_CORE_PVTPLL	27
+
+/* cru_softrst_con2 */
+#define SRST_GPU		32
+#define SRST_A_GPU_NIU		33
+#define SRST_P_GPU_NIU		34
+#define SRST_P_GPU_PVTM		35
+#define SRST_GPU_PVTM		36
+#define SRST_GPU_PVTPLL		37
+#define SRST_A_NPU_NIU		40
+#define SRST_H_NPU_NIU		41
+#define SRST_P_NPU_NIU		42
+#define SRST_A_NPU		43
+#define SRST_H_NPU		44
+#define SRST_P_NPU_PVTM		45
+#define SRST_NPU_PVTM		46
+#define SRST_NPU_PVTPLL		47
+
+/* cru_softrst_con3 */
+#define SRST_A_MSCH		51
+#define SRST_HWFFC_CTRL		52
+#define SRST_DDR_ALWAYSON	53
+#define SRST_A_DDRSPLIT		54
+#define SRST_DDRDFI_CTL		55
+#define SRST_A_DMA2DDR		57
+
+/* cru_softrst_con4 */
+#define SRST_A_PERIMID_NIU	64
+#define SRST_H_PERIMID_NIU	65
+#define SRST_A_GIC_AUDIO_NIU	66
+#define SRST_H_GIC_AUDIO_NIU	67
+#define SRST_A_GIC600		68
+#define SRST_A_GIC600_DEBUG	69
+#define SRST_A_GICADB_CORE2GIC	70
+#define SRST_A_GICADB_GIC2CORE	71
+#define SRST_A_SPINLOCK		72
+#define SRST_H_SDMMC_BUFFER	73
+#define SRST_D_SDMMC_BUFFER	74
+#define SRST_H_I2S0_8CH		75
+#define SRST_H_I2S1_8CH		76
+#define SRST_H_I2S2_2CH		77
+#define SRST_H_I2S3_2CH		78
+
+/* cru_softrst_con5 */
+#define SRST_M_I2S0_8CH_TX	80
+#define SRST_M_I2S0_8CH_RX	81
+#define SRST_M_I2S1_8CH_TX	82
+#define SRST_M_I2S1_8CH_RX	83
+#define SRST_M_I2S2_2CH		84
+#define SRST_M_I2S3_2CH_TX	85
+#define SRST_M_I2S3_2CH_RX	86
+#define SRST_H_PDM		87
+#define SRST_M_PDM		88
+#define SRST_H_VAD		89
+#define SRST_H_SPDIF_8CH	90
+#define SRST_M_SPDIF_8CH	91
+#define SRST_H_AUDPWM		92
+#define SRST_S_AUDPWM		93
+#define SRST_H_ACDCDIG		94
+#define SRST_ACDCDIG		95
+
+/* cru_softrst_con6 */
+#define SRST_A_SECURE_FLASH_NIU	96
+#define SRST_H_SECURE_FLASH_NIU	97
+#define SRST_A_CRYPTO_NS	103
+#define SRST_H_CRYPTO_NS	104
+#define SRST_CRYPTO_NS_CORE	105
+#define SRST_CRYPTO_NS_PKA	106
+#define SRST_CRYPTO_NS_RNG	107
+#define SRST_H_TRNG_NS		108
+#define SRST_TRNG_NS		109
+
+/* cru_softrst_con7 */
+#define SRST_H_NANDC		112
+#define SRST_N_NANDC		113
+#define SRST_H_SFC		114
+#define SRST_H_SFC_XIP		115
+#define SRST_S_SFC		116
+#define SRST_A_EMMC		117
+#define SRST_H_EMMC		118
+#define SRST_B_EMMC		119
+#define SRST_C_EMMC		120
+#define SRST_T_EMMC		121
+
+/* cru_softrst_con8 */
+#define SRST_A_PIPE_NIU		128
+#define SRST_P_PIPE_NIU		130
+#define SRST_P_PIPE_GRF		133
+#define SRST_A_SATA0		134
+#define SRST_SATA0_PIPE		135
+#define SRST_SATA0_PMALIVE	136
+#define SRST_SATA0_RXOOB	137
+#define SRST_A_SATA1		138
+#define SRST_SATA1_PIPE		139
+#define SRST_SATA1_PMALIVE	140
+#define SRST_SATA1_RXOOB	141
+
+/* cru_softrst_con9 */
+#define SRST_A_SATA2		144
+#define SRST_SATA2_PIPE		145
+#define SRST_SATA2_PMALIVE	146
+#define SRST_SATA2_RXOOB	147
+#define SRST_USB3OTG0		148
+#define SRST_USB3OTG1		149
+#define SRST_XPCS		150
+#define SRST_XPCS_TX_DIV10	151
+#define SRST_XPCS_RX_DIV10	152
+#define SRST_XPCS_XGXS_RX	153
+
+/* cru_softrst_con10 */
+#define SRST_P_PCIE20		160
+#define SRST_PCIE20_POWERUP	161
+#define SRST_MSTR_ARESET_PCIE20	162
+#define SRST_SLV_ARESET_PCIE20	163
+#define SRST_DBI_ARESET_PCIE20	164
+#define SRST_BRESET_PCIE20	165
+#define SRST_PERST_PCIE20	166
+#define SRST_CORE_RST_PCIE20	167
+#define SRST_NSTICKY_RST_PCIE20	168
+#define SRST_STICKY_RST_PCIE20	169
+#define SRST_PWR_RST_PCIE20	170
+
+/* cru_softrst_con11 */
+#define SRST_P_PCIE30X1		176
+#define SRST_PCIE30X1_POWERUP	177
+#define SRST_M_ARESET_PCIE30X1	178
+#define SRST_S_ARESET_PCIE30X1	179
+#define SRST_D_ARESET_PCIE30X1	180
+#define SRST_BRESET_PCIE30X1	181
+#define SRST_PERST_PCIE30X1	182
+#define SRST_CORE_RST_PCIE30X1	183
+#define SRST_NSTC_RST_PCIE30X1	184
+#define SRST_STC_RST_PCIE30X1	185
+#define SRST_PWR_RST_PCIE30X1	186
+
+/* cru_softrst_con12 */
+#define SRST_P_PCIE30X2		192
+#define SRST_PCIE30X2_POWERUP	193
+#define SRST_M_ARESET_PCIE30X2	194
+#define SRST_S_ARESET_PCIE30X2	195
+#define SRST_D_ARESET_PCIE30X2	196
+#define SRST_BRESET_PCIE30X2	197
+#define SRST_PERST_PCIE30X2	198
+#define SRST_CORE_RST_PCIE30X2	199
+#define SRST_NSTC_RST_PCIE30X2	200
+#define SRST_STC_RST_PCIE30X2	201
+#define SRST_PWR_RST_PCIE30X2	202
+
+/* cru_softrst_con13 */
+#define SRST_A_PHP_NIU		208
+#define SRST_H_PHP_NIU		209
+#define SRST_P_PHP_NIU		210
+#define SRST_H_SDMMC0		211
+#define SRST_SDMMC0		212
+#define SRST_H_SDMMC1		213
+#define SRST_SDMMC1		214
+#define SRST_A_GMAC0		215
+#define SRST_GMAC0_TIMESTAMP	216
+
+/* cru_softrst_con14 */
+#define SRST_A_USB_NIU		224
+#define SRST_H_USB_NIU		225
+#define SRST_P_USB_NIU		226
+#define SRST_P_USB_GRF		227
+#define SRST_H_USB2HOST0	228
+#define SRST_H_USB2HOST0_ARB	229
+#define SRST_USB2HOST0_UTMI	230
+#define SRST_H_USB2HOST1	231
+#define SRST_H_USB2HOST1_ARB	232
+#define SRST_USB2HOST1_UTMI	233
+#define SRST_H_SDMMC2		234
+#define SRST_SDMMC2		235
+#define SRST_A_GMAC1		236
+#define SRST_GMAC1_TIMESTAMP	237
+
+/* cru_softrst_con15 */
+#define SRST_A_VI_NIU		240
+#define SRST_H_VI_NIU		241
+#define SRST_P_VI_NIU		242
+#define SRST_A_VICAP		247
+#define SRST_H_VICAP		248
+#define SRST_D_VICAP		249
+#define SRST_I_VICAP		250
+#define SRST_P_VICAP		251
+#define SRST_H_ISP		252
+#define SRST_ISP		253
+#define SRST_P_CSI2HOST1	255
+
+/* cru_softrst_con16 */
+#define SRST_A_VO_NIU		256
+#define SRST_H_VO_NIU		257
+#define SRST_P_VO_NIU		258
+#define SRST_A_VOP_NIU		259
+#define SRST_A_VOP		260
+#define SRST_H_VOP		261
+#define SRST_VOP0		262
+#define SRST_VOP1		263
+#define SRST_VOP2		264
+#define SRST_VOP_PWM		265
+#define SRST_A_HDCP		266
+#define SRST_H_HDCP		267
+#define SRST_P_HDCP		268
+#define SRST_P_HDMI_HOST	270
+#define SRST_HDMI_HOST		271
+
+/* cru_softrst_con17 */
+#define SRST_P_DSITX_0		272
+#define SRST_P_DSITX_1		273
+#define SRST_P_EDP_CTRL		274
+#define SRST_EDP_24M		275
+#define SRST_A_VPU_NIU		280
+#define SRST_H_VPU_NIU		281
+#define SRST_A_VPU		282
+#define SRST_H_VPU		283
+#define SRST_H_EINK		286
+#define SRST_P_EINK		287
+
+/* cru_softrst_con18 */
+#define SRST_A_RGA_NIU		288
+#define SRST_H_RGA_NIU		289
+#define SRST_P_RGA_NIU		290
+#define SRST_A_RGA		292
+#define SRST_H_RGA		293
+#define SRST_RGA_CORE		294
+#define SRST_A_IEP		295
+#define SRST_H_IEP		296
+#define SRST_IEP_CORE		297
+#define SRST_H_EBC		298
+#define SRST_D_EBC		299
+#define SRST_A_JDEC		300
+#define SRST_H_JDEC		301
+#define SRST_A_JENC		302
+#define SRST_H_JENC		303
+
+/* cru_softrst_con19 */
+#define SRST_A_VENC_NIU		304
+#define SRST_H_VENC_NIU		305
+#define SRST_A_RKVENC		307
+#define SRST_H_RKVENC		308
+#define SRST_RKVENC_CORE	309
+
+/* cru_softrst_con20 */
+#define SRST_A_RKVDEC_NIU	320
+#define SRST_H_RKVDEC_NIU	321
+#define SRST_A_RKVDEC		322
+#define SRST_H_RKVDEC		323
+#define SRST_RKVDEC_CA		324
+#define SRST_RKVDEC_CORE	325
+#define SRST_RKVDEC_HEVC_CA	326
+
+/* cru_softrst_con21 */
+#define SRST_A_BUS_NIU		336
+#define SRST_P_BUS_NIU		338
+#define SRST_P_CAN0		340
+#define SRST_CAN0		341
+#define SRST_P_CAN1		342
+#define SRST_CAN1		343
+#define SRST_P_CAN2		344
+#define SRST_CAN2		345
+#define SRST_P_GPIO1		346
+#define SRST_GPIO1		347
+#define SRST_P_GPIO2		348
+#define SRST_GPIO2		349
+#define SRST_P_GPIO3		350
+#define SRST_GPIO3		351
+
+/* cru_softrst_con22 */
+#define SRST_P_GPIO4		352
+#define SRST_GPIO4		353
+#define SRST_P_I2C1		354
+#define SRST_I2C1		355
+#define SRST_P_I2C2		356
+#define SRST_I2C2		357
+#define SRST_P_I2C3		358
+#define SRST_I2C3		359
+#define SRST_P_I2C4		360
+#define SRST_I2C4		361
+#define SRST_P_I2C5		362
+#define SRST_I2C5		363
+#define SRST_P_OTPC_NS		364
+#define SRST_OTPC_NS_SBPI	365
+#define SRST_OTPC_NS_USR	366
+
+/* cru_softrst_con23 */
+#define SRST_P_PWM1		368
+#define SRST_PWM1		369
+#define SRST_P_PWM2		370
+#define SRST_PWM2		371
+#define SRST_P_PWM3		372
+#define SRST_PWM3		373
+#define SRST_P_SPI0		374
+#define SRST_SPI0		375
+#define SRST_P_SPI1		376
+#define SRST_SPI1		377
+#define SRST_P_SPI2		378
+#define SRST_SPI2		379
+#define SRST_P_SPI3		380
+#define SRST_SPI3		381
+
+/* cru_softrst_con24 */
+#define SRST_P_SARADC		384
+#define SRST_P_TSADC		385
+#define SRST_TSADC		386
+#define SRST_P_TIMER		387
+#define SRST_TIMER0		388
+#define SRST_TIMER1		389
+#define SRST_TIMER2		390
+#define SRST_TIMER3		391
+#define SRST_TIMER4		392
+#define SRST_TIMER5		393
+#define SRST_P_UART1		394
+#define SRST_S_UART1		395
+
+/* cru_softrst_con25 */
+#define SRST_P_UART2		400
+#define SRST_S_UART2		401
+#define SRST_P_UART3		402
+#define SRST_S_UART3		403
+#define SRST_P_UART4		404
+#define SRST_S_UART4		405
+#define SRST_P_UART5		406
+#define SRST_S_UART5		407
+#define SRST_P_UART6		408
+#define SRST_S_UART6		409
+#define SRST_P_UART7		410
+#define SRST_S_UART7		411
+#define SRST_P_UART8		412
+#define SRST_S_UART8		413
+#define SRST_P_UART9		414
+#define SRST_S_UART9		415
+
+/* cru_softrst_con26 */
+#define SRST_P_GRF 416
+#define SRST_P_GRF_VCCIO12	417
+#define SRST_P_GRF_VCCIO34	418
+#define SRST_P_GRF_VCCIO567	419
+#define SRST_P_SCR		420
+#define SRST_P_WDT_NS		421
+#define SRST_T_WDT_NS		422
+#define SRST_P_DFT2APB		423
+#define SRST_A_MCU		426
+#define SRST_P_INTMUX		427
+#define SRST_P_MAILBOX		428
+
+/* cru_softrst_con27 */
+#define SRST_A_TOP_HIGH_NIU	432
+#define SRST_A_TOP_LOW_NIU	433
+#define SRST_H_TOP_NIU		434
+#define SRST_P_TOP_NIU		435
+#define SRST_P_TOP_CRU		438
+#define SRST_P_DDRPHY		439
+#define SRST_DDRPHY		440
+#define SRST_P_MIPICSIPHY	442
+#define SRST_P_MIPIDSIPHY0	443
+#define SRST_P_MIPIDSIPHY1	444
+#define SRST_P_PCIE30PHY	445
+#define SRST_PCIE30PHY		446
+#define SRST_P_PCIE30PHY_GRF	447
+
+/* cru_softrst_con28 */
+#define SRST_P_APB2ASB_LEFT	448
+#define SRST_P_APB2ASB_BOTTOM	449
+#define SRST_P_ASB2APB_LEFT	450
+#define SRST_P_ASB2APB_BOTTOM	451
+#define SRST_P_PIPEPHY0		452
+#define SRST_PIPEPHY0		453
+#define SRST_P_PIPEPHY1		454
+#define SRST_PIPEPHY1		455
+#define SRST_P_PIPEPHY2		456
+#define SRST_PIPEPHY2		457
+#define SRST_P_USB2PHY0_GRF	458
+#define SRST_P_USB2PHY1_GRF	459
+#define SRST_P_CPU_BOOST	460
+#define SRST_CPU_BOOST		461
+#define SRST_P_OTPPHY		462
+#define SRST_OTPPHY		463
+
+/* cru_softrst_con29 */
+#define SRST_USB2PHY0_POR	464
+#define SRST_USB2PHY0_USB3OTG0	465
+#define SRST_USB2PHY0_USB3OTG1	466
+#define SRST_USB2PHY1_POR	467
+#define SRST_USB2PHY1_USB2HOST0	468
+#define SRST_USB2PHY1_USB2HOST1	469
+#define SRST_P_EDPPHY_GRF	470
+#define SRST_TSADCPHY		471
+#define SRST_GMAC0_DELAYLINE	472
+#define SRST_GMAC1_DELAYLINE	473
+#define SRST_OTPC_ARB		474
+#define SRST_P_PIPEPHY0_GRF	475
+#define SRST_P_PIPEPHY1_GRF	476
+#define SRST_P_PIPEPHY2_GRF	477
+
+#endif