Merge tag 'fsl-qoriq-2023-7-13' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriqWIP/19Jul2023

Enable DM_SERIAL for T2080RDB, T4240RDB, T1042D4RDB, T1024RDB

25 files changed, 153 insertions, 19 deletions

diff --git a/arch/powerpc/dts/t1023si-post.dtsi b/arch/powerpc/dts/t1023si-post.dtsi
index 6f666a1..0cd34fe 100644
--- a/arch/powerpc/dts/t1023si-post.dtsi
+++ b/arch/powerpc/dts/t1023si-post.dtsi
@@ -3,13 +3,15 @@
  * T1023 Silicon/SoC Device Tree Source (post include)
  *
  * Copyright 2014 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2023 NXP
  *
  */
 
 &soc {
 
 /include/ "qoriq-clockgen2.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
 /include/ "qoriq-gpio-0.dtsi"
 /include/ "qoriq-gpio-1.dtsi"
 /include/ "qoriq-gpio-2.dtsi"
diff --git a/arch/powerpc/dts/t1024rdb-u-boot.dtsi b/arch/powerpc/dts/t1024rdb-u-boot.dtsi
new file mode 100644
index 0000000..b50b922
--- /dev/null
+++ b/arch/powerpc/dts/t1024rdb-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+&serial0 {
+	bootph-all;
+};
+
+&serial1 {
+	bootph-all;
+};
+
+#include "u-boot.dtsi"
diff --git a/arch/powerpc/dts/t1024rdb.dts b/arch/powerpc/dts/t1024rdb.dts
index eeba99f..afaf90c 100644
--- a/arch/powerpc/dts/t1024rdb.dts
+++ b/arch/powerpc/dts/t1024rdb.dts
@@ -3,7 +3,7 @@
  * T1024RDB Device Tree Source
  *
  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2023 NXP
  */
 
 /include/ "t102x.dtsi"
@@ -17,6 +17,10 @@
 
 	aliases {
 		sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4;
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
 		spi0 = &espi0;
 	};
 
diff --git a/arch/powerpc/dts/t1042d4rdb-u-boot.dtsi b/arch/powerpc/dts/t1042d4rdb-u-boot.dtsi
new file mode 100644
index 0000000..b50b922
--- /dev/null
+++ b/arch/powerpc/dts/t1042d4rdb-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+&serial0 {
+	bootph-all;
+};
+
+&serial1 {
+	bootph-all;
+};
+
+#include "u-boot.dtsi"
diff --git a/arch/powerpc/dts/t1042d4rdb.dts b/arch/powerpc/dts/t1042d4rdb.dts
index 5e9fab7..0230d3b 100644
--- a/arch/powerpc/dts/t1042d4rdb.dts
+++ b/arch/powerpc/dts/t1042d4rdb.dts
@@ -3,7 +3,7 @@
  * T1042D4RDB Device Tree Source
  *
  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2021 NXP
+ * Copyright 2019-2023 NXP
  */
 
 /include/ "t104x.dtsi"
@@ -17,6 +17,10 @@
 
 	aliases {
 		spi0 = &espi0;
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
 	};
 };
 
diff --git a/arch/powerpc/dts/t1042si-post.dtsi b/arch/powerpc/dts/t1042si-post.dtsi
index eebbbaf..9f4fd72 100644
--- a/arch/powerpc/dts/t1042si-post.dtsi
+++ b/arch/powerpc/dts/t1042si-post.dtsi
@@ -3,11 +3,13 @@
  * T1042 Silicon/SoC Device Tree Source (post include)
  *
  * Copyright 2013 - 2014 Freescale Semiconductor Inc.
- * Copyright 2021 NXP
+ * Copyright 2021-2023 NXP
  *
  */
 &soc {
 /include/ "qoriq-clockgen2.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
 /include/ "qoriq-gpio-0.dtsi"
 /include/ "qoriq-gpio-1.dtsi"
 /include/ "qoriq-gpio-2.dtsi"
diff --git a/arch/powerpc/dts/t2080rdb-u-boot.dtsi b/arch/powerpc/dts/t2080rdb-u-boot.dtsi
new file mode 100644
index 0000000..b50b922
--- /dev/null
+++ b/arch/powerpc/dts/t2080rdb-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+&serial0 {
+	bootph-all;
+};
+
+&serial1 {
+	bootph-all;
+};
+
+#include "u-boot.dtsi"
diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts
index 4de814e..c0b0bd6 100644
--- a/arch/powerpc/dts/t2080rdb.dts
+++ b/arch/powerpc/dts/t2080rdb.dts
@@ -3,7 +3,7 @@
  * T2080RDB Device Tree Source
  *
  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2021 NXP
+ * Copyright 2019-2023 NXP
  */
 
 /include/ "t2080.dtsi"
@@ -17,6 +17,10 @@
 
 	aliases {
 		spi0 = &espi0;
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
 	};
 };
 
diff --git a/arch/powerpc/dts/t2080si-post.dtsi b/arch/powerpc/dts/t2080si-post.dtsi
index c06526b..46053c6 100644
--- a/arch/powerpc/dts/t2080si-post.dtsi
+++ b/arch/powerpc/dts/t2080si-post.dtsi
@@ -3,12 +3,14 @@
  * T2080 Silicon/SoC Device Tree Source (post include)
  *
  * Copyright 2013 Freescale Semiconductor Inc.
- * Copyright 2021 NXP
+ * Copyright 2021-2023 NXP
  *
  */
 &soc {
 
 /include/ "qoriq-clockgen2.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
 /include/ "qoriq-gpio-0.dtsi"
 /include/ "qoriq-gpio-1.dtsi"
 /include/ "qoriq-gpio-2.dtsi"
diff --git a/arch/powerpc/dts/t4240rdb-u-boot.dtsi b/arch/powerpc/dts/t4240rdb-u-boot.dtsi
new file mode 100644
index 0000000..b50b922
--- /dev/null
+++ b/arch/powerpc/dts/t4240rdb-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2023 NXP */
+
+&serial0 {
+	bootph-all;
+};
+
+&serial1 {
+	bootph-all;
+};
+
+#include "u-boot.dtsi"
diff --git a/arch/powerpc/dts/t4240rdb.dts b/arch/powerpc/dts/t4240rdb.dts
index b3251e3..c33b498 100644
--- a/arch/powerpc/dts/t4240rdb.dts
+++ b/arch/powerpc/dts/t4240rdb.dts
@@ -3,7 +3,7 @@
  * T4240RDB Device Tree Source
  *
  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2021 NXP
+ * Copyright 2019-2023 NXP
  */
 
 /include/ "t4240.dtsi"
@@ -17,6 +17,10 @@
 
 	aliases {
 		spi0 = &espi0;
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
 	};
 };
 
diff --git a/arch/powerpc/dts/t4240si-post.dtsi b/arch/powerpc/dts/t4240si-post.dtsi
index 9fa99ae..bd93345 100644
--- a/arch/powerpc/dts/t4240si-post.dtsi
+++ b/arch/powerpc/dts/t4240si-post.dtsi
@@ -3,11 +3,13 @@
  * T4240 Silicon/SoC Device Tree Source (post include)
  *
  * Copyright 2012 - 2015 Freescale Semiconductor Inc.
- * Copyright 2021 NXP
+ * Copyright 2021-2023 NXP
  *
  */
 &soc {
 /include/ "qoriq-clockgen2.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
 /include/ "qoriq-gpio-0.dtsi"
 /include/ "qoriq-gpio-1.dtsi"
 /include/ "qoriq-gpio-2.dtsi"
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index baa5961..73f9d3a 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2023 NXP
  */
 
 #include <common.h>
@@ -20,6 +20,7 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_liodn.h>
+#include <clock_legacy.h>
 #include <fm_eth.h>
 #include "t102xrdb.h"
 #ifdef CONFIG_TARGET_T1024RDB
@@ -45,6 +46,13 @@ enum {
 };
 #endif
 
+#if CONFIG_IS_ENABLED(DM_SERIAL)
+int get_serial_clock(void)
+{
+	return get_bus_freq(0) / 2;
+}
+#endif
+
 int checkboard(void)
 {
 	struct cpu_type *cpu = gd->arch.cpu;
@@ -159,6 +167,8 @@ int board_early_init_r(void)
 	board_mux_lane();
 #endif
 
+	pci_init();
+
 	return 0;
 }
 
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index 8cec712..b308049 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2023 NXP
  */
 
 #include <common.h>
@@ -22,6 +23,7 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_liodn.h>
+#include <clock_legacy.h>
 #include <fm_eth.h>
 #include "../common/sleep.h"
 #include "t104xrdb.h"
@@ -29,6 +31,13 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if CONFIG_IS_ENABLED(DM_SERIAL)
+int get_serial_clock(void)
+{
+	return get_bus_freq(0) / 2;
+}
+#endif
+
 int checkboard(void)
 {
 	struct cpu_type *cpu = gd->arch.cpu;
@@ -88,6 +97,9 @@ int board_early_init_r(void)
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 #endif
+
+	pci_init();
+
 	return 0;
 }
 
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index 04cb313..e33e5d0 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2009-2013 Freescale Semiconductor, Inc.
- * Copyright 2021 NXP
+ * Copyright 2021-2023 NXP
  */
 
 #include <common.h>
@@ -20,6 +20,7 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_liodn.h>
+#include <clock_legacy.h>
 #include <fm_eth.h>
 #include "t208xrdb.h"
 #include "cpld.h"
@@ -42,6 +43,13 @@ u8 get_hw_revision(void)
 	}
 }
 
+#if CONFIG_IS_ENABLED(DM_SERIAL)
+int get_serial_clock(void)
+{
+	return get_bus_freq(0) / 2;
+}
+#endif
+
 int checkboard(void)
 {
 	struct cpu_type *cpu = gd->arch.cpu;
@@ -106,6 +114,9 @@ int board_early_init_r(void)
 	 */
 	if (adjust_vdd(0))
 		printf("Warning: Adjusting core voltage failed.\n");
+
+	pci_init();
+
 	return 0;
 }
 
diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
index 0bd0ba9..ab71776 100644
--- a/board/freescale/t4rdb/t4240rdb.c
+++ b/board/freescale/t4rdb/t4240rdb.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2023 NXP
  */
 
 #include <common.h>
@@ -20,6 +21,7 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_liodn.h>
+#include <clock_legacy.h>
 #include <fm_eth.h>
 
 #include "t4rdb.h"
@@ -28,6 +30,13 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if CONFIG_IS_ENABLED(DM_SERIAL)
+int get_serial_clock(void)
+{
+	return get_bus_freq(0) / 2;
+}
+#endif
+
 int checkboard(void)
 {
 	struct cpu_type *cpu = gd->arch.cpu;
@@ -86,6 +95,8 @@ int board_early_init_r(void)
 	if (adjust_vdd(0))
 		printf("Warning: Adjusting core voltage failed.\n");
 
+	pci_init();
+
 	return 0;
 }
 
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 5e8dfbf..0d0707e 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -101,7 +101,9 @@ CONFIG_SYS_QE_FW_ADDR=0xEFE00000
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1337=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 06eb06d..fe84f36 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -101,7 +101,9 @@ CONFIG_SYS_QE_FW_ADDR=0xEFF10000
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1337=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 8a85d49..e1e9630 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -106,7 +106,9 @@ CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1307=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig
index f5383cc..d9116df 100644
--- a/configs/T2080RDB_revD_defconfig
+++ b/configs/T2080RDB_revD_defconfig
@@ -108,7 +108,9 @@ CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1307=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index eddd6fb..4b63ef4 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -96,7 +96,9 @@ CONFIG_MII=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 7ee46ab..284291a 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020-2021 NXP
+ * Copyright 2020-2023 NXP
  */
 
 /*
@@ -283,7 +283,9 @@
 #define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /* Serial Port */
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
 #define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#endif
 
 #define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index f196bd7..01db298 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020-2021 NXP
+ * Copyright 2020-2023 NXP
  */
 
 #ifndef __CONFIG_H
@@ -238,7 +238,9 @@
  * open - index 2
  * shorted - index 1
  */
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
 #define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#endif
 
 #define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index f213d2d..0b9dde3 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020-2021 NXP
+ * Copyright 2020-2023 NXP
  */
 
 /*
@@ -215,7 +215,9 @@
 /*
  * Serial Port
  */
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
 #define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#endif
 #define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 506f1b7..78e1362 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020-2021 NXP
+ * Copyright 2020-2023 NXP
  */
 
 /*
@@ -77,7 +77,9 @@
  * open - index 2
  * shorted - index 1
  */
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
 #define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#endif
 
 #define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}