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authorMassimo Pegorer <massimo.pegorer+oss@gmail.com>2023-08-03 13:08:11 +0200
committerKever Yang <kever.yang@rock-chips.com>2023-08-12 10:37:57 +0800
commite4c6ccc6875638766970d249a6cb5dacce6822fe (patch)
tree3fcae2f77e2e2668f4e0f328a80448e03b7e1914
parent36adce73724d53f0a22520af86690381b69518aa (diff)
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clk: rockchip: rk3308: Fix ordering between masking and shifting
As per definitions of masks and shift offsets in cru_rk3308.h, values read from registers must be first masked and then shifted. By the way, this fix is binary invariant, because in all of fixed cases the shift offset is zero. Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
-rw-r--r--drivers/clk/rockchip/clk_rk3308.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c
index 64f3358..d27673c 100644
--- a/drivers/clk/rockchip/clk_rk3308.c
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -150,7 +150,7 @@ static ulong rk3308_i2c_get_clk(struct clk *clk)
}
con = readl(&cru->clksel_con[con_id]);
- div = con >> CLK_I2C_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
+ div = (con & CLK_I2C_DIV_CON_MASK) >> CLK_I2C_DIV_CON_SHIFT;
return DIV_TO_RATE(priv->dpll_hz, div);
}
@@ -314,7 +314,7 @@ static ulong rk3308_saradc_get_clk(struct clk *clk)
u32 div, con;
con = readl(&cru->clksel_con[34]);
- div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
+ div = (con & CLK_SARADC_DIV_CON_MASK) >> CLK_SARADC_DIV_CON_SHIFT;
return DIV_TO_RATE(OSC_HZ, div);
}
@@ -342,7 +342,7 @@ static ulong rk3308_tsadc_get_clk(struct clk *clk)
u32 div, con;
con = readl(&cru->clksel_con[33]);
- div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
+ div = (con & CLK_SARADC_DIV_CON_MASK) >> CLK_SARADC_DIV_CON_SHIFT;
return DIV_TO_RATE(OSC_HZ, div);
}
@@ -385,7 +385,7 @@ static ulong rk3308_spi_get_clk(struct clk *clk)
}
con = readl(&cru->clksel_con[con_id]);
- div = con >> CLK_SPI_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK;
+ div = (con & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
return DIV_TO_RATE(priv->dpll_hz, div);
}
@@ -429,7 +429,7 @@ static ulong rk3308_pwm_get_clk(struct clk *clk)
u32 div, con;
con = readl(&cru->clksel_con[29]);
- div = con >> CLK_PWM_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK;
+ div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
return DIV_TO_RATE(priv->dpll_hz, div);
}