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author | Dario Binacchi <dario.binacchi@amarulasolutions.com> | 2023-11-11 11:46:19 +0100 |
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committer | Patrice Chotard <patrice.chotard@foss.st.com> | 2023-12-15 15:03:18 +0100 |
commit | 767ca6d6827281744641180e4ac2921f5b828893 (patch) | |
tree | 6d2885b4c07671f25aa7de80c040de8f9524674d | |
parent | bd6eb5ddd715e7441d804c67f434418e172a1423 (diff) | |
download | u-boot-767ca6d6827281744641180e4ac2921f5b828893.zip u-boot-767ca6d6827281744641180e4ac2921f5b828893.tar.gz u-boot-767ca6d6827281744641180e4ac2921f5b828893.tar.bz2 |
clk: stm32f: fix setting of LCD clock
Set pllsaidivr only if the PLLSAIR output frequency is an exact multiple
of the pixel clock rate. Otherwise, we search through all combinations
of pllsaidivr * pllsair and use the one which gives the rate closest to
requested one.
Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
-rw-r--r-- | drivers/clk/stm32/clk-stm32f.c | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index 4c18641..d68c75e 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -522,18 +522,20 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate) /* get the current PLLSAIR output freq */ pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR); - best_div = pllsair_rate / rate; - - /* look into pllsaidivr_table if this divider is available*/ - for (i = 0 ; i < sizeof(pllsaidivr_table); i++) - if (best_div == pllsaidivr_table[i]) { - /* set pll_saidivr with found value */ - clrsetbits_le32(®s->dckcfgr, - RCC_DCKCFGR_PLLSAIDIVR_MASK, - pllsaidivr_table[i] << - RCC_DCKCFGR_PLLSAIDIVR_SHIFT); - return rate; - } + if ((pllsair_rate % rate) == 0) { + best_div = pllsair_rate / rate; + + /* look into pllsaidivr_table if this divider is available */ + for (i = 0 ; i < sizeof(pllsaidivr_table); i++) + if (best_div == pllsaidivr_table[i]) { + /* set pll_saidivr with found value */ + clrsetbits_le32(®s->dckcfgr, + RCC_DCKCFGR_PLLSAIDIVR_MASK, + pllsaidivr_table[i] << + RCC_DCKCFGR_PLLSAIDIVR_SHIFT); + return rate; + } + } /* * As no pllsaidivr value is suitable to obtain requested freq, |