aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorTom Rini <trini@konsulko.com>2023-03-16 12:18:30 -0400
committerTom Rini <trini@konsulko.com>2023-03-16 12:18:30 -0400
commitcefd0449d6df77eb0edb8a6800a441f9cd4e3653 (patch)
treeba939b19698ff7f7dee9f274d9ecb20733cbe09f
parente63828bf35ac5632bd584980df5014c7c3e8c44d (diff)
parent7ac50f88f8a9374e5cb4bc2a88c002d02ef3c570 (diff)
downloadu-boot-WIP/16Mar2023-next.zip
u-boot-WIP/16Mar2023-next.tar.gz
u-boot-WIP/16Mar2023-next.tar.bz2
Merge tag 'xilinx-for-v2023.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into nextWIP/16Mar2023-next
Xilinx changes for v2023.07-rc1 cmd: - Print results in hex instead of dec in smc command firmware: - Cover missing ZYNQMP_FIRMWARE dependencies fpga: - fix loads for unencrypted use case relocation - Add support for BE systems spi: - Fix xilinx_spi init reset sequence arasan nand: - Remove hardcoded bbt option - Set ofnode value xilinx: - Enable SMC command - Fix some sparse issues zynqmp: - Remove cdns,zynq-gem compatible string - Add optee node - Some DT cleanups zynq: - Some DT cleanups microblaze - Remove MANUAL_RELOC option
-rw-r--r--arch/arm/dts/zynq-7000.dtsi14
-rw-r--r--arch/arm/dts/zynq-zc702.dts4
-rw-r--r--arch/arm/dts/zynq-zturn-common.dtsi2
-rw-r--r--arch/arm/dts/zynqmp-sck-kr-g-revA.dts2
-rw-r--r--arch/arm/dts/zynqmp-sck-kr-g-revB.dts2
-rw-r--r--arch/arm/dts/zynqmp-sck-kv-g-revA.dts4
-rw-r--r--arch/arm/dts/zynqmp-sck-kv-g-revB.dts4
-rw-r--r--arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts2
-rw-r--r--arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts119
-rw-r--r--arch/arm/dts/zynqmp-zcu100-revC.dts2
-rw-r--r--arch/arm/dts/zynqmp.dtsi15
-rw-r--r--arch/arm/mach-versal-net/include/mach/sys_proto.h7
-rw-r--r--arch/arm/mach-versal/include/mach/sys_proto.h6
-rw-r--r--arch/microblaze/Kconfig13
-rw-r--r--arch/microblaze/config.mk4
-rw-r--r--arch/microblaze/cpu/Makefile3
-rw-r--r--arch/microblaze/cpu/start.S28
-rw-r--r--board/xilinx/zynqmp/Kconfig1
-rw-r--r--cmd/smccc.c2
-rw-r--r--configs/xilinx_versal_net_virt_defconfig1
-rw-r--r--configs/xilinx_versal_virt_defconfig1
-rw-r--r--configs/xilinx_zynqmp_virt_defconfig1
-rw-r--r--drivers/clk/Kconfig4
-rw-r--r--drivers/fpga/Kconfig2
-rw-r--r--drivers/fpga/zynqmppl.c12
-rw-r--r--drivers/mmc/zynq_sdhci.c5
-rw-r--r--drivers/mtd/nand/raw/arasan_nfc.c5
-rw-r--r--drivers/net/zynq_gem.c2
-rw-r--r--drivers/spi/xilinx_spi.c5
-rw-r--r--drivers/spi/zynqmp_gqspi.c5
-rw-r--r--include/spl.h1
-rw-r--r--tools/relocate-rela.c52
32 files changed, 175 insertions, 155 deletions
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 149c644..97a9e49 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -258,7 +258,7 @@
};
gem0: ethernet@e000b000 {
- compatible = "xlnx,zynq-gem", "cdns,zynq-gem", "cdns,gem";
+ compatible = "xlnx,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "disabled";
interrupts = <0 22 4>;
@@ -269,7 +269,7 @@
};
gem1: ethernet@e000c000 {
- compatible = "xlnx,zynq-gem", "cdns,zynq-gem", "cdns,gem";
+ compatible = "xlnx,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0 45 4>;
@@ -369,20 +369,20 @@
};
};
- dmac_s: dmac@f8003000 {
+ dmac_s: dma-controller@f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <&intc>;
- interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
- "dma4", "dma5", "dma6", "dma7";
+ /*
+ * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
+ * "dma4", "dma5", "dma6", "dma7";
+ */
interrupts = <0 13 4>,
<0 14 4>, <0 15 4>,
<0 16 4>, <0 17 4>,
<0 40 4>, <0 41 4>,
<0 42 4>, <0 43 4>;
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <4>;
clocks = <&clkc 27>;
clock-names = "apb_pclk";
};
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 24ad49e..27fb194 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -34,14 +34,14 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- sw14 {
+ switch-14 {
label = "sw14";
gpios = <&gpio0 12 0>;
linux,code = <108>; /* down */
wakeup-source;
autorepeat;
};
- sw13 {
+ switch-13 {
label = "sw13";
gpios = <&gpio0 14 0>;
linux,code = <103>; /* up */
diff --git a/arch/arm/dts/zynq-zturn-common.dtsi b/arch/arm/dts/zynq-zturn-common.dtsi
index edba3d8..c849c24 100644
--- a/arch/arm/dts/zynq-zturn-common.dtsi
+++ b/arch/arm/dts/zynq-zturn-common.dtsi
@@ -49,7 +49,7 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- K1 {
+ key {
label = "K1";
gpios = <&gpio0 0x32 0x1>;
linux,code = <0x66>;
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
index 83c6502..c82e1df 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
@@ -229,7 +229,7 @@
/* gem2/gem3 via PL with phys u79@2 and u80@3 */
-&pinctrl0 { /* required by spec */
+&pinctrl0 {
status = "okay";
pinctrl_uart1_default: uart1-default {
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
index f41a2f8..9dd160c 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
@@ -229,7 +229,7 @@
/* gem2/gem3 via PL with phys u79@2 and u80@3 */
-&pinctrl0 { /* required by spec */
+&pinctrl0 {
status = "okay";
pinctrl_uart1_default: uart1-default {
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index 0be5b29..6f5a426 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -159,7 +159,7 @@
bus-width = <8>;
};
-&gem3 { /* required by spec */
+&gem3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
@@ -185,7 +185,7 @@
};
};
-&pinctrl0 { /* required by spec */
+&pinctrl0 {
status = "okay";
pinctrl_uart1_default: uart1-default {
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index fca57a6..7764adf 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -146,7 +146,7 @@
bus-width = <8>;
};
-&gem3 { /* required by spec */
+&gem3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
@@ -172,7 +172,7 @@
};
};
-&pinctrl0 { /* required by spec */
+&pinctrl0 {
status = "okay";
pinctrl_uart1_default: uart1-default {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 4e6160bc..b6bc2f5 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -142,6 +142,7 @@
label = "main-storage-0";
nand-ecc-step-size = <1024>;
nand-ecc-strength = <24>;
+ nand-on-flash-bbt;
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
@@ -178,6 +179,7 @@
label = "main-storage-1";
nand-ecc-step-size = <1024>;
nand-ecc-strength = <24>;
+ nand-on-flash-bbt;
partition@0 { /* for testing purpose */
label = "nand1-fsbl-uboot";
diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
index 1381247..6021f8b 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@@ -128,54 +128,79 @@
arasan,has-mdma;
num-cs = <2>;
- partition@0 { /* for testing purpose */
- label = "nand-fsbl-uboot";
- reg = <0x0 0x0 0x400000>;
+ nand@0 {
+ reg = <0x0>;
+ #address-cells = <0x2>;
+ #size-cells = <0x1>;
+ nand-ecc-mode = "soft";
+ nand-ecc-algo = "bch";
+ nand-rb = <0>;
+ label = "main-storage-0";
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-on-flash-bbt;
+
+ partition@0 { /* for testing purpose */
+ label = "nand-fsbl-uboot";
+ reg = <0x0 0x0 0x400000>;
+ };
+ partition@1 { /* for testing purpose */
+ label = "nand-linux";
+ reg = <0x0 0x400000 0x1400000>;
+ };
+ partition@2 { /* for testing purpose */
+ label = "nand-device-tree";
+ reg = <0x0 0x1800000 0x400000>;
+ };
+ partition@3 { /* for testing purpose */
+ label = "nand-rootfs";
+ reg = <0x0 0x1C00000 0x1400000>;
+ };
+ partition@4 { /* for testing purpose */
+ label = "nand-bitstream";
+ reg = <0x0 0x3000000 0x400000>;
+ };
+ partition@5 { /* for testing purpose */
+ label = "nand-misc";
+ reg = <0x0 0x3400000 0xFCC00000>;
+ };
};
- partition@1 { /* for testing purpose */
- label = "nand-linux";
- reg = <0x0 0x400000 0x1400000>;
- };
- partition@2 { /* for testing purpose */
- label = "nand-device-tree";
- reg = <0x0 0x1800000 0x400000>;
- };
- partition@3 { /* for testing purpose */
- label = "nand-rootfs";
- reg = <0x0 0x1C00000 0x1400000>;
- };
- partition@4 { /* for testing purpose */
- label = "nand-bitstream";
- reg = <0x0 0x3000000 0x400000>;
- };
- partition@5 { /* for testing purpose */
- label = "nand-misc";
- reg = <0x0 0x3400000 0xFCC00000>;
- };
-
- partition@6 { /* for testing purpose */
- label = "nand1-fsbl-uboot";
- reg = <0x1 0x0 0x400000>;
- };
- partition@7 { /* for testing purpose */
- label = "nand1-linux";
- reg = <0x1 0x400000 0x1400000>;
- };
- partition@8 { /* for testing purpose */
- label = "nand1-device-tree";
- reg = <0x1 0x1800000 0x400000>;
- };
- partition@9 { /* for testing purpose */
- label = "nand1-rootfs";
- reg = <0x1 0x1C00000 0x1400000>;
- };
- partition@10 { /* for testing purpose */
- label = "nand1-bitstream";
- reg = <0x1 0x3000000 0x400000>;
- };
- partition@11 { /* for testing purpose */
- label = "nand1-misc";
- reg = <0x1 0x3400000 0xFCC00000>;
+ nand@1 {
+ reg = <0x1>;
+ #address-cells = <0x2>;
+ #size-cells = <0x1>;
+ nand-ecc-mode = "soft";
+ nand-ecc-algo = "bch";
+ nand-rb = <0>;
+ label = "main-storage-1";
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-on-flash-bbt;
+
+ partition@0 { /* for testing purpose */
+ label = "nand1-fsbl-uboot";
+ reg = <0x0 0x0 0x400000>;
+ };
+ partition@1 { /* for testing purpose */
+ label = "nand1-linux";
+ reg = <0x0 0x400000 0x1400000>;
+ };
+ partition@2 { /* for testing purpose */
+ label = "nand1-device-tree";
+ reg = <0x0 0x1800000 0x400000>;
+ };
+ partition@3 { /* for testing purpose */
+ label = "nand1-rootfs";
+ reg = <0x0 0x1C00000 0x1400000>;
+ };
+ partition@4 { /* for testing purpose */
+ label = "nand1-bitstream";
+ reg = <0x0 0x3000000 0x400000>;
+ };
+ partition@5 { /* for testing purpose */
+ label = "nand1-misc";
+ reg = <0x0 0x3400000 0xFCC00000>;
+ };
};
};
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index eea703a..742a539 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -95,7 +95,7 @@
linux,default-trigger = "bluetooth-power";
};
- vbus-det { /* U5 USB5744 VBUS detection via MIO25 */
+ led-vbus-det { /* U5 USB5744 VBUS detection via MIO25 */
label = "vbus_det";
gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
default-state = "on";
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index b74fb3b..6a16638 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -147,6 +147,11 @@
};
firmware {
+ optee: optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
#power-domain-cells = <1>;
@@ -529,7 +534,7 @@
};
gem0: ethernet@ff0b0000 {
- compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem";
+ compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 57 4>, <0 57 4>;
@@ -544,7 +549,7 @@
};
gem1: ethernet@ff0c0000 {
- compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem";
+ compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 59 4>, <0 59 4>;
@@ -559,7 +564,7 @@
};
gem2: ethernet@ff0d0000 {
- compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem";
+ compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 61 4>, <0 61 4>;
@@ -574,7 +579,7 @@
};
gem3: ethernet@ff0e0000 {
- compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem";
+ compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 63 4>, <0 63 4>;
@@ -874,6 +879,7 @@
snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
snps,xhci-stream-quirk;
+ snps,resume-hs-terminations;
/* dma-coherent; */
};
};
@@ -905,6 +911,7 @@
snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
snps,xhci-stream-quirk;
+ snps,resume-hs-terminations;
/* dma-coherent; */
};
};
diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h b/arch/arm/mach-versal-net/include/mach/sys_proto.h
index 5bba903..a20cf02 100644
--- a/arch/arm/mach-versal-net/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h
@@ -8,9 +8,4 @@
void mem_map_fill(void);
-static inline int zynqmp_mmio_write(const u32 address, const u32 mask,
- const u32 value)
-{
- BUILD_BUG();
- return -EINVAL;
-}
+int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h
index 8e5712e..3f01508 100644
--- a/arch/arm/mach-versal/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal/include/mach/sys_proto.h
@@ -13,8 +13,4 @@ enum {
void tcm_init(u8 mode);
void mem_map_fill(void);
-static inline int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
-{
- BUILD_BUG();
- return -EINVAL;
-}
+int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index ce157a7..e38c9f6 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -4,19 +4,8 @@ menu "MicroBlaze architecture"
config SYS_ARCH
default "microblaze"
-config NEEDS_MANUAL_RELOC
- bool "Disable position-independent pre-relocation code"
- default y
- help
- U-Boot expects to be linked to a specific hard-coded address, and to
- be loaded to and run from that address. This option lifts that
- restriction, thus allowing the code to be loaded to and executed from
- almost any 4K aligned address. This logic relies on the relocation
- information that is embedded in the binary to support U-Boot
- relocating itself to the top-of-RAM later during execution.
-
config STATIC_RELA
- def_bool y if !NEEDS_MANUAL_RELOC
+ def_bool y
choice
prompt "Target select"
diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk
index 467c5ca..64c3f31 100644
--- a/arch/microblaze/config.mk
+++ b/arch/microblaze/config.mk
@@ -13,10 +13,6 @@ LDFLAGS_FINAL += --gc-sections
ifeq ($(CONFIG_SPL_BUILD),)
PLATFORM_CPPFLAGS += -fPIC
-endif
-
-ifeq ($(CONFIG_STATIC_RELA),y)
-PLATFORM_CPPFLAGS += -fPIC
LDFLAGS_u-boot += -pic
endif
diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile
index 1c586a7..b8c1dcb 100644
--- a/arch/microblaze/cpu/Makefile
+++ b/arch/microblaze/cpu/Makefile
@@ -5,7 +5,6 @@
extra-y = start.o
obj-y = irq.o
-obj-y += interrupts.o cache.o exception.o cpuinfo.o
-obj-$(CONFIG_STATIC_RELA) += relocate.o
+obj-y += interrupts.o cache.o exception.o cpuinfo.o relocate.o
obj-$(CONFIG_XILINX_MICROBLAZE0_PVR) += pvr.o
obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 7079d9e..c1e0fcd 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -10,16 +10,11 @@
#include <asm-offsets.h>
#include <config.h>
-#if defined(CONFIG_STATIC_RELA)
#define SYM_ADDR(reg, reg_add, symbol) \
mfs r20, rpc; \
addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8; \
lwi reg, r20, symbol@GOT; \
addk reg, reg reg_add;
-#else
-#define SYM_ADDR(reg, reg_add, symbol) \
- addi reg, reg_add, symbol
-#endif
.text
.global _start
@@ -35,7 +30,6 @@ _start:
addi r1, r0, CONFIG_SPL_STACK
#else
add r1, r0, r20
-#if defined(CONFIG_STATIC_RELA)
bri 1f
/* Force alignment for easier ASM code below */
@@ -68,7 +62,6 @@ uboot_sym_start:
brlid r15, mb_fix_rela
nop
#endif
-#endif
addi r1, r1, -4 /* Decrement SP to top of memory */
@@ -310,7 +303,6 @@ relocate_code:
brlid r15, __setup_exceptions
nop
-#if defined(CONFIG_STATIC_RELA)
/* reloc_offset is current location */
SYM_ADDR(r10, r0, _start)
@@ -331,27 +323,7 @@ relocate_code:
add r9, r9, r5
brlid r15, mb_fix_rela
nop
-
/* end of code which does relocation */
-#else
- /* Check if GOT exist */
- addik r21, r23, _got_start
- addik r22, r23, _got_end
- cmpu r12, r21, r22
- beqi r12, 2f /* No GOT table - jump over */
-
- /* Skip last 3 entries plus 1 because of loop boundary below */
- addik r22, r22, -0x10
-
- /* Relocate the GOT. */
-3: lw r12, r21, r0 /* Load entry */
- addk r12, r12, r23 /* Add reloc offset */
- sw r12, r21, r0 /* Save entry back */
-
- cmpu r12, r21, r22 /* Check if this cross boundary */
- bneid r12, 3b
- addik r21. r21, 4
-#endif
/* Flush caches to ensure consistency */
brlid r15, flush_cache_all
diff --git a/board/xilinx/zynqmp/Kconfig b/board/xilinx/zynqmp/Kconfig
index 7d1f739..ffa2f02 100644
--- a/board/xilinx/zynqmp/Kconfig
+++ b/board/xilinx/zynqmp/Kconfig
@@ -6,6 +6,7 @@ if ARCH_ZYNQMP
config CMD_ZYNQMP
bool "Enable ZynqMP specific commands"
+ depends on ZYNQMP_FIRMWARE
default y
help
Enable ZynqMP specific commands like "zynqmp secure"
diff --git a/cmd/smccc.c b/cmd/smccc.c
index 0539a42..fb80431 100644
--- a/cmd/smccc.c
+++ b/cmd/smccc.c
@@ -43,7 +43,7 @@ static int do_call(struct cmd_tbl *cmdtp, int flag, int argc,
else
arm_smccc_hvc(fid, a1, a2, a3, a4, a5, a6, a7, &res);
- printf("Res: %ld %ld %ld %ld\n", res.a0, res.a1, res.a2, res.a3);
+ printf("Res: 0x%lx 0x%lx 0x%lx 0x%lx\n", res.a0, res.a1, res.a2, res.a3);
return 0;
}
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
index 0992643..edd9463 100644
--- a/configs/xilinx_versal_net_virt_defconfig
+++ b/configs/xilinx_versal_net_virt_defconfig
@@ -48,6 +48,7 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
+CONFIG_CMD_SMC=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SQUASHFS=y
CONFIG_CMD_MTDPARTS=y
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index 169cece..7e38fd4 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -48,6 +48,7 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
+CONFIG_CMD_SMC=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SQUASHFS=y
CONFIG_CMD_MTDPARTS=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 4d30f5f..d29df93 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -92,6 +92,7 @@ CONFIG_CMD_TIME=y
CONFIG_CMD_GETTIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_SMC=y
CONFIG_CMD_TPM=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SQUASHFS=y
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 09aa97e..42280cb 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -185,7 +185,7 @@ config CLK_VERSACLOCK
config CLK_VERSAL
bool "Enable clock driver support for Versal"
depends on (ARCH_VERSAL || ARCH_VERSAL_NET)
- select ZYNQMP_FIRMWARE
+ imply ZYNQMP_FIRMWARE
help
This clock driver adds support for clock realted settings for
Versal platform.
@@ -219,7 +219,7 @@ config CLK_ZYNQ
config CLK_ZYNQMP
bool "Enable clock driver support for ZynqMP"
depends on ARCH_ZYNQMP
- select ZYNQMP_FIRMWARE
+ imply ZYNQMP_FIRMWARE
help
This clock driver adds support for clock realted settings for
ZynqMP platform.
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 61490d6..62cb77b 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -75,7 +75,7 @@ config FPGA_XILINX
config FPGA_ZYNQMPPL
bool "Enable Xilinx FPGA driver for ZynqMP"
- depends on FPGA_XILINX
+ depends on FPGA_XILINX && ZYNQMP_FIRMWARE
help
Enable FPGA driver for loading bitstream in BIT and BIN format
on Xilinx Zynq UltraScale+ (ZynqMP) device.
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index d1491da..7b5128f 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -332,10 +332,16 @@ static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
buf_lo = lower_32_bits((ulong)buf);
buf_hi = upper_32_bits((ulong)buf);
- ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
+ if ((u32)(uintptr_t)fpga_sec_info->userkey_addr)
+ ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
buf_hi,
- (u32)(uintptr_t)fpga_sec_info->userkey_addr,
- flag, ret_payload);
+ (u32)(uintptr_t)fpga_sec_info->userkey_addr,
+ flag, ret_payload);
+ else
+ ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
+ buf_hi, (u32)bsize,
+ flag, ret_payload);
+
if (ret)
puts("PL FPGA LOAD fail\n");
else
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 91e309d..9dc3106 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -14,6 +14,7 @@
#include "mmc_private.h"
#include <log.h>
#include <reset.h>
+#include <asm/arch/sys_proto.h>
#include <dm/device_compat.h>
#include <linux/err.h>
#include <linux/libfdt.h>
@@ -988,7 +989,7 @@ static const struct sdhci_ops arasan_ops = {
};
#endif
-#if defined(CONFIG_ARCH_ZYNQMP)
+#if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_ZYNQMP_FIRMWARE)
static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv,
struct udevice *dev)
{
@@ -1090,7 +1091,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
host = priv->host;
-#if defined(CONFIG_ARCH_ZYNQMP)
+#if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_ZYNQMP_FIRMWARE)
if (device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
ret = zynqmp_pm_is_function_supported(PM_IOCTL,
IOCTL_SET_SD_CONFIG);
diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c
index 4621bfb..99e2681 100644
--- a/drivers/mtd/nand/raw/arasan_nfc.c
+++ b/drivers/mtd/nand/raw/arasan_nfc.c
@@ -1230,12 +1230,16 @@ static int arasan_probe(struct udevice *dev)
struct nand_drv *info = &arasan->nand_ctrl;
struct nand_config *nand = &info->config;
struct mtd_info *mtd;
+ ofnode child;
int err = -1;
info->reg = (struct nand_regs *)dev_read_addr(dev);
mtd = nand_to_mtd(nand_chip);
nand_set_controller_data(nand_chip, &arasan->nand_ctrl);
+ ofnode_for_each_subnode(child, dev_ofnode(dev))
+ nand_set_flash_node(nand_chip, child);
+
#ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
#endif
@@ -1248,7 +1252,6 @@ static int arasan_probe(struct udevice *dev)
/* Buffer read/write routines */
nand_chip->read_buf = arasan_nand_read_buf;
nand_chip->write_buf = arasan_nand_write_buf;
- nand_chip->bbt_options = NAND_BBT_USE_FLASH;
writel(0x0, &info->reg->cmd_reg);
writel(0x0, &info->reg->pgm_reg);
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index cc49788..211b2c6 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -738,7 +738,7 @@ static int gem_zynqmp_set_dynamic_config(struct udevice *dev)
u32 pm_info[2];
int ret;
- if (IS_ENABLED(CONFIG_ARCH_ZYNQMP)) {
+ if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) && IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) {
if (!zynqmp_pm_is_function_supported(PM_IOCTL,
IOCTL_SET_GEM_CONFIG)) {
ret = ofnode_read_u32_array(dev_ofnode(dev),
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 4e9115d..9e6255a 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -112,10 +112,9 @@ struct xilinx_spi_priv {
static int xilinx_spi_probe(struct udevice *bus)
{
struct xilinx_spi_priv *priv = dev_get_priv(bus);
- struct xilinx_spi_regs *regs = priv->regs;
-
- priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
+ struct xilinx_spi_regs *regs;
+ regs = priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
writel(SPISSR_RESET_VALUE, &regs->srr);
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 335b458..c4aee27 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -183,6 +183,11 @@ struct zynqmp_qspi_priv {
const struct spi_mem_op *op;
};
+__weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
+{
+ return 0;
+}
+
static int zynqmp_qspi_of_to_plat(struct udevice *bus)
{
struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
diff --git a/include/spl.h b/include/spl.h
index 827bd25..bad12fb 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -884,5 +884,6 @@ void spl_perform_fixups(struct spl_image_info *spl_image);
*/
struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size);
+void board_boot_order(u32 *spl_boot_list);
void spl_save_restore_data(void);
#endif
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
index 2d2a2ed..fe8cd6b 100644
--- a/tools/relocate-rela.c
+++ b/tools/relocate-rela.c
@@ -45,6 +45,7 @@
#endif
static int ei_class;
+static int ei_data;
static uint64_t rela_start, rela_end, text_base, dyn_start;
@@ -61,6 +62,22 @@ static void debug(const char *fmt, ...)
}
}
+static uint16_t elf16_to_cpu(uint16_t data)
+{
+ if (ei_data == ELFDATA2LSB)
+ return le16_to_cpu(data);
+
+ return be16_to_cpu(data);
+}
+
+static uint32_t elf32_to_cpu(uint32_t data)
+{
+ if (ei_data == ELFDATA2LSB)
+ return le32_to_cpu(data);
+
+ return be32_to_cpu(data);
+}
+
static bool supported_rela(Elf64_Rela *rela)
{
uint64_t mask = 0xffffffffULL; /* would be different on 32-bit */
@@ -234,7 +251,7 @@ static int decode_elf32(FILE *felf, char **argv)
return 25;
}
- machine = le16_to_cpu(header.e_machine);
+ machine = elf16_to_cpu(header.e_machine);
debug("Machine %d\n", machine);
if (machine != EM_MICROBLAZE) {
@@ -242,10 +259,10 @@ static int decode_elf32(FILE *felf, char **argv)
return 30;
}
- text_base = le32_to_cpu(header.e_entry);
- section_header_base = le32_to_cpu(header.e_shoff);
- section_header_size = le16_to_cpu(header.e_shentsize) *
- le16_to_cpu(header.e_shnum);
+ text_base = elf32_to_cpu(header.e_entry);
+ section_header_base = elf32_to_cpu(header.e_shoff);
+ section_header_size = elf16_to_cpu(header.e_shentsize) *
+ elf16_to_cpu(header.e_shnum);
sh_table = malloc(section_header_size);
if (!sh_table) {
@@ -273,8 +290,8 @@ static int decode_elf32(FILE *felf, char **argv)
return 27;
}
- sh_index = le16_to_cpu(header.e_shstrndx);
- sh_size = le32_to_cpu(sh_table[sh_index].sh_size);
+ sh_index = elf16_to_cpu(header.e_shstrndx);
+ sh_size = elf32_to_cpu(sh_table[sh_index].sh_size);
debug("e_shstrndx %x, sh_size %lx\n", sh_index, sh_size);
sh_str = malloc(sh_size);
@@ -289,8 +306,8 @@ static int decode_elf32(FILE *felf, char **argv)
* Specifies the byte offset from the beginning of the file
* to the first byte in the section.
*/
- sh_offset = le32_to_cpu(sh_table[sh_index].sh_offset);
- sh_num = le16_to_cpu(header.e_shnum);
+ sh_offset = elf32_to_cpu(sh_table[sh_index].sh_offset);
+ sh_num = elf16_to_cpu(header.e_shnum);
ret = fseek(felf, sh_offset, SEEK_SET);
if (ret) {
@@ -312,13 +329,13 @@ static int decode_elf32(FILE *felf, char **argv)
}
for (i = 0; i < sh_num; i++) {
- char *sh_name = sh_str + le32_to_cpu(sh_table[i].sh_name);
+ char *sh_name = sh_str + elf32_to_cpu(sh_table[i].sh_name);
debug("%s\n", sh_name);
- sh_addr = le64_to_cpu(sh_table[i].sh_addr);
- sh_offset = le64_to_cpu(sh_table[i].sh_offset);
- sh_size = le64_to_cpu(sh_table[i].sh_size);
+ sh_addr = elf32_to_cpu(sh_table[i].sh_addr);
+ sh_offset = elf32_to_cpu(sh_table[i].sh_offset);
+ sh_size = elf32_to_cpu(sh_table[i].sh_size);
if (!strcmp(".rela.dyn", sh_name)) {
debug("Found section\t\".rela_dyn\"\n");
@@ -384,6 +401,9 @@ static int decode_elf(char **argv)
ei_class = e_ident[4];
debug("EI_CLASS(1=32bit, 2=64bit) %d\n", ei_class);
+ ei_data = e_ident[5];
+ debug("EI_DATA(1=little endian, 2=big endian) %d\n", ei_data);
+
if (ei_class == 2)
return decode_elf64(felf, argv);
@@ -520,9 +540,9 @@ static int rela_elf32(char **argv, FILE *f)
PRIu32 " r_addend:\t%" PRIx32 "\n",
rela.r_offset, rela.r_info, rela.r_addend);
- swrela.r_offset = le32_to_cpu(rela.r_offset);
- swrela.r_info = le32_to_cpu(rela.r_info);
- swrela.r_addend = le32_to_cpu(rela.r_addend);
+ swrela.r_offset = elf32_to_cpu(rela.r_offset);
+ swrela.r_info = elf32_to_cpu(rela.r_info);
+ swrela.r_addend = elf32_to_cpu(rela.r_addend);
debug("SWRela:\toffset:\t%" PRIx32 " r_info:\t%"
PRIu32 " r_addend:\t%" PRIx32 "\n",