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| author | Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> | 2021-05-03 09:59:17 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-06-09 13:34:01 +0200 |
| commit | 6ac4d4480663ca43f64a0ae1e49af5455bcff7aa (patch) | |
| tree | b1f1e82ce60882fa9db068f75ce25495b3b3ff66 | |
| parent | b8916306d1061b254d066ccaa4c797896c96a2c1 (diff) | |
| download | u-boot-6ac4d4480663ca43f64a0ae1e49af5455bcff7aa.zip u-boot-6ac4d4480663ca43f64a0ae1e49af5455bcff7aa.tar.gz u-boot-6ac4d4480663ca43f64a0ae1e49af5455bcff7aa.tar.bz2 | |
arm: imx: imx8mm: correct unrecognized fracpll frequency
Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ()
macro, which expands the value provided to the Hz range without taking into
account the precise Hz setting. This causes the frequency of 266 MHz not ot
be found in the imx8mm_fracpll_tbl, since it is entered there with a
precise Hz value. This in turn causes the boot hang in SPL, as proper DDR
fracpll frequency cannot be determined.
Correct the value in imx8mm_fracpll_tbl to match the one expanded by
MHZ(266) macro, rounding it down to MHz range only.
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Ye Li <ye.li@nxp.com>
Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m")
Reviewed-by: Fabio Estevam <festevam@gmail.com>
| -rw-r--r-- | arch/arm/mach-imx/imx8m/clock_imx8mm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 6f45d74..f8e4ec0 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -54,7 +54,7 @@ static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(600000000U, 300, 3, 2, 0), PLL_1443X_RATE(594000000U, 99, 1, 2, 0), PLL_1443X_RATE(400000000U, 300, 9, 1, 0), - PLL_1443X_RATE(266666667U, 400, 9, 2, 0), + PLL_1443X_RATE(266000000U, 400, 9, 2, 0), PLL_1443X_RATE(167000000U, 334, 3, 4, 0), PLL_1443X_RATE(100000000U, 300, 9, 3, 0), }; |