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| author | Ondrej Jirman <megi@xff.cz> | 2023-05-22 23:47:08 +0200 |
|---|---|---|
| committer | Anatolij Gustschin <agust@denx.de> | 2023-07-14 18:30:58 +0200 |
| commit | bd6375c5511c3b96ce91ea66084d27afe2bbc43b (patch) | |
| tree | 8859175c8d630c258469c84bcaeed03e8ad3e245 | |
| parent | 7c5f278a030359d2266b63345f9f9f2890a5f17f (diff) | |
| download | u-boot-bd6375c5511c3b96ce91ea66084d27afe2bbc43b.zip u-boot-bd6375c5511c3b96ce91ea66084d27afe2bbc43b.tar.gz u-boot-bd6375c5511c3b96ce91ea66084d27afe2bbc43b.tar.bz2 | |
video: rockchip: dw_mipi_dsi: Fix GRF access
Use proper register base and access method to access GRF registers.
GRF registers start at a completely different base, and need special
access method, that sets the change mask in the 16 MSBs.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
| -rw-r--r-- | drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c index fd885ac..117c3db 100644 --- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c +++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c @@ -18,6 +18,7 @@ #include <panel.h> #include <phy-mipi-dphy.h> #include <reset.h> +#include <syscon.h> #include <video_bridge.h> #include <dm/device_compat.h> #include <dm/lists.h> @@ -30,6 +31,9 @@ #include <dm/device-internal.h> #include <linux/bitops.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> + #define USEC_PER_SEC 1000000L /* @@ -197,6 +201,7 @@ struct dw_rockchip_dsi_priv { struct mipi_dsi_device device; void __iomem *base; struct udevice *panel; + void __iomem *grf; /* Optional external dphy */ struct phy phy; @@ -752,16 +757,13 @@ static int dw_mipi_dsi_rockchip_set_bl(struct udevice *dev, int percent) static void dw_mipi_dsi_rockchip_config(struct dw_rockchip_dsi_priv *dsi) { if (dsi->cdata->lanecfg1_grf_reg) - dsi_write(dsi, dsi->cdata->lanecfg1_grf_reg, - dsi->cdata->lanecfg1); + rk_setreg(dsi->grf + dsi->cdata->lanecfg1_grf_reg, dsi->cdata->lanecfg1); if (dsi->cdata->lanecfg2_grf_reg) - dsi_write(dsi, dsi->cdata->lanecfg2_grf_reg, - dsi->cdata->lanecfg2); + rk_setreg(dsi->grf + dsi->cdata->lanecfg2_grf_reg, dsi->cdata->lanecfg2); if (dsi->cdata->enable_grf_reg) - dsi_write(dsi, dsi->cdata->enable_grf_reg, - dsi->cdata->enable); + rk_setreg(dsi->grf + dsi->cdata->enable_grf_reg, dsi->cdata->enable); } static int dw_mipi_dsi_rockchip_bind(struct udevice *dev) @@ -794,6 +796,8 @@ static int dw_mipi_dsi_rockchip_probe(struct udevice *dev) return -EINVAL; } + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + i = 0; while (cdata[i].reg) { if (cdata[i].reg == (fdt_addr_t)priv->base) { |