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| author | Patrick Delaunay <patrick.delaunay@st.com> | 2020-04-10 16:02:02 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-05-01 11:34:01 -0400 |
| commit | f8dc7f2f18d324343737c72e27b6bd0ee8ff728e (patch) | |
| tree | ccab976640c82f0530290fcdbfde1807055be034 | |
| parent | e7882f65f02eca5a7d35871ba0355462bbf7362e (diff) | |
| download | u-boot-f8dc7f2f18d324343737c72e27b6bd0ee8ff728e.zip u-boot-f8dc7f2f18d324343737c72e27b6bd0ee8ff728e.tar.gz u-boot-f8dc7f2f18d324343737c72e27b6bd0ee8ff728e.tar.bz2 | |
configs: migrate CONFIG_SYS_ARM_CACHE_* in Kconfig
Move CONFIG_SYS_ARM_CACHE_WRITETHROUGH and
CONFIG_SYS_ARM_CACHE_WRITEALLOC into Kconfig done by moveconfig.py.
Kconfig uses a choice between the 3 values supported in U-Boot,
including the new configuration CONFIG_SYS_ARM_CACHE_WRITEBACK
(the default configuration).
The patch also avoids to select simultaneously 2 configurations.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| -rw-r--r-- | arch/arm/Kconfig | 28 | ||||
| -rw-r--r-- | arch/arm/include/asm/iproc-common/configs.h | 1 | ||||
| -rw-r--r-- | include/configs/grpeach.h | 1 | ||||
| -rw-r--r-- | include/configs/pxa-common.h | 2 | ||||
| -rw-r--r-- | scripts/config_whitelist.txt | 1 |
5 files changed, 28 insertions, 5 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8e67e1c..8b6c6a2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -340,6 +340,34 @@ config SYS_CACHELINE_SIZE default 64 if SYS_CACHE_SHIFT_6 default 32 if SYS_CACHE_SHIFT_5 +choice + prompt "Select the ARM data write cache policy" + default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \ + TARGET_BCMNSP || CPU_PXA || RZA1 + default SYS_ARM_CACHE_WRITEBACK + +config SYS_ARM_CACHE_WRITEBACK + bool "Write-back (WB)" + help + A write updates the cache only and marks the cache line as dirty. + External memory is updated only when the line is evicted or explicitly + cleaned. + +config SYS_ARM_CACHE_WRITETHROUGH + bool "Write-through (WT)" + help + A write updates both the cache and the external memory system. + This does not mark the cache line as dirty. + +config SYS_ARM_CACHE_WRITEALLOC + bool "Write allocation (WA)" + help + A cache line is allocated on a write miss. This means that executing a + store instruction on the processor might cause a burst read to occur. + There is a linefill to obtain the data for the cache line, before the + write is performed. +endchoice + config ARCH_CPU_INIT bool "Enable ARCH_CPU_INIT" help diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h index 96c4f54..4733c07 100644 --- a/arch/arm/include/asm/iproc-common/configs.h +++ b/arch/arm/include/asm/iproc-common/configs.h @@ -10,7 +10,6 @@ /* Architecture, CPU, chip, etc */ #define CONFIG_IPROC -#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH /* Memory Info */ #define CONFIG_SYS_SDRAM_BASE 0x61000000 diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index f1ea729..001e9d3 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -16,7 +16,6 @@ /* Miscellaneous */ #define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH #define CONFIG_CMDLINE_TAG /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h index e25800a..2632d48 100644 --- a/include/configs/pxa-common.h +++ b/include/configs/pxa-common.h @@ -8,8 +8,6 @@ #ifndef __CONFIG_PXA_COMMON_H__ #define __CONFIG_PXA_COMMON_H__ -#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH - /* * KGDB */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 12a6698..7a5da9d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1770,7 +1770,6 @@ CONFIG_SYS_AMASK4 CONFIG_SYS_AMASK5 CONFIG_SYS_AMASK6 CONFIG_SYS_AMASK7 -CONFIG_SYS_ARM_CACHE_WRITETHROUGH CONFIG_SYS_AT91_CPU_NAME CONFIG_SYS_AT91_MAIN_CLOCK CONFIG_SYS_AT91_PLLA |