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| author | Jagan Teki <jagan@amarulasolutions.com> | 2020-04-23 22:30:54 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2020-04-30 22:34:20 +0530 |
| commit | 622b913ea179645a37dc4fcb75cea6f54d3b505f (patch) | |
| tree | 17cce9082494287a275f9262670ccf7329fdc7ab | |
| parent | b7d6e104fbfd54b7ffe9e0a00200e98dd2904a65 (diff) | |
| download | u-boot-622b913ea179645a37dc4fcb75cea6f54d3b505f.zip u-boot-622b913ea179645a37dc4fcb75cea6f54d3b505f.tar.gz u-boot-622b913ea179645a37dc4fcb75cea6f54d3b505f.tar.bz2 | |
spi: sifive: Fix format register proto field
SiFive SPI controller has a proto bit field in frame format
register which would be used to configure the SPI I/O protocol
lines used on specific transfer.
Right now the driver is configuring this proto using slave->mode,
for all types of transctions. This makes the driver unable to
function since the proto needs to configure dynamically for
each and every transaction separately at runtime.
Now, the controller driver supports per transfer via spi-mem
exec_opo, so add the fmt_proto flag and fill the per transfer
buswidth so that the controller configures the proto bit at
runtime.
This patch fixes the SPI controller works with SPI NOR flash
on quad read with page program.
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
| -rw-r--r-- | drivers/spi/spi-sifive.c | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c index 5e612ed..0ea4930 100644 --- a/drivers/spi/spi-sifive.c +++ b/drivers/spi/spi-sifive.c @@ -86,6 +86,11 @@ #define SIFIVE_SPI_IP_TXWM BIT(0) #define SIFIVE_SPI_IP_RXWM BIT(1) +/* format protocol */ +#define SIFIVE_SPI_PROTO_QUAD 4 /* 4 lines I/O protocol transfer */ +#define SIFIVE_SPI_PROTO_DUAL 2 /* 2 lines I/O protocol transfer */ +#define SIFIVE_SPI_PROTO_SINGLE 1 /* 1 line I/O protocol transfer */ + struct sifive_spi { void *regs; /* base address of the registers */ u32 fifo_depth; @@ -93,6 +98,7 @@ struct sifive_spi { u32 cs_inactive; /* Level of the CS pins when inactive*/ u32 freq; u32 num_cs; + u8 fmt_proto; }; static void sifive_spi_prep_device(struct sifive_spi *spi, @@ -147,12 +153,17 @@ static void sifive_spi_prep_transfer(struct sifive_spi *spi, /* Number of wires ? */ cr &= ~SIFIVE_SPI_FMT_PROTO_MASK; - if ((slave_plat->mode & SPI_TX_QUAD) || (slave_plat->mode & SPI_RX_QUAD)) + switch (spi->fmt_proto) { + case SIFIVE_SPI_PROTO_QUAD: cr |= SIFIVE_SPI_FMT_PROTO_QUAD; - else if ((slave_plat->mode & SPI_TX_DUAL) || (slave_plat->mode & SPI_RX_DUAL)) + break; + case SIFIVE_SPI_PROTO_DUAL: cr |= SIFIVE_SPI_FMT_PROTO_DUAL; - else + break; + default: cr |= SIFIVE_SPI_FMT_PROTO_SINGLE; + break; + } /* SPI direction in/out ? */ cr &= ~SIFIVE_SPI_FMT_DIR; @@ -246,6 +257,7 @@ static int sifive_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) { struct udevice *dev = slave->dev; + struct sifive_spi *spi = dev_get_priv(dev->parent); unsigned long flags = SPI_XFER_BEGIN; u8 opcode = op->cmd.opcode; unsigned int pos = 0; @@ -257,6 +269,8 @@ static int sifive_spi_exec_op(struct spi_slave *slave, if (!op->addr.nbytes && !op->dummy.nbytes && !op->data.nbytes) flags |= SPI_XFER_END; + spi->fmt_proto = op->cmd.buswidth; + /* send the opcode */ ret = sifive_spi_xfer(dev, 8, (void *)&opcode, NULL, flags); if (ret < 0) { @@ -284,6 +298,8 @@ static int sifive_spi_exec_op(struct spi_slave *slave, if (!op->data.nbytes) flags |= SPI_XFER_END; + spi->fmt_proto = op->addr.buswidth; + ret = sifive_spi_xfer(dev, op_len * 8, op_buf, NULL, flags); if (ret < 0) { dev_err(dev, "failed to xfer addr + dummy\n"); @@ -298,6 +314,8 @@ static int sifive_spi_exec_op(struct spi_slave *slave, else tx_buf = op->data.buf.out; + spi->fmt_proto = op->data.buswidth; + ret = sifive_spi_xfer(dev, op->data.nbytes * 8, tx_buf, rx_buf, SPI_XFER_END); if (ret) { |