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author | Francesco Dolcini <francesco.dolcini@toradex.com> | 2024-02-13 17:00:03 +0100 |
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committer | Tom Rini <trini@konsulko.com> | 2024-02-13 15:38:49 -0500 |
commit | ea7d3eec1e6e6541db68bf48a1314410e06cd9de (patch) | |
tree | 4a641d6853dd8dd7fd7586b6be8d67c418717204 | |
parent | e761035b64235db8930eb15d2703dc3f43e99224 (diff) | |
download | u-boot-ea7d3eec1e6e6541db68bf48a1314410e06cd9de.zip u-boot-ea7d3eec1e6e6541db68bf48a1314410e06cd9de.tar.gz u-boot-ea7d3eec1e6e6541db68bf48a1314410e06cd9de.tar.bz2 |
Revert "board: verdin-am62: set cpu core voltage depending on speed grade"WIP/2024-02-13-assorted-updates
This reverts commit d2099587d661c6ca2309256c0e04c06e26c8d34c.
According to TI changing the VDD_CORE while the SoC is running is not
allowed, the voltage must be set before the AM62 device reset is
released, revert this change therefore.
The correct solution would be to program the PMIC during manufactoring
according to the speed grade of the SoC.
Link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1318338/am623-booting-from-mmc-failed-after-lowering-vdd_core-to-0-75v/5036508#5036508
Fixes: d2099587d661 ("board: verdin-am62: set cpu core voltage depending on speed grade")
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
-rw-r--r-- | board/toradex/verdin-am62/verdin-am62.c | 47 |
1 files changed, 0 insertions, 47 deletions
diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index 395eb36..e948fc1 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -14,13 +14,10 @@ #include <fdt_support.h> #include <init.h> #include <k3-ddrss.h> -#include <power/regulator.h> #include <spl.h> #include "../common/tdx-cfg-block.h" -#define VDD_CORE_REG "buck1" - DECLARE_GLOBAL_DATA_PTR; int board_init(void) @@ -53,37 +50,9 @@ int board_fit_config_name_match(const char *name) } #endif -static u32 get_vdd_core_nominal(void) -{ - int core_uvolt; - - switch (k3_get_speed_grade()) { - case 'G': - case 'K': - case 'S': - core_uvolt = 750000; - break; - case 'T': - default: - core_uvolt = 850000; - break; - } - return core_uvolt; -} - #if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { - int core_uvolt; - - core_uvolt = get_vdd_core_nominal(); - if (core_uvolt != 850000) { - do_fixup_by_path_u32(blob, "/bus@f0000/i2c@20000000/pmic@30/regulators/buck1", - "regulator-max-microvolt", core_uvolt, 0); - do_fixup_by_path_u32(blob, "/bus@f0000/i2c@20000000/pmic@30/regulators/buck1", - "regulator-min-microvolt", core_uvolt, 0); - } - return ft_common_board_setup(blob, bd); } #endif @@ -118,22 +87,6 @@ static void select_dt_from_module_version(void) int board_late_init(void) { - int ret; - int core_uvolt; - struct udevice *dev = NULL; - - core_uvolt = get_vdd_core_nominal(); - if (core_uvolt != 850000) { - /* Set CPU core voltage to 0.75V for slower speed grades */ - ret = regulator_get_by_devname(VDD_CORE_REG, &dev); - if (ret) - pr_err("VDD CORE Regulator get error: %d\n", ret); - - ret = regulator_set_value_force(dev, core_uvolt); - if (ret) - pr_err("VDD CORE Regulator value setting error: %d\n", ret); - } - select_dt_from_module_version(); return 0; |