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| author | Chanho Park <chanho61.park@samsung.com> | 2023-11-06 08:13:15 +0900 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-12-05 16:40:16 +0800 |
| commit | 8ef2d7926f6973707164f4bd8f76bb94e80f336b (patch) | |
| tree | d10ce24909400b868f8d593a22b97f8fc3769680 | |
| parent | 2f0282922b2c458eea7f85c500a948a587437b63 (diff) | |
| download | u-boot-8ef2d7926f6973707164f4bd8f76bb94e80f336b.zip u-boot-8ef2d7926f6973707164f4bd8f76bb94e80f336b.tar.gz u-boot-8ef2d7926f6973707164f4bd8f76bb94e80f336b.tar.bz2 | |
clk: starfive: jh7110: Add watchdog clocks
Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110
watchdog device.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| -rw-r--r-- | drivers/clk/starfive/clk-jh7110.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index a835541..a386948 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -434,6 +434,15 @@ static int jh7110_syscrg_init(struct udevice *dev) starfive_clk_gate(priv->reg, "i2c5_apb", "apb0", OFFSET(JH7110_SYSCLK_I2C5_APB))); + /* Watchdog clocks */ + clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_APB), + starfive_clk_gate(priv->reg, + "wdt_apb", "apb0", + OFFSET(JH7110_SYSCLK_WDT_APB))); + clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_CORE), + starfive_clk_gate(priv->reg, + "wdt_core", "oscillator", + OFFSET(JH7110_SYSCLK_WDT_CORE))); /* enable noc_bus_stg_axi clock */ if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk)) |