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| author | Marek Vasut <marex@denx.de> | 2023-12-16 06:42:28 +0100 |
|---|---|---|
| committer | Fabio Estevam <festevam@gmail.com> | 2023-12-16 07:45:02 -0300 |
| commit | d953ef8a2451aa74bc285b201439873735bd5045 (patch) | |
| tree | de5162ab6b7ac68ab47f192ee8a73333a9af1e6e | |
| parent | 3ac22891cfc0dc6d8eec25d2b0fbdd2eb8f3d3ed (diff) | |
| download | u-boot-d953ef8a2451aa74bc285b201439873735bd5045.zip u-boot-d953ef8a2451aa74bc285b201439873735bd5045.tar.gz u-boot-d953ef8a2451aa74bc285b201439873735bd5045.tar.bz2 | |
ARM: imx: Force DRAM regulators into FPWM mode on DH i.MX8MP DHCOM SoM
In case the Buck5 and Buck6 regulators which supply DRAM Vdd1 and Vdd2/Vddq
respectively operate in automatic PWM/PFM mode, the DRAM EDAC detects more
correctable errors than if the regulators operate in forced PWM only mode.
Force DRAM regulators to forced PWM mode only to stop tempting the DRAM.
Signed-off-by: Marek Vasut <marex@denx.de>
| -rw-r--r-- | board/dhelectronics/dh_imx8mp/spl.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c index 1b05da5..21b12a7 100644 --- a/board/dhelectronics/dh_imx8mp/spl.c +++ b/board/dhelectronics/dh_imx8mp/spl.c @@ -94,6 +94,11 @@ static int dh_imx8mp_board_power_init(void) /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c); + /* DRAM Vdd1 always FPWM */ + pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d); + /* DRAM Vdd2/Vddq always FPWM */ + pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d); + /* Set LDO4 and CONFIG2 to enable the I2C level translator. */ pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59); pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); |