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| author | Tom Rini <trini@konsulko.com> | 2024-04-15 07:38:18 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-04-15 07:38:18 -0600 |
| commit | d736d9f2126e014e92cd3efaa82d4b1520c6c25b (patch) | |
| tree | 31fbe5892b45f9c618a478b9732bf9f1d8894260 | |
| parent | b03b49046af5dfca599d2ce8f0aafed89b97aa91 (diff) | |
| parent | 27ed98d491521a637f2b4468ac021511294f897f (diff) | |
| download | u-boot-d736d9f2126e014e92cd3efaa82d4b1520c6c25b.zip u-boot-d736d9f2126e014e92cd3efaa82d4b1520c6c25b.tar.gz u-boot-d736d9f2126e014e92cd3efaa82d4b1520c6c25b.tar.bz2 | |
Merge tag 'u-boot-socfpga-next-20240415' of https://source.denx.de/u-boot/custodians/u-boot-socfpga
- Add option to reprogram FPGA every reboot, enable this as default in
chameleonv3 defconfig.
- Fixes: Rename CONFIG_SPL_SOCFPGA_SEC_REG to CONFIG_SPL_SOCFPGA_DT_REG,
so the driver can be built when CONFIG_SPL_SOCFPGA_DT_REG is set in
defconfig.
| -rw-r--r-- | arch/arm/mach-socfpga/Kconfig | 8 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/spl_a10.c | 8 | ||||
| -rw-r--r-- | configs/socfpga_chameleonv3_defconfig | 1 | ||||
| -rw-r--r-- | drivers/misc/Makefile | 2 |
4 files changed, 16 insertions, 3 deletions
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 1008232..6b6a162 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -90,6 +90,14 @@ config TARGET_SOCFPGA_ARRIA10 imply FPGA_SOCFPGA imply SPL_USE_TINY_PRINTF +config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM + bool "Always reprogram Arria 10 FPGA" + depends on TARGET_SOCFPGA_ARRIA10 + help + Arria 10 FPGA is only programmed during the cold boot. + This option forces the FPGA to be reprogrammed every reboot, + allowing to change the bitstream and apply it with warm reboot. + config TARGET_SOCFPGA_CYCLONE5 bool select TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 9edbbf4..3981d2d 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -122,7 +122,10 @@ void spl_board_init(void) arch_early_init_r(); /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */ - if (is_fpgamgr_user_mode()) { + if ((IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) && + is_regular_boot_valid()) || + (!IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) && + is_fpgamgr_user_mode())) { ret = config_pins(gd->fdt_blob, "shared"); if (ret) return; @@ -130,7 +133,8 @@ void spl_board_init(void) ret = config_pins(gd->fdt_blob, "fpga"); if (ret) return; - } else if (!is_fpgamgr_early_user_mode()) { + } else if (IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) || + !is_fpgamgr_early_user_mode()) { /* Program IOSSM(early IO release) or full FPGA */ fpgamgr_program(buf, FPGA_BUFSIZ, 0); diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig index 6ea61ca..7506aa8 100644 --- a/configs/socfpga_chameleonv3_defconfig +++ b/configs/socfpga_chameleonv3_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2" CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y +CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM=y CONFIG_SPL_FS_FAT=y CONFIG_FIT=y CONFIG_SPL_FIT=y diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 9e82990..e53d52c 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -91,4 +91,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o obj-$(CONFIG_ESM_K3) += k3_esm.o obj-$(CONFIG_ESM_PMIC) += esm_pmic.o obj-$(CONFIG_SL28CPLD) += sl28cpld.o -obj-$(CONFIG_SPL_SOCFPGA_SEC_REG) += socfpga_dtreg.o +obj-$(CONFIG_SPL_SOCFPGA_DT_REG) += socfpga_dtreg.o |