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| author | Tim Harvey <tharvey@gateworks.com> | 2023-11-27 11:37:23 -0800 |
|---|---|---|
| committer | Fabio Estevam <festevam@denx.de> | 2023-12-20 15:00:47 -0300 |
| commit | c0689191f1205289ec5f422a9e707fa466907f69 (patch) | |
| tree | 3189d97bef43695db5d9d13f5265f6679e1f8e86 | |
| parent | b1c40d069206dac25a2124b613229eab54594abb (diff) | |
| download | u-boot-c0689191f1205289ec5f422a9e707fa466907f69.zip u-boot-c0689191f1205289ec5f422a9e707fa466907f69.tar.gz u-boot-c0689191f1205289ec5f422a9e707fa466907f69.tar.bz2 | |
arm: dts: imx8mp-venice-gw72xx: add TPM device
Add the TPM device found on the GW72xx revision F PCB.
This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
| -rw-r--r-- | arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi | 9 | ||||
| -rw-r--r-- | arch/arm/dts/imx8mp-venice-gw72xx.dtsi | 9 |
2 files changed, 17 insertions, 1 deletions
diff --git a/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi index 7f2609a..525316d 100644 --- a/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi @@ -4,6 +4,15 @@ */ #include "imx8mp-venice-gw702x-u-boot.dtsi" +&gpio1 { + tpm_rst { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; + }; +}; + &gpio4 { dio_1 { gpio-hog; diff --git a/arch/arm/dts/imx8mp-venice-gw72xx.dtsi b/arch/arm/dts/imx8mp-venice-gw72xx.dtsi index e05fdec..4e72612 100644 --- a/arch/arm/dts/imx8mp-venice-gw72xx.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw72xx.dtsi @@ -83,8 +83,14 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio4 { @@ -286,6 +292,7 @@ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 >; }; |