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| author | Tim Harvey <tharvey@gateworks.com> | 2023-11-27 11:36:58 -0800 |
|---|---|---|
| committer | Fabio Estevam <festevam@denx.de> | 2023-12-20 15:00:47 -0300 |
| commit | b1c40d069206dac25a2124b613229eab54594abb (patch) | |
| tree | d362afd38fe59427fda2abb3525d33f00f476e8a | |
| parent | 2264bfba19349a5f07b587c857f45123d8f4c286 (diff) | |
| download | u-boot-b1c40d069206dac25a2124b613229eab54594abb.zip u-boot-b1c40d069206dac25a2124b613229eab54594abb.tar.gz u-boot-b1c40d069206dac25a2124b613229eab54594abb.tar.bz2 | |
arm: dts: imx8mm-venice-gw72xx: add TPM device
Add the TPM device found on the GW72xx revision F PCB.
This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
| -rw-r--r-- | arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi | 7 | ||||
| -rw-r--r-- | arch/arm/dts/imx8mm-venice-gw72xx.dtsi | 10 |
2 files changed, 16 insertions, 1 deletions
diff --git a/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi index 92e44d4..31f9d47 100644 --- a/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi @@ -39,6 +39,13 @@ gpios = <9 GPIO_ACTIVE_HIGH>; line-name = "dio1"; }; + + tpm_rst { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; + }; }; &gpio4 { diff --git a/arch/arm/dts/imx8mm-venice-gw72xx.dtsi b/arch/arm/dts/imx8mm-venice-gw72xx.dtsi index 41d0de6..97ed34a 100644 --- a/arch/arm/dts/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw72xx.dtsi @@ -84,8 +84,15 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio1 { @@ -314,6 +321,7 @@ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 >; }; |