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authorTom Rini <trini@konsulko.com>2021-01-25 09:01:28 -0500
committerTom Rini <trini@konsulko.com>2021-01-25 09:01:28 -0500
commitaee5bcce35009c50555d9917e2ca4b9422210fbb (patch)
tree7f17251dbb1eeba1255dec492f89650c3b1d5895
parent69d29fe1c0aeb33f42633a75555d30b7921c02aa (diff)
parent786f35b619ddbfb88e4532d11a56413f5dab473f (diff)
downloadu-boot-aee5bcce35009c50555d9917e2ca4b9422210fbb.zip
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Merge tag 'u-boot-atmel-2021.04-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
Second set of u-boot-atmel features for 2021.04 cycle This feature set includes macb updates for all interfaces and new sama7g5 variant support; micrel ksz9031 DLL support; a new board from Giant based on Adafruit feather form factor which contains a SAMA5D27 SoC; several fixes regarding the NAND flash PMECC block; and pincontrol drive strength support for pio4 controller.
-rw-r--r--arch/arm/dts/Makefile3
-rw-r--r--arch/arm/dts/at91-sama5d27_giantboard.dts128
-rw-r--r--arch/arm/mach-at91/include/mach/atmel_pio4.h1
-rw-r--r--arch/arm/mach-at91/include/mach/sam9x60.h4
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d3.h4
-rw-r--r--arch/arm/mach-at91/spl_atmel.c7
-rw-r--r--board/atmel/sama5d27_som1_ek/MAINTAINERS6
-rw-r--r--configs/at91sam9n12ek_mmc_defconfig1
-rw-r--r--configs/at91sam9n12ek_spiflash_defconfig1
-rw-r--r--configs/at91sam9x5ek_mmc_defconfig1
-rw-r--r--configs/at91sam9x5ek_spiflash_defconfig1
-rw-r--r--configs/sama5d27_giantboard_defconfig97
-rw-r--r--configs/sama5d36ek_cmp_mmc_defconfig2
-rw-r--r--configs/sama5d36ek_cmp_nandflash_defconfig1
-rw-r--r--configs/sama5d36ek_cmp_spiflash_defconfig2
-rw-r--r--configs/sama5d3_xplained_mmc_defconfig2
-rw-r--r--configs/sama5d3xek_mmc_defconfig2
-rw-r--r--configs/sama5d3xek_spiflash_defconfig2
-rw-r--r--configs/sama5d4_xplained_spiflash_defconfig2
-rw-r--r--configs/sama5d4ek_mmc_defconfig2
-rw-r--r--configs/sama5d4ek_spiflash_defconfig2
-rw-r--r--doc/device-tree-bindings/pinctrl/atmel,at91-pio4-pinctrl.txt2
-rw-r--r--drivers/net/macb.c100
-rw-r--r--drivers/net/phy/micrel_ksz90x1.c65
-rw-r--r--drivers/pinctrl/pinctrl-at91-pio4.c14
-rw-r--r--include/configs/sama5d27_som1_ek.h7
-rw-r--r--include/dt-bindings/pinctrl/at91.h7
27 files changed, 436 insertions, 30 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ebdda1a..0217c62 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -906,7 +906,8 @@ dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \
- at91-sama5d27_som1_ek.dtb
+ at91-sama5d27_som1_ek.dtb \
+ at91-sama5d27_giantboard.dtb
dtb-$(CONFIG_TARGET_SAMA5D27_WLSOM1_EK) += \
at91-sama5d27_wlsom1_ek.dtb
diff --git a/arch/arm/dts/at91-sama5d27_giantboard.dts b/arch/arm/dts/at91-sama5d27_giantboard.dts
new file mode 100644
index 0000000..e81ca60
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d27_giantboard.dts
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * at91-sama5d27_giantboard.dts - Device Tree file for Giant Board
+ *
+ * Copyright (C) 2020 Greg Gallagher <greg@embeddedgreg.com>
+ *
+ * Derived from at91-sama5d27_som1_ek.dts
+ *
+ * Copyright (C) 2017 Microchip Corporation
+ * Wenyou Yang <wenyou.yang@microchip.com>
+ */
+/dts-v1/;
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+
+/ {
+ model = "Giant Board";
+ compatible = "atmel,sama5d27-giantboard", "atmel,sama5d2", "atmel,sama5";
+
+ memory {
+ reg = <0x20000000 0x8000000>;
+ };
+
+ chosen {
+ u-boot,dm-pre-reloc;
+ stdout-path = &uart1;
+ };
+
+ ahb {
+ sdmmc1: sdio-host@b0000000 {
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ apb {
+
+ uart1: serial@f8020000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ i2c0: i2c@f8028000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ status = "okay";
+ };
+
+ i2c1: i2c@fc028000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ status = "okay";
+
+ pmic@5b {
+ compatible = "active-semi,act8945a";
+ reg = <0x5b>;
+ active-semi,vsel-low;
+ status = "okay";
+ };
+ };
+
+ pit: timer@f8048030 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ sfr: sfr@f8030000 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ pioA: gpio@fc038000 {
+ pinctrl {
+
+ pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default {
+ pinmux = <PIN_PA28__SDMMC1_CMD>,
+ <PIN_PA18__SDMMC1_DAT0>,
+ <PIN_PA19__SDMMC1_DAT1>,
+ <PIN_PA20__SDMMC1_DAT2>,
+ <PIN_PA21__SDMMC1_DAT3>;
+ bias-pull-up;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default {
+ pinmux = <PIN_PA22__SDMMC1_CK>,
+ <PIN_PA30__SDMMC1_CD>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_uart1_default: uart1_default {
+ pinmux = <PIN_PD2__URXD1>,
+ <PIN_PD3__UTXD1>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_i2c0_default: i2c0_default {
+ pinmux = <PIN_PD21__TWD0>,
+ <PIN_PD22__TWCK0>;
+ bias-disable;
+ };
+
+ pinctrl_i2c1_default: i2c1_default {
+ pinmux = <PIN_PD4__TWD1>,
+ <PIN_PD5__TWCK1>;
+ bias-disable;
+ };
+
+ pinctrl_usb_default: usb_default {
+ pinmux = <PIN_PB10__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_usba_vbus: usba_vbus {
+ pinmux = <PIN_PA31__GPIO>;
+ bias-disable;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-at91/include/mach/atmel_pio4.h b/arch/arm/mach-at91/include/mach/atmel_pio4.h
index f348b05..35ac7b2 100644
--- a/arch/arm/mach-at91/include/mach/atmel_pio4.h
+++ b/arch/arm/mach-at91/include/mach/atmel_pio4.h
@@ -52,6 +52,7 @@ struct atmel_pio4_port {
#define ATMEL_PIO_DRVSTR_LO (1 << 16)
#define ATMEL_PIO_DRVSTR_ME (2 << 16)
#define ATMEL_PIO_DRVSTR_HI (3 << 16)
+#define ATMEL_PIO_DRVSTR_OFFSET 16
#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
#define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
#define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
diff --git a/arch/arm/mach-at91/include/mach/sam9x60.h b/arch/arm/mach-at91/include/mach/sam9x60.h
index b7f4322..c08d19c 100644
--- a/arch/arm/mach-at91/include/mach/sam9x60.h
+++ b/arch/arm/mach-at91/include/mach/sam9x60.h
@@ -154,8 +154,8 @@
/*
* PMECC table in ROM
*/
-#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000
-#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000
+#define ATMEL_PMECC_INDEX_OFFSET_512 0x0000
+#define ATMEL_PMECC_INDEX_OFFSET_1024 0x8000
/*
* SAM9X60 specific prototypes
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index 83f18a8..f4f0567 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -190,8 +190,8 @@
/*
* PMECC table in ROM
*/
-#define ATMEL_PMECC_INDEX_OFFSET_512 0x10000
-#define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000
+#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000
+#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000
/*
* SAMA5D3 specific prototypes
diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c
index 23588e7..217ed12 100644
--- a/arch/arm/mach-at91/spl_atmel.c
+++ b/arch/arm/mach-at91/spl_atmel.c
@@ -103,6 +103,13 @@ void board_init_f(ulong dummy)
{
int ret;
+ if (IS_ENABLED(CONFIG_OF_CONTROL)) {
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+ }
switch_to_main_crystal_osc();
#ifdef CONFIG_SAMA5D2
diff --git a/board/atmel/sama5d27_som1_ek/MAINTAINERS b/board/atmel/sama5d27_som1_ek/MAINTAINERS
index f2d2f49..ba2f31e 100644
--- a/board/atmel/sama5d27_som1_ek/MAINTAINERS
+++ b/board/atmel/sama5d27_som1_ek/MAINTAINERS
@@ -6,3 +6,9 @@ F: include/configs/sama5d27_som1_ek.h
F: configs/sama5d27_som1_ek_mmc_defconfig
F: configs/sama5d27_som1_ek_mmc1_defconfig
F: configs/sama5d27_som1_ek_qspiflash_defconfig
+
+SAMA5D27 GIANT BOARD
+M: Greg Gallagher <greg@embeddedgreg.com>
+S: Maintained
+F: configs/sama5d27_giantboard_defconfig
+F: arch/arm/dts/at91-sama5d27_giantboard.dts
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index 74a28a3..ad6ab85 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -42,6 +42,7 @@ CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index 6a340f5..c6ac366 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -44,6 +44,7 @@ CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index d48d2d7..9acdbb8 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -45,6 +45,7 @@ CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index eb935d6..25de37f 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -47,6 +47,7 @@ CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/sama5d27_giantboard_defconfig b/configs/sama5d27_giantboard_defconfig
new file mode 100644
index 0000000..4e55a62
--- /dev/null
+++ b/configs/sama5d27_giantboard_defconfig
@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_AT91=y
+CONFIG_CMDLINE=y
+CONFIG_SYS_TEXT_BASE=0x23f00000
+CONFIG_TARGET_SAMA5D27_SOM1_EK=y
+CONFIG_SAMA5D27_GIANTBOARD=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xf8020000
+CONFIG_DEBUG_UART_CLOCK=82000000
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SYS_BOARD="giantboard"
+CONFIG_SYS_BOARD_NAME="giantboard"
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_MISC_INIT_R=y
+CONFIG_BOARD_EARLY_INIT_F=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIBFDT=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_giantboard"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+# CONFIG_NET is not set
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig
index 22c1134..7b6cbb1 100644
--- a/configs/sama5d36ek_cmp_mmc_defconfig
+++ b/configs/sama5d36ek_cmp_mmc_defconfig
@@ -46,6 +46,8 @@ CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
+CONFIG_PMECC_CAP=4
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig
index ed78f4e..a3b2fac 100644
--- a/configs/sama5d36ek_cmp_nandflash_defconfig
+++ b/configs/sama5d36ek_cmp_nandflash_defconfig
@@ -46,6 +46,7 @@ CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=4
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig
index 8fc183f..4d604a2 100644
--- a/configs/sama5d36ek_cmp_spiflash_defconfig
+++ b/configs/sama5d36ek_cmp_spiflash_defconfig
@@ -48,6 +48,8 @@ CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
+CONFIG_PMECC_CAP=4
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index c839b4f..e35a575 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -65,6 +65,8 @@ CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
+CONFIG_PMECC_CAP=4
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 70c6e30..5c0c5cb 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -70,6 +70,8 @@ CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
+CONFIG_PMECC_CAP=4
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index 5a06518..109ac9f 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -71,6 +71,8 @@ CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
+CONFIG_PMECC_CAP=4
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index d9ad9cc..a29bbae 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -67,6 +67,8 @@ CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
+CONFIG_PMECC_CAP=8
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index d91a6f6..3aa1fd4 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -61,6 +61,8 @@ CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
+CONFIG_PMECC_CAP=8
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index 5ebd1cc..e62619f 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -64,6 +64,8 @@ CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
+CONFIG_PMECC_CAP=8
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/doc/device-tree-bindings/pinctrl/atmel,at91-pio4-pinctrl.txt b/doc/device-tree-bindings/pinctrl/atmel,at91-pio4-pinctrl.txt
index a376c6f..9252dc1 100644
--- a/doc/device-tree-bindings/pinctrl/atmel,at91-pio4-pinctrl.txt
+++ b/doc/device-tree-bindings/pinctrl/atmel,at91-pio4-pinctrl.txt
@@ -28,6 +28,8 @@ Optional properties:
- GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable,
bias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable,
input-debounce.
+- atmel,drive-strength: 0 or 1 for low drive, 2 for medium drive and 3 for
+high drive. The default value is low drive.
Example:
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 2225b33..6e26467 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -144,11 +144,20 @@ struct macb_device {
#endif
};
+struct macb_usrio_cfg {
+ unsigned int mii;
+ unsigned int rmii;
+ unsigned int rgmii;
+ unsigned int clken;
+};
+
struct macb_config {
unsigned int dma_burst_length;
unsigned int hw_dma_cap;
+ unsigned int caps;
int (*clk_init)(struct udevice *dev, ulong rate);
+ const struct macb_usrio_cfg *usrio;
};
#ifndef CONFIG_DM_ETH
@@ -586,6 +595,23 @@ static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
return 0;
}
+static int macb_sama7g5_clk_init(struct udevice *dev, ulong rate)
+{
+ struct clk clk;
+ int ret;
+
+ ret = clk_get_by_name(dev, "tx_clk", &clk);
+ if (ret)
+ return ret;
+
+ /*
+ * This is for using GCK. Clock rate is addressed via assigned-clock
+ * property, so only clock enable is needed here. The switching to
+ * proper clock rate depending on link speed is managed by IP logic.
+ */
+ return clk_enable(&clk);
+}
+
int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
{
#ifdef CONFIG_CLK
@@ -622,7 +648,7 @@ int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
if (tx_clk.dev) {
ret = clk_set_rate(&tx_clk, rate);
- if (ret)
+ if (ret < 0)
return ret;
}
#endif
@@ -850,6 +876,7 @@ static int _macb_init(struct macb_device *macb, const char *name)
{
#ifdef CONFIG_DM_ETH
struct macb_device *macb = dev_get_priv(dev);
+ unsigned int val = 0;
#endif
unsigned long paddr;
int ret;
@@ -920,11 +947,20 @@ static int _macb_init(struct macb_device *macb, const char *name)
* to select interface between RMII and MII.
*/
#ifdef CONFIG_DM_ETH
- if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) ||
- (macb->phy_interface == PHY_INTERFACE_MODE_RGMII))
- gem_writel(macb, USRIO, GEM_BIT(RGMII));
- else
- gem_writel(macb, USRIO, 0);
+ if (macb->phy_interface == PHY_INTERFACE_MODE_RGMII ||
+ macb->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ macb->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+ macb->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ val = macb->config->usrio->rgmii;
+ else if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
+ val = macb->config->usrio->rmii;
+ else if (macb->phy_interface == PHY_INTERFACE_MODE_MII)
+ val = macb->config->usrio->mii;
+
+ if (macb->config->caps & MACB_CAPS_USRIO_HAS_CLKEN)
+ val |= macb->config->usrio->clken;
+
+ gem_writel(macb, USRIO, val);
if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
unsigned int ncfgr = macb_readl(macb, NCFGR);
@@ -934,7 +970,7 @@ static int _macb_init(struct macb_device *macb, const char *name)
}
#else
#if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
- gem_writel(macb, USRIO, GEM_BIT(RGMII));
+ gem_writel(macb, USRIO, macb->config->usrio->rgmii);
#else
gem_writel(macb, USRIO, 0);
#endif
@@ -945,28 +981,30 @@ static int _macb_init(struct macb_device *macb, const char *name)
#ifdef CONFIG_AT91FAMILY
if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
macb_writel(macb, USRIO,
- MACB_BIT(RMII) | MACB_BIT(CLKEN));
+ macb->config->usrio->rmii |
+ macb->config->usrio->clken);
} else {
- macb_writel(macb, USRIO, MACB_BIT(CLKEN));
+ macb_writel(macb, USRIO, macb->config->usrio->clken);
}
#else
if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
macb_writel(macb, USRIO, 0);
else
- macb_writel(macb, USRIO, MACB_BIT(MII));
+ macb_writel(macb, USRIO, macb->config->usrio->mii);
#endif
#else
#ifdef CONFIG_RMII
#ifdef CONFIG_AT91FAMILY
- macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
+ macb_writel(macb, USRIO, macb->config->usrio->rmii |
+ macb->config->usrio->clken);
#else
macb_writel(macb, USRIO, 0);
#endif
#else
#ifdef CONFIG_AT91FAMILY
- macb_writel(macb, USRIO, MACB_BIT(CLKEN));
+ macb_writel(macb, USRIO, macb->config->usrio->clken);
#else
- macb_writel(macb, USRIO, MACB_BIT(MII));
+ macb_writel(macb, USRIO, macb->config->usrio->mii);
#endif
#endif /* CONFIG_RMII */
#endif
@@ -1307,10 +1345,18 @@ static int macb_enable_clk(struct udevice *dev)
}
#endif
+static const struct macb_usrio_cfg macb_default_usrio = {
+ .mii = MACB_BIT(MII),
+ .rmii = MACB_BIT(RMII),
+ .rgmii = GEM_BIT(RGMII),
+ .clken = MACB_BIT(CLKEN),
+};
+
static const struct macb_config default_gem_config = {
.dma_burst_length = 16,
.hw_dma_cap = HW_DMA_CAP_32B,
.clk_init = NULL,
+ .usrio = &macb_default_usrio,
};
static int macb_eth_probe(struct udevice *dev)
@@ -1404,28 +1450,56 @@ static int macb_eth_of_to_plat(struct udevice *dev)
return macb_late_eth_of_to_plat(dev);
}
+static const struct macb_usrio_cfg sama7g5_usrio = {
+ .mii = 0,
+ .rmii = 1,
+ .rgmii = 2,
+ .clken = BIT(2),
+};
+
static const struct macb_config microchip_config = {
.dma_burst_length = 16,
.hw_dma_cap = HW_DMA_CAP_64B,
.clk_init = NULL,
+ .usrio = &macb_default_usrio,
};
static const struct macb_config sama5d4_config = {
.dma_burst_length = 4,
.hw_dma_cap = HW_DMA_CAP_32B,
.clk_init = NULL,
+ .usrio = &macb_default_usrio,
};
static const struct macb_config sifive_config = {
.dma_burst_length = 16,
.hw_dma_cap = HW_DMA_CAP_32B,
.clk_init = macb_sifive_clk_init,
+ .usrio = &macb_default_usrio,
+};
+
+static const struct macb_config sama7g5_gmac_config = {
+ .dma_burst_length = 16,
+ .hw_dma_cap = HW_DMA_CAP_32B,
+ .clk_init = macb_sama7g5_clk_init,
+ .usrio = &sama7g5_usrio,
+};
+
+static const struct macb_config sama7g5_emac_config = {
+ .caps = MACB_CAPS_USRIO_HAS_CLKEN,
+ .dma_burst_length = 16,
+ .hw_dma_cap = HW_DMA_CAP_32B,
+ .usrio = &sama7g5_usrio,
};
static const struct udevice_id macb_eth_ids[] = {
{ .compatible = "cdns,macb" },
{ .compatible = "cdns,at91sam9260-macb" },
{ .compatible = "cdns,sam9x60-macb" },
+ { .compatible = "cdns,sama7g5-gem",
+ .data = (ulong)&sama7g5_gmac_config },
+ { .compatible = "cdns,sama7g5-emac",
+ .data = (ulong)&sama7g5_emac_config },
{ .compatible = "atmel,sama5d2-gem" },
{ .compatible = "atmel,sama5d3-gem" },
{ .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },
diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c
index f0032e8..77fad4a 100644
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -396,9 +396,70 @@ static struct phy_driver ksz9031_driver = {
/*
* KSZ9131
*/
+
+#define KSZ9131RN_MMD_COMMON_CTRL_REG 2
+#define KSZ9131RN_RXC_DLL_CTRL 76
+#define KSZ9131RN_TXC_DLL_CTRL 77
+#define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12)
+#define KSZ9131RN_DLL_ENABLE_DELAY 0
+#define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
+
+static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
+{
+ struct phy_driver *drv = phydev->drv;
+ u16 rxcdll_val, txcdll_val, val;
+ int ret;
+
+ switch (phydev->interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
+ txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
+ txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
+ txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
+ txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
+ break;
+ default:
+ return 0;
+ }
+
+ val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
+ KSZ9131RN_RXC_DLL_CTRL);
+ val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
+ val |= rxcdll_val;
+ ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
+ KSZ9131RN_RXC_DLL_CTRL, val);
+ if (ret)
+ return ret;
+
+ val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
+ KSZ9131RN_TXC_DLL_CTRL);
+
+ val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
+ val |= txcdll_val;
+ ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
+ KSZ9131RN_TXC_DLL_CTRL, val);
+
+ return ret;
+}
+
static int ksz9131_config(struct phy_device *phydev)
{
- /* TBD: Implement Skew values for dts */
+ int ret;
+
+ if (phy_interface_is_rgmii(phydev)) {
+ ret = ksz9131_config_rgmii_delay(phydev);
+ if (ret)
+ return ret;
+ }
/* add an option to disable the gigabit feature of this PHY */
if (env_get("disable_giga")) {
@@ -430,7 +491,7 @@ static int ksz9131_config(struct phy_device *phydev)
}
static struct phy_driver ksz9131_driver = {
- .name = "Micrel ksz9031",
+ .name = "Micrel ksz9131",
.uid = PHY_ID_KSZ9131,
.mask = MII_KSZ9x31_SILICON_REV_MASK,
.features = PHY_GBIT_FEATURES,
diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
index 1aba8a9..3a5143a 100644
--- a/drivers/pinctrl/pinctrl-at91-pio4.c
+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -34,17 +34,19 @@ static const struct pinconf_param conf_params[] = {
{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
{ "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
+ { "atmel,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
};
-static u32 atmel_pinctrl_get_pinconf(const void *blob, int node)
+static u32 atmel_pinctrl_get_pinconf(struct udevice *config)
{
const struct pinconf_param *params;
u32 param, arg, conf = 0;
u32 i;
+ u32 val;
for (i = 0; i < ARRAY_SIZE(conf_params); i++) {
params = &conf_params[i];
- if (!fdt_get_property(blob, node, params->property, NULL))
+ if (!dev_read_prop(config, params->property, NULL))
continue;
param = params->param;
@@ -82,6 +84,12 @@ static u32 atmel_pinctrl_get_pinconf(const void *blob, int node)
conf |= ATMEL_PIO_IFSCEN_MASK;
}
break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ dev_read_u32(config, params->property, &val);
+ conf &= (~ATMEL_PIO_DRVSTR_MASK);
+ conf |= (val << ATMEL_PIO_DRVSTR_OFFSET)
+ & ATMEL_PIO_DRVSTR_MASK;
+ break;
default:
printf("%s: Unsupported configuration parameter: %u\n",
__func__, param);
@@ -115,7 +123,7 @@ static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config)
u32 i, conf;
int count;
- conf = atmel_pinctrl_get_pinconf(blob, node);
+ conf = atmel_pinctrl_get_pinconf(config);
count = fdtdec_get_int_array_count(blob, node, "pinmux",
cells, ARRAY_SIZE(cells));
diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h
index 3358149..8942d15 100644
--- a/include/configs/sama5d27_som1_ek.h
+++ b/include/configs/sama5d27_som1_ek.h
@@ -27,14 +27,11 @@
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-/* NAND flash */
-
-/* SPI flash */
-
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_SD_BOOT
/* bootstrap + u-boot + env in sd card */
-#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 at91-sama5d27_som1_ek.dtb; " \
+#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 " \
+ CONFIG_DEFAULT_DEVICE_TREE ".dtb; " \
"fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \
"bootz 0x22000000 - 0x21000000"
#endif
diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
index 616f5ce..3831f91 100644
--- a/include/dt-bindings/pinctrl/at91.h
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This header provides constants for most at91 pinctrl bindings.
*
* Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * GPLv2 only
*/
#ifndef __DT_BINDINGS_AT91_PINCTRL_H__
@@ -43,4 +42,8 @@
#define AT91_PERIPH_C 3
#define AT91_PERIPH_D 4
+#define ATMEL_PIO_DRVSTR_LO 1
+#define ATMEL_PIO_DRVSTR_ME 2
+#define ATMEL_PIO_DRVSTR_HI 3
+
#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */