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| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2023-11-16 09:35:26 +0200 |
|---|---|---|
| committer | Svyatoslav Ryhel <clamor95@gmail.com> | 2023-12-19 21:24:11 +0200 |
| commit | 944ac34075fe1dd1a16f0dee0d7279c8d49a537a (patch) | |
| tree | 6c488a4a1c1c446416334e3786c6857c9e4a239c | |
| parent | e63ab85dba80f15f6740821a4669569564537f94 (diff) | |
| download | u-boot-944ac34075fe1dd1a16f0dee0d7279c8d49a537a.zip u-boot-944ac34075fe1dd1a16f0dee0d7279c8d49a537a.tar.gz u-boot-944ac34075fe1dd1a16f0dee0d7279c8d49a537a.tar.bz2 | |
ARM: tegra114: clock: implement PLLD2 support
PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
| -rw-r--r-- | arch/arm/include/asm/arch-tegra114/clock-tables.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra114/clock.c | 7 |
2 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h index 9b95b33..95fadd0 100644 --- a/arch/arm/include/asm/arch-tegra114/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h @@ -23,6 +23,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DISPLAY2, /* These are the base clocks (inputs to the Tegra SOC) */ CLOCK_ID_32KHZ, @@ -30,7 +31,6 @@ enum clock_id { CLOCK_ID_CLK_M, CLOCK_ID_COUNT, /* number of PLLs */ - CLOCK_ID_DISPLAY2, /* placeholder */ CLOCK_ID_NONE = -1, }; diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index 9a8c10e..418ad48 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -457,6 +457,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ }; /* @@ -671,6 +673,9 @@ enum clock_id clk_id_to_pll_id(int clk_id) case TEGRA114_CLK_PLL_D: case TEGRA114_CLK_PLL_D_OUT0: return CLOCK_ID_DISPLAY; + case TEGRA114_CLK_PLL_D2: + case TEGRA114_CLK_PLL_D2_OUT0: + return CLOCK_ID_DISPLAY2; case TEGRA114_CLK_PLL_X: return CLOCK_ID_XCPU; case TEGRA114_CLK_PLL_E_OUT0: @@ -778,6 +783,8 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) case CLOCK_ID_EPCI: case CLOCK_ID_SFROM32KHZ: return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DISPLAY2: + return &clkrst->plld2; default: return NULL; } |