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| author | Hamish Martin <hamish.martin@alliedtelesis.co.nz> | 2022-10-21 10:21:59 +1300 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2022-11-07 07:17:55 +0100 |
| commit | 497db3ad89d6bc257519961cb89aa7dcda30a045 (patch) | |
| tree | 5546c56cfc1cf43b61706b35fa8d01b7cc23e19d | |
| parent | 898bd53e6a930080cee7cd7b1a09120c4dfd9467 (diff) | |
| download | u-boot-497db3ad89d6bc257519961cb89aa7dcda30a045.zip u-boot-497db3ad89d6bc257519961cb89aa7dcda30a045.tar.gz u-boot-497db3ad89d6bc257519961cb89aa7dcda30a045.tar.bz2 | |
arm: armada: dts: Add clock to armada-ap80x uart1
The uart1 node was missing the 'clock-frequency' property. This meant
the driver for this device would fail at probe.
The clock for uart1 is fed from the same source as uart0 and is a fixed
200MHz clock. This is confirmed via documentation for the CN9130 SoC
and from the equivalent code in Linux at:
<linux>/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
where uart0 and uart1 share a common 'clocks' definition.
Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Reviewed-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | arch/arm/dts/armada-ap80x.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/armada-ap80x.dtsi b/arch/arm/dts/armada-ap80x.dtsi index 8787a87..ab3c32e 100644 --- a/arch/arm/dts/armada-ap80x.dtsi +++ b/arch/arm/dts/armada-ap80x.dtsi @@ -181,7 +181,7 @@ reg-io-width = <1>; clocks = <&ap_syscon 3>; status = "disabled"; - + clock-frequency = <200000000>; }; watchdog: watchdog@610000 { |