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| author | Minda Chen <minda.chen@starfivetech.com> | 2023-08-07 16:53:37 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-08-10 10:58:01 +0800 |
| commit | eca2d41c681466c229fc0b4372432db71745c826 (patch) | |
| tree | 3fdc400dbe79d3b191e56eaa1ee20d9676157668 | |
| parent | 1037c5ba3702996d854becb3e719d44d2178c1bf (diff) | |
| download | u-boot-eca2d41c681466c229fc0b4372432db71745c826.zip u-boot-eca2d41c681466c229fc0b4372432db71745c826.tar.gz u-boot-eca2d41c681466c229fc0b4372432db71745c826.tar.bz2 | |
riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE
Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive
SYS_CACHE_SHIFT_6 to enable it.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| -rw-r--r-- | arch/riscv/cpu/jh7110/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 4d95811..c1d3e6a 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -13,6 +13,7 @@ config STARFIVE_JH7110 select SUPPORT_SPL select SPL_RAM if SPL select SPL_STARFIVE_DDR + select SYS_CACHE_SHIFT_6 select PINCTRL_STARFIVE_JH7110 imply MMC imply MMC_BROKEN_CD |