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author | Patrick Delaunay <patrick.delaunay@foss.st.com> | 2022-04-26 14:37:49 +0200 |
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committer | Patrick Delaunay <patrick.delaunay@foss.st.com> | 2022-09-06 13:54:50 +0200 |
commit | 06328d1411cf1167133aff0bd56472a8f67724e0 (patch) | |
tree | 0a2f458f9d432dc3eb570ab12ceef681e4f78193 | |
parent | 9406f9735c998a179d8ecc886ad7d5287473222f (diff) | |
download | u-boot-06328d1411cf1167133aff0bd56472a8f67724e0.zip u-boot-06328d1411cf1167133aff0bd56472a8f67724e0.tar.gz u-boot-06328d1411cf1167133aff0bd56472a8f67724e0.tar.bz2 |
clk: stm32mp: handle ck_usbo_48m clock provided by USBPHYC
Handle the input clock of RCC USB_PHY_48, provided by USBPHYC
and named "ck_usbo_48m".
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
-rw-r--r-- | drivers/clk/stm32/clk-stm32mp1.c | 35 |
1 files changed, 20 insertions, 15 deletions
diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c index 4525500..4f4524f 100644 --- a/drivers/clk/stm32/clk-stm32mp1.c +++ b/drivers/clk/stm32/clk-stm32mp1.c @@ -962,6 +962,24 @@ static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv, return dfout; } +static ulong stm32mp1_clk_get_by_name(const char *name) +{ + struct clk clk; + struct udevice *dev = NULL; + ulong clock = 0; + + if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) { + if (clk_request(dev, &clk)) { + log_err("%s request", name); + } else { + clk.id = 0; + clock = clk_get_rate(&clk); + } + } + + return clock; +} + static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) { u32 reg; @@ -1127,24 +1145,11 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) break; /* other */ case _USB_PHY_48: - clock = 48000000; + clock = stm32mp1_clk_get_by_name("ck_usbo_48m"); break; case _DSI_PHY: - { - struct clk clk; - struct udevice *dev = NULL; - - if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy", - &dev)) { - if (clk_request(dev, &clk)) { - log_err("ck_dsi_phy request"); - } else { - clk.id = 0; - clock = clk_get_rate(&clk); - } - } + clock = stm32mp1_clk_get_by_name("ck_dsi_phy"); break; - } default: break; } |