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| author | Tom Rini <trini@konsulko.com> | 2023-10-13 08:45:55 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-10-13 08:45:55 -0400 |
| commit | 6961ca0a46310da782668d8bfbf4f45b04758c55 (patch) | |
| tree | 17434f00e66b9c7fa40fdfc41717c44ab816d067 | |
| parent | 5895d5c7ab9e501205fd4b9a2b4544680ae7e72a (diff) | |
| parent | 7a82bfff5ea7089905dff14e65436d23c1e5adc4 (diff) | |
| download | u-boot-6961ca0a46310da782668d8bfbf4f45b04758c55.zip u-boot-6961ca0a46310da782668d8bfbf4f45b04758c55.tar.gz u-boot-6961ca0a46310da782668d8bfbf4f45b04758c55.tar.bz2 | |
Merge tag 'xilinx-for-v2024.01-rc1-v3' of https://source.denx.de/u-boot/custodians/u-boot-microblazeWIP/13Oct2023
Xilinx changes for v2024.01-rc1 v3
clk:
- remove additional compatible strings for Versal NET
net:
- zynq_gem: Fix clock calculation for MDC for higher frequencies
pinctrl:
- core: Extend pinmux status buffere size
- zynqmp driver: Show also tristate configuration
test:
- add test case for pxe get
Xilinx:
- describe SelectMAP boot mode
Zynq:
- Fix nand description in DT
ZynqMP:
- DTS sync patches with kernel and also W=1 related fixes
- Add support for KD240, zcu670, e-a2197 with x-prc cards, SC revB/C with i2c
description for other SC based boards
- k24 psu_init cleanup
84 files changed, 6186 insertions, 393 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fba7dfe..6e9c5f0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -396,25 +396,43 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-a2197-revA.dtb \ zynqmp-dlc21-revA.dtb \ zynqmp-e-a2197-00-revA.dtb \ + zynqmp-e-a2197-00-revB.dtb \ zynqmp-g-a2197-00-revA.dtb \ zynqmp-m-a2197-01-revA.dtb \ zynqmp-m-a2197-02-revA.dtb \ zynqmp-m-a2197-03-revA.dtb \ zynqmp-p-a2197-00-revA.dtb \ + zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo \ + zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo \ + zynqmp-p-a2197-00-revA-x-prc-03-revA.dtbo \ + zynqmp-p-a2197-00-revA-x-prc-04-revA.dtbo \ + zynqmp-p-a2197-00-revA-x-prc-05-revA.dtbo \ zynqmp-mini.dtb \ zynqmp-mini-emmc0.dtb \ zynqmp-mini-emmc1.dtb \ zynqmp-mini-nand.dtb \ zynqmp-mini-qspi.dtb \ + zynqmp-sc-revB.dtb \ + zynqmp-sc-revC.dtb \ + zynqmp-sc-vek280-revA.dtbo \ + zynqmp-sc-vek280-revB.dtbo \ + zynqmp-sc-vhk158-revA.dtbo \ + zynqmp-sc-vpk120-revB.dtbo \ + zynqmp-sc-vpk180-revA.dtbo \ + zynqmp-sc-vpk180-revB.dtbo \ + zynqmp-sc-vn-p-b2197-00-revA.dtbo \ zynqmp-sm-k24-revA.dtb \ zynqmp-smk-k24-revA.dtb \ zynqmp-sm-k26-revA.dtb \ zynqmp-smk-k26-revA.dtb \ + zynqmp-sck-kd-g-revA.dtbo \ zynqmp-sck-kr-g-revA.dtbo \ zynqmp-sck-kr-g-revB.dtbo \ zynqmp-sck-kv-g-revA.dtbo \ zynqmp-sck-kv-g-revB.dtbo \ zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \ + zynqmp-vpk120-revA.dtb \ + zynqmp-vp-x-a2785-00-revA.dtb \ zynqmp-zcu100-revC.dtb \ zynqmp-zcu102-revA.dtb \ zynqmp-zcu102-revB.dtb \ @@ -430,6 +448,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu1285-revA.dtb \ zynqmp-zcu208-revA.dtb \ zynqmp-zcu216-revA.dtb \ + zynqmp-zcu670-revA.dtb \ + zynqmp-zcu670-revB.dtb \ zynqmp-zc1232-revA.dtb \ zynqmp-zc1254-revA.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ diff --git a/arch/arm/dts/avnet-ultra96-rev1.dts b/arch/arm/dts/avnet-ultra96-rev1.dts index 96a6403..4c1bd69 100644 --- a/arch/arm/dts/avnet-ultra96-rev1.dts +++ b/arch/arm/dts/avnet-ultra96-rev1.dts @@ -2,7 +2,7 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018 - 2020, Xilinx, Inc. + * (C) Copyright 2018, Xilinx, Inc. * * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/bitmain-antminer-s9.dts b/arch/arm/dts/bitmain-antminer-s9.dts index 6c47396..0228b4b 100644 --- a/arch/arm/dts/bitmain-antminer-s9.dts +++ b/arch/arm/dts/bitmain-antminer-s9.dts @@ -52,6 +52,9 @@ &nfc0 { status = "okay"; + nand@0 { + reg = <0>; + }; }; &smcc { diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts index bd685dd..60b1c0e 100644 --- a/arch/arm/dts/versal-mini-emmc0.dts +++ b/arch/arm/dts/versal-mini-emmc0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts index fbdcf5d..751cc38 100644 --- a/arch/arm/dts/versal-mini-emmc1.dts +++ b/arch/arm/dts/versal-mini-emmc1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi index 5683a23..1abe44f 100644 --- a/arch/arm/dts/versal-mini-ospi.dtsi +++ b/arch/arm/dts/versal-mini-ospi.dtsi @@ -4,7 +4,7 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/versal-mini-qspi.dtsi b/arch/arm/dts/versal-mini-qspi.dtsi index 2fec92c..9347ea3 100644 --- a/arch/arm/dts/versal-mini-qspi.dtsi +++ b/arch/arm/dts/versal-mini-qspi.dtsi @@ -4,7 +4,7 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/versal-mini.dts b/arch/arm/dts/versal-mini.dts index a213b74..844e384 100644 --- a/arch/arm/dts/versal-mini.dts +++ b/arch/arm/dts/versal-mini.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts index dc942b0..593ca4a 100644 --- a/arch/arm/dts/zynq-cc108.dts +++ b/arch/arm/dts/zynq-cc108.dts @@ -55,7 +55,6 @@ &qspi { status = "okay"; - is-dual = <0>; num-cs = <1>; flash@0 { /* 16 MB */ compatible = "n25q128a11", "jedec,spi-nor"; diff --git a/arch/arm/dts/zynq-dlc20-rev1.0.dts b/arch/arm/dts/zynq-dlc20-rev1.0.dts index d06838c..8d00737 100644 --- a/arch/arm/dts/zynq-dlc20-rev1.0.dts +++ b/arch/arm/dts/zynq-dlc20-rev1.0.dts @@ -66,7 +66,6 @@ &qspi { bootph-all; status = "okay"; - is-dual = <0>; num-cs = <1>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; diff --git a/arch/arm/dts/zynq-minized.dts b/arch/arm/dts/zynq-minized.dts index 3214ee4..96d2937 100644 --- a/arch/arm/dts/zynq-minized.dts +++ b/arch/arm/dts/zynq-minized.dts @@ -39,7 +39,6 @@ &qspi { status = "okay"; - is-dual = <0>; num-cs = <1>; flash@0 { compatible = "micron,m25p128"; diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts index 57cb86a..8307a2e 100644 --- a/arch/arm/dts/zynq-topic-miami.dts +++ b/arch/arm/dts/zynq-topic-miami.dts @@ -33,7 +33,6 @@ &qspi { bootph-all; status = "okay"; - is-dual = <0>; num-cs = <1>; flash@0 { compatible = "st,m25p80", "n25q256a", "jedec,spi-nor"; diff --git a/arch/arm/dts/zynq-topic-miamilite.dts b/arch/arm/dts/zynq-topic-miamilite.dts index 366fd5b..af0bc7e 100644 --- a/arch/arm/dts/zynq-topic-miamilite.dts +++ b/arch/arm/dts/zynq-topic-miamilite.dts @@ -12,5 +12,4 @@ }; &qspi { - is-dual = <1>; }; diff --git a/arch/arm/dts/zynq-topic-miamiplus.dts b/arch/arm/dts/zynq-topic-miamiplus.dts index df53886..36a7db3 100644 --- a/arch/arm/dts/zynq-topic-miamiplus.dts +++ b/arch/arm/dts/zynq-topic-miamiplus.dts @@ -21,5 +21,4 @@ }; &qspi { - is-dual = <1>; }; diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 0221434..d1e9712 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -49,6 +49,9 @@ &nfc0 { status = "okay"; + nand@0 { + reg = <0>; + }; }; &smcc { diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 1ae8ea2..5f1b0b2 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -15,24 +16,6 @@ clocks = <&zynqmp_clk PL0_REF>; }; - fclk1: fclk1 { - status = "okay"; - compatible = "xlnx,fclk"; - clocks = <&zynqmp_clk PL1_REF>; - }; - - fclk2: fclk2 { - status = "okay"; - compatible = "xlnx,fclk"; - clocks = <&zynqmp_clk PL2_REF>; - }; - - fclk3: fclk3 { - status = "okay"; - compatible = "xlnx,fclk"; - clocks = <&zynqmp_clk PL3_REF>; - }; - pss_ref_clk: pss_ref_clk { bootph-all; compatible = "fixed-clock"; @@ -253,10 +236,12 @@ &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk UART0_REF>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk UART1_REF>; }; &usb0 { diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index 016081e..f737004 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -88,9 +88,13 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; - /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revB.dts b/arch/arm/dts/zynqmp-e-a2197-00-revB.dts new file mode 100644 index 0000000..8310df9 --- /dev/null +++ b/arch/arm/dts/zynqmp-e-a2197-00-revB.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal a2197 RevB System Controller + * + * (C) Copyright 2019 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include "zynqmp-e-a2197-00-revA.dts" + +/ { + model = "Versal System Controller on a2197 Eval board RevB"; /* VCK190/VMK180 */ + compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB", + "xlnx,zynqmp-a2197", "xlnx,zynqmp"; + + /delete-node/ ina226-vcco-500; + /delete-node/ ina226-vcco-501; + /delete-node/ ina226-vcco-502; +}; + +&i2c0 { + i2c-mux@74 { /* u33 */ + i2c@2 { /* PCIE_CLK */ + /delete-node/ clock-generator@6c; + }; + i2c@3 { /* PMBUS2_INA226 */ + /delete-node/ ina226@42; + /delete-node/ ina226@43; + /delete-node/ ina226@44; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index d5cfc61..36a0db4 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -81,10 +81,14 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; - phy0: ethernet-phy@0 { /* marwell m88e1512 */ - reg = <0>; - reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { /* marwell m88e1512 */ + reg = <0>; + reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; /* xlnx,phy-type = <PHY_TYPE_SGMII>; */ + }; }; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 97500b1..25ef646 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -71,7 +71,6 @@ &qspi { status = "okay"; - is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; @@ -110,10 +109,14 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ - phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; - phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; + phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ + reg = <0>; /* xlnx,phy-type = <PHY_TYPE_SGMII>; */ + }; }; }; @@ -360,25 +363,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr_sel0 { + gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr_sel1 { + gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr_sel2 { + gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr_sel3 { + gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index 3bdcf05..ece9e69 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -67,7 +67,6 @@ &qspi { status = "okay"; - is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; @@ -106,9 +105,13 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; - phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; - phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; + phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ + reg = <0>; + }; }; }; @@ -362,25 +365,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr_sel0 { + gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr_sel1 { + gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr_sel2 { + gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr_sel3 { + gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 9a693a5..7372968 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -67,7 +67,6 @@ &qspi { status = "okay"; - is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; @@ -106,9 +105,13 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; - phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; - phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; + phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ + reg = <0>; + }; }; }; @@ -356,25 +359,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr_sel0 { + gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr_sel1 { + gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr_sel2 { + gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr_sel3 { + gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts index 08ec2f7..02e80bd 100644 --- a/arch/arm/dts/zynqmp-mini-emmc0.dts +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts index 905de08..ce1cdb2 100644 --- a/arch/arm/dts/zynqmp-mini-emmc1.dts +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts index e5688fd..e0517cf 100644 --- a/arch/arm/dts/zynqmp-mini-nand.dts +++ b/arch/arm/dts/zynqmp-mini-nand.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index fc0a2e8..ee8be53 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2020, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso new file mode 100644 index 0000000..197dc25 --- /dev/null +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP System Controller X-PRC-01 revA (SE1) + * + * (C) Copyright 2019 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01"; + + fragment@0 { + target = <&dc_i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + x_prc_eeprom: eeprom@52 { /* u120 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + x_prc_tca9534: gpio@22 { /* u121 tca9534 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr-sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr-sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr-sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr-sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; /* Must be enabled via J242 */ + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + eeprom_versal: eeprom@51 { /* u116 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso new file mode 100644 index 0000000..8eb6e40 --- /dev/null +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) + * + * (C) Copyright 2019 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02"; + + fragment@0 { + target = <&dc_i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + x_prc_eeprom: eeprom@52 { /* u16 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + x_prc_tca9534: gpio@22 { /* u17 tca9534 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr-sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr-sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr-sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr-sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; /* Must be enabled via J242 */ + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + eeprom_versal: eeprom@51 { /* u12 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso new file mode 100644 index 0000000..af7a3ce --- /dev/null +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) + * + * (C) Copyright 2019 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03"; + + fragment@0 { + target = <&dc_i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + x_prc_eeprom: eeprom@52 { /* u1 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + x_prc_tca9534: gpio@22 { /* u3 tca9534 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr-sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr-sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr-sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr-sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + x_prc_si5338: clock-generator@70 { /* U9 */ + compatible = "silabs,si5338"; + reg = <0x70>; /* FIXME */ + }; + }; + }; + + fragment@1 { + target = <&i2c1>; /* Must be enabled via J90/J91 */ + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + eeprom_versal: eeprom@51 { /* u2 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso new file mode 100644 index 0000000..29a6c2a --- /dev/null +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) + * + * (C) Copyright 2019 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04"; + + fragment@0 { + target = <&dc_i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + x_prc_eeprom: eeprom@52 { /* u120 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + x_prc_tca9534: gpio@22 { /* u121 tca9534 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr-sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr-sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr-sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr-sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + + si570_gem_tsu: clock-generator@5d { /* u164 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; /* FIXME */ + clock-frequency = <300000000>; + clock-output-names = "si570_gem_tsu_clk"; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + eeprom_versal: eeprom@51 { /* u153 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso new file mode 100644 index 0000000..6ddf18c --- /dev/null +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) + * + * (C) Copyright 2019 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05"; + + fragment@0 { + target = <&dc_i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + x_prc_eeprom: eeprom@52 { /* u120 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + x_prc_tca9534: gpio@22 { /* u121 tca9534 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr-sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr-sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr-sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr-sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + + si570_gem_tsu: clock-generator@5d { /* u164 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; /* FIXME */ + clock-frequency = <300000000>; + clock-output-names = "si570_gem_tsu_clk"; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + eeprom_versal: eeprom@51 { /* u153 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index 16691a8..c456c37 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -91,9 +91,13 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; - /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; @@ -423,25 +427,25 @@ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; - gtr_sel0 { + gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; - gtr_sel1 { + gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; - gtr_sel2 { + gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; - gtr_sel3 { + gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts new file mode 100644 index 0000000..e0b554c --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-revB.dts @@ -0,0 +1,430 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP Generic System Controller + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP Generic System Controller"; + compatible = "xlnx,zynqmp-sc-revB", "xlnx,zynqmp-sc", "xlnx,zynqmp"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + nvmem0 = &eeprom; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + spi0 = &qspi; + spi1 = &spi0; + spi2 = &spi1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + fwuen { + label = "sw16"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + linux,code = <BTN_MISC>; + wakeup-source; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + ds40-led { + label = "heartbeat"; + gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + ds44-led { + label = "status"; + gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; + }; + }; + + si5332_2: si5332_2 { /* u42 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + pwm-fan { + compatible = "pwm-fan"; + status = "okay"; + pwms = <&ttc0 2 40000 1>; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ + "QSPI_CS_B", "", "LED1", "LED2", "", /* 5 - 9 */ + "", "ZU4_TRIGGER", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ + "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ + "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "I2C1_SCL", /* 20 - 24 */ + "I2C1_SDA", "UART0_RXD", "UART0_TXD", "", "", /* 25 - 29 */ + "", "", "", "", "I2C0_SCL", /* 30 - 34 */ + "I2C0_SDA", "UART1_TXD", "UART1_RXD", "GEM_TX_CLK", "GEM_TX_D0", /* 35 - 39 */ + "GEM_TX_D1", "GEM_TX_D2", "GEM_TX_D3", "GEM_TX_CTL", "GEM_RX_CLK", /* 40 - 44 */ + "GEM_RX_D0", "GEM_RX_D1", "GEM_RX_D2", "GEM_RX_D3", "GEM_RX_CTL", /* 45 - 49 */ + "GEM_MDC", "GEM_MDIO", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ + "", "", "", "", "", /* 65 - 69 */ + "", "", "", "", "", /* 70 - 74 */ + "", "", "ETH_RESET_B", /* 75 - 77, MIO end and EMIO start */ + "", "", /* 78 - 79 */ + "", "", "", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 -89 */ + "", "", "", "", "", /* 90 - 94 */ + "", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 173 */ +}; + +&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem1_default>; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@1 { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <1>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; + reset-assert-us = <100>; + reset-deassert-us = <280>; + }; + }; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&i2c1 { /* i2c1 MIO 24-25 */ + status = "okay"; + bootph-all; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + /* Use for storing information about SC board */ + eeprom: eeprom@54 { /* u34 - m24128 16kB */ + compatible = "st,24c128", "atmel,24c128"; + reg = <0x54>; /* & 0x5c */ + bootph-all; + }; +}; + +/* USB 3.0 only */ +&psgtr { + status = "okay"; + /* nc, nc, usb3 */ + clocks = <&si5332_2>; + clock-names = "ref2"; +}; + +&qspi { /* MIO 0-5 */ + status = "okay"; + /* QSPI should also have PINCTRL setup */ + flash@0 { + compatible = "mt25qu512a", "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; /* 40MHz */ + partition@0 { + label = "Image Selector"; + reg = <0x0 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@80000 { + label = "Image Selector Golden"; + reg = <0x80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@100000 { + label = "Persistent Register"; + reg = <0x100000 0x20000>; /* 128KB */ + }; + partition@120000 { + label = "Persistent Register Backup"; + reg = <0x120000 0x20000>; /* 128KB */ + }; + partition@140000 { + label = "Open_1"; + reg = <0x140000 0xC0000>; /* 768KB */ + }; + partition@200000 { + label = "Image A (FSBL, PMU, ATF, U-Boot)"; + reg = <0x200000 0xD00000>; /* 13MB */ + }; + partition@f00000 { + label = "ImgSel Image A Catch"; + reg = <0xF00000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@f80000 { + label = "Image B (FSBL, PMU, ATF, U-Boot)"; + reg = <0xF80000 0xD00000>; /* 13MB */ + }; + partition@1c80000 { + label = "ImgSel Image B Catch"; + reg = <0x1C80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@1d00000 { + label = "Open_2"; + reg = <0x1D00000 0x100000>; /* 1MB */ + }; + partition@1e00000 { + label = "Recovery Image"; + reg = <0x1E00000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2000000 { + label = "Recovery Image Backup"; + reg = <0x2000000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2200000 { + label = "U-Boot storage variables"; + reg = <0x2200000 0x20000>; /* 128KB */ + }; + partition@2220000 { + label = "U-Boot storage variables backup"; + reg = <0x2220000 0x20000>; /* 128KB */ + }; + partition@2240000 { + label = "SHA256"; + reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ + read-only; + lock; + }; + partition@2280000 { + label = "Secure OS Storage"; + reg = <0x2280000 0x20000>; /* 128KB */ + }; + partition@22A0000 { + label = "User"; + reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ + }; + }; +}; + +&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ + status = "okay"; + non-removable; + disable-wp; + bus-width = <8>; + xlnx,mio-bank = <0>; +}; + +&ttc0 { + status = "okay"; + #pwm-cells = <3>; +}; + +&uart1 { /* uart0 MIO36-37 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; + +&pinctrl0 { /* required by spec */ + status = "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_8_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_8_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_34_grp", "gpio0_35_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_34_grp", "gpio0_35_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups = "ethernet1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO44", "MIO46", "MIO48"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO45", "MIO47", "MIO49"; + bias-disable; + low-power-disable; + }; + + conf-tx { + pins = "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + bias-disable; + }; + + mux-mdio { + function = "mdio1"; + groups = "mdio1_0_grp"; + }; + + mux { + function = "ethernet1"; + groups = "ethernet1_0_grp"; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-sc-revC.dts b/arch/arm/dts/zynqmp-sc-revC.dts new file mode 100644 index 0000000..530a4a5 --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-revC.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP Generic System Controller + * + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include "zynqmp-sc-revB.dts" + +/ { + model = "ZynqMP Generic System Controller"; + compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp"; +}; + +&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ + /delete-node/ mdio; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@1 { /* ADI1300 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id0283.bc30"; + reg = <1>; + adi,rx-internal-delay-ps = <2400>; + adi,tx-internal-delay-ps = <2400>; + adi,fifo-depth-bits = <8>; + reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <5000>; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso new file mode 100644 index 0000000..3320bbc --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VEK280 revA + * + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA", + "xlnx,zynqmp-vek280", "xlnx,zynqmp"; + + vc7_xin: vc7-xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + tca6416_u233: gpio@20 { /* u233 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "", "", "SFP_MOD_ABS", "SFP_TX_DISABLE", /* 0 - 3 */ + "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */ + "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ + "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + pmbus_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* On connector J325 */ + ir35215_46: pmic@46 { /* IR35215 - u152 */ + compatible = "infineon,ir35215"; + reg = <0x46>; /* i2c addr - 0x16 */ + }; + irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ + compatible = "infineon,irps5401"; + reg = <0x47>; /* i2c addr 0x17 */ + }; + irps5401_48: pmic@48 { /* IRPS5401 - u279 */ + compatible = "infineon,irps5401"; + reg = <0x48>; /* i2c addr 0x18 */ + }; + ir38064_49: regulator@49 { /* IR38064 - u295 */ + compatible = "infineon,ir38064"; + reg = <0x49>; /* i2c addr 0x19 */ + }; + irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ + compatible = "infineon,irps5401"; + reg = <0x4c>; /* i2c addr 0x1c */ + }; + irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x4d>; /* i2c addr 0x1d */ + }; + ir38060_4e: regulator@4e { /* IR38060 - u282 */ + compatible = "infineon,ir38060"; + reg = <0x4e>; /* i2c addr 0x1e */ + }; + }; + pmbus1_ina226_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* alerts coming to u233 and SC */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <500>; /* r440 */ + }; + vcc_soc: ina226@41 { /* u161 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <500>; /* r1702 */ + }; + vcc_pmc: ina226@42 { /* u163 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; /* r382 */ + }; + vcc_ram: ina226@43 { /* u355 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; /* r2417 */ + }; + vcc_pslp: ina226@44 { /* u165 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; /* r1830 */ + }; + vcc_psfp: ina226@45 { /* u260 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; /* r2386 */ + }; + vcco_hdio: ina226@46 { /* u356 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; /* r2392 */ + }; + }; + i2c@2 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + pmbus2_ina226_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* alerts coming to u233 and SC */ + vccaux: ina226@40 { /* u166 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; /* r2384 */ + }; + vccaux_pmc: ina226@41 { /* u168 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; /* r2000 */ + }; + mgtavcc: ina226@42 { /* u265 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; /* r1829 */ + }; + vcc1v5: ina226@43 { /* u264 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; /* r2397 */ + }; + vcco_mio: ina226@45 { /* u172 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; /* r2401 */ + }; + mgtavtt: ina226@46 { /* u188 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <500>; /* r1384 */ + }; + vcco_502: ina226@47 { /* u174 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; /* r1994 */ + }; + mgtvccaux: ina226@48 { /* u176 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; /* r2384 */ + }; + vcc1v1_lp4: ina226@49 { /* u306 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <500>; /* r2064 */ + }; + vadj_fmc: ina226@4a { /* u281 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; /* r2031 */ + }; + lpdmgtyavcc: ina226@4b { /* u177 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; /* r2004 */ + }; + lpdmgtyavtt: ina226@4c { /* u309 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <5000>; /* r1229 */ + }; + lpdmgtyvccaux: ina226@4d { /* u234 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <5000>; /* r1679 */ + }; + }; + i2c@4 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + rc21008a_gtclk1: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* connector j374 */ + /* rc21008a at 0x9 u299 */ + vc7: clock-generator@9 { + compatible = "renesas,rc21008a"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + }; + fmcp1_iic: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* to j51c */ + }; + sfp: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* sfp+ connector J376 */ + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso new file mode 100644 index 0000000..a3983f3 --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VEK280 revB + * + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc + * + * Michal Simek <michal.simek@amd.com> + */ + +#include "zynqmp-sc-vek280-revA.dtso" + +&{/} { + compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", + "xlnx,zynqmp-vek280", "xlnx,zynqmp"; +}; diff --git a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso new file mode 100644 index 0000000..2ce6937 --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VHK158 revA + * + * (C) Copyright 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-vhk158-revA", + "xlnx,zynqmp-vhk158", "xlnx,zynqmp"; + + vc7_xin: vc7-xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + tca6416_u233: gpio@20 { /* u233 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "", "", "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", /* 0 - 3 */ + "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */ + "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ + "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + pmbus_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* On connector J325 */ + ir38064_41: regulator@41 { /* IR38064 - u294 */ + compatible = "infineon,ir38064"; + reg = <0x41>; /* i2c addr 0x11 */ + }; + irps5401_45: pmic5401@45 { /* IRPS5401 - u280 */ + compatible = "infineon,irps5401"; + reg = <0x45>; /* i2c addr 0x15 */ + }; + ir35221_46: pmic@46 { /* IR35221 - u152 */ + compatible = "infineon,ir35221"; + reg = <0x46>; /* i2c addr - 0x16 */ + }; + irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ + compatible = "infineon,irps5401"; + reg = <0x47>; /* i2c addr 0x17 */ + }; + irps5401_48: regulator@48 { /* IRPS5401 - u279 */ + compatible = "infineon,irps5401"; + reg = <0x48>; /* i2c addr 0x18 */ + }; + ir38164_49: regulator@49 { /* IR38164 - u295 */ + compatible = "infineon,ir38164"; + reg = <0x49>; /* i2c addr 0x19 */ + }; + ir38060_4a: regulator@4a { /* IR38060 - u259 */ + compatible = "infineon,ir38164"; + reg = <0x4a>; /* i2c addr 0x1a */ + }; + irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ + compatible = "infineon,irps5401"; + reg = <0x4c>; /* i2c addr 0x1c */ + }; + irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x4d>; /* i2c addr 0x1d */ + }; + ir38060_4e: regulator@4e { /* IR38060 - u282 */ + compatible = "infineon,ir38164"; + reg = <0x4e>; /* i2c addr 0x1e */ + }; + }; + pmbus1_ina226_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME check alerts coming to SC */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <500>; /* R440 */ + }; + vcc_soc: ina226@41 { /* u161 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <500>; /* R1702 */ + }; + vcc_pmc: ina226@42 { /* u163 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; /* R382 */ + }; + vcc_ram: ina226@43 { /* u5 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <500>; /* R121 */ + }; + vcc_pslp: ina226@44 { /* u165 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; /* R1830 */ + }; + vcc_psfp: ina226@45 { /* u260 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; /* R1834 */ + }; + vcco_hbm: ina226@46 { /* u164 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <500>; /* R2056 */ + }; + vcc_hbm: ina226@47 { /* u307 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <500>; /* R2068 */ + }; + vccaux_hbm: ina226@48 { /* u308 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; /* R2019 */ + }; + }; + i2c@2 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + pmbus2_ina226_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* FIXME check alerts coming to SC */ + vccaux: ina226@40 { /* u166 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; /* R2060 */ + }; + vccaux_pmc: ina226@41 { /* u168 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <500>; /* R2000 */ + }; + mgtavcc: ina226@42 { /* u265 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <500>; /* R1829 */ + }; + vcc1v5: ina226@43 { /* u264 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <500>; /* R1221 */ + }; + vcco_mio: ina226@45 { /* u172 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <500>; /* R2015 */ + }; + mgtavtt: ina226@46 { /* u188 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <500>; /* R1384 */ + }; + vcco_502: ina226@47 { /* u174 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <500>; /* R1994 */ + }; + mgtvccaux: ina226@48 { /* u176 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <500>; /* R1232 */ + }; + vcc1v2_rdimm: ina226@49 { /* u306 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <500>; /* R2064 */ + }; + vadj_fmc: ina226@4a { /* u281 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; /* R2031 */ + }; + lpdmgtyavcc: ina226@4b { /* u177 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <500>; /* R2004 */ + }; + lpdmgtyavtt: ina226@4c { /* u309 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <500>; /* R1229 */ + }; + lpdmgtyvccaux: ina226@4d { /* u234 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <500>; /* R1679 */ + }; + }; + i2c@4 { /* NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + rc21008a_gtclk1: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + vc7_1: clock-generator@9 { + compatible = "renesas,rc21008a"; + clock-output-names = "rc21008a-0"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + /* i2c@9 - U299 */ + }; + rc21008a_gtclk2: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + vc7_2: clock-generator@9 { + compatible = "renesas,rc21008a"; + clock-output-names = "rc21008a-1"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + /* i2c@9 - U300 */ + }; + sync_8a34001: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* U219 - i2c address UNKNOWN */ + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@74 { /* u35 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + ddr4_dimm0: i2c@0 { /* wired but NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + fmcp1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME connection to Samtec J51C */ + /* expected eeprom 0x50 SE cards */ + }; + qsfp1_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* J350 connector */ + }; + qsfp2_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* J351 connector */ + }; + qsfp3_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* J352 connector */ + }; + qsfp4_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* J353 connector */ + }; + qsfpdd_i2c: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* J1/J2 connectors */ + }; + ddr4_dimm1: i2c@7 { /* wired but NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso new file mode 100644 index 0000000..5333767 --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2) + * + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + +&{/} { + #address-cells = <2>; + #size-cells = <2>; + + compatible = "xlnx,zynqmp-sc-vn-p-b2197-revA", + "xlnx,zynqmp-sc-vn-p-b2197", "xlnx,zynqmp"; + + aliases { + nvmem1 = &x_prc_eeprom; + }; + + ina226-u1700 { + compatible = "iio-hwmon"; + io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>; + }; + ina226-u1732 { + compatible = "iio-hwmon"; + io-channels = <&vcc_lpd_ina 0>, <&vcc_lpd_ina 1>, <&vcc_lpd_ina 2>; + }; + ina226-u1733 { + compatible = "iio-hwmon"; + io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>; + }; + ina226-u1736 { + compatible = "iio-hwmon"; + io-channels = <&vccaux_lpd_ina 0>, <&vccaux_lpd_ina 1>, <&vccaux_lpd_ina 2>; + }; + ina226-u1737 { + compatible = "iio-hwmon"; + io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>; + }; + ina226-u1739 { + compatible = "iio-hwmon"; + io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>; + }; + ina226-u1741 { + compatible = "iio-hwmon"; + io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>; + }; + ina226-u1743 { + compatible = "iio-hwmon"; + io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>; + }; + ina226-u1745 { + compatible = "iio-hwmon"; + io-channels = <&vcco_700_ina 0>, <&vcco_700_ina 1>, <&vcco_700_ina 2>; + }; + ina226-u1747 { + compatible = "iio-hwmon"; + io-channels = <&vcco_706_ina 0>, <&vcco_706_ina 1>, <&vcco_706_ina 2>; + }; + ina226-u1750 { + compatible = "iio-hwmon"; + io-channels = <>yp_avcc_ina 0>, <>yp_avcc_ina 1>, <>yp_avcc_ina 2>; + }; + ina226-u1752 { + compatible = "iio-hwmon"; + io-channels = <>yp_avtt_ina 0>, <>yp_avtt_ina 1>, <>yp_avtt_ina 2>; + }; + ina226-u1754 { + compatible = "iio-hwmon"; + io-channels = <>yp_avccaux_ina 0>, <>yp_avccaux_ina 1>, <>yp_avccaux_ina 2>; + }; + ina226-u1756 { + compatible = "iio-hwmon"; + io-channels = <>m_avcc_ina 0>, <>m_avcc_ina 1>, <>m_avcc_ina 2>; + }; + ina226-u1758 { + compatible = "iio-hwmon"; + io-channels = <>m_avtt_ina 0>, <>m_avtt_ina 1>, <>m_avtt_ina 2>; + }; + ina226-u1760 { + compatible = "iio-hwmon"; + io-channels = <>m_avccaux_ina 0>, <>m_avccaux_ina 1>, <>m_avccaux_ina 2>; + }; + + /* sc_vpk180_axi_iic_0_0: i2c@80050000 - UNUSED NOW */ /* SI5332 */ + + /* Connect to J212G pin G29/G30 - sysmon connector */ + /* sc_vpk180_axi_iic_1_0: i2c@80060000 */ /* SYSMON */ + + /* FIXME Fan control via u1702 - max6643 and mux via J1703 - not SW controllable - via EMIO */ +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + /* u97 eeprom at 0x54 described in sc-revB - WP protection via BOARD_EEPROM_WP - J1801 */ + /* DC/SE eeprom at 0x52 */ + x_prc_eeprom: eeprom@52 { /* u4 - DC card identification - possible WP */ + compatible = "atmel,24c02"; + reg = <0x52>; + bootph-all; + }; + + x_prc_tca9534: gpio@22 { /* u5 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "xprc_sw_1", "xprc_sw_2", "xprc_sw_3", "xprc_sw_4", + "", "", "", ""; + gtr-sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "xprc_sw_1"; + }; + gtr-sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "xprc_sw_1"; + }; + gtr-sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "xprc_sw_1"; + }; + gtr-sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "xprc_sw_1"; + }; + }; + + /* FMC eeproms at 0x50/0x51 */ + /* via j3/j5 to 0x68 to u32/9FGV1006C + + /* i2c_main_1 - u147 - j157 - disable translation, add 8 */ + /* J1 - OE for u43@55 + 8 - 161,132813MHz - QSFP56G_0 */ + qsfp56g_0_clk: clock-controller@5d { + compatible = "renesas,proxo-xp"; + reg = <0x5d>; + #clock-cells = <0>; + clock-output-names = "qsfp56g_0_clk"; + }; + + /* J2 - OE for u41@57 + 8 - 322,265625MHz - QSFP56G_1 */ + qsfp56g_1_clk: clock-controller@5f { + compatible = "renesas,proxo-xp"; + reg = <0x5f>; + #clock-cells = <0>; + clock-output-names = "qsfp56g_1_clk"; + }; + + /* J81 - OE for u115@50 + 8 - 320MHz - LPDDR5_C0 */ + lpddr5_c0_clk: clock-controller@58 { + compatible = "renesas,proxo-xp"; + reg = <0x58>; + #clock-cells = <0>; + clock-output-names = "lpddr5_c0_clk"; + }; + + /* i2c_main_2 - u148 - j122 - disable translation, add 9 */ + /* J112 - OE for u63@50 + 9 - 320MHz - LPDDR5_C2 */ + lpddr5_c2_clk: clock-controller@59 { + compatible = "renesas,proxo-xp"; + reg = <0x59>; + #clock-cells = <0>; + clock-output-names = "lpddr5_c2_clk"; + }; + + /* i2c_main_3 - u149 - j154 - disable translation, add 6 */ + /* J78 - OE for u116@50 + 6 - 320MHz - DDR5_UDIMM */ + ddr5_udimm_clk: clock-controller@56 { + compatible = "renesas,proxo-xp"; + reg = <0x56>; + #clock-cells = <0>; + clock-output-names = "ddr5_udimm_clk"; + }; + + /* i2c_main_4 - u150 - j146 - disable translation, add 5 */ + /* J107 - OE for u39@50 + 5 - 33,3333MHz - PS_REFCLK */ + ps_refclk: clock-controller@55 { + compatible = "renesas,proxo-xp"; + reg = <0x55>; + #clock-cells = <0>; + clock-output-names = "ps_refclk"; + }; + + /* i2c_main_5 - u1782 - j1798 - disable translation, add 7 */ + /* J77 - OE for u1783@50 + 7 - 320MHz - DDR4 */ + ddr4_clk: clock-controller@57 { + compatible = "renesas,proxo-xp"; + reg = <0x57>; + #clock-cells = <0>; + clock-output-names = "ddr4_clk"; + }; + + /* LTC4316 - not wired XORH/XORL - FIXME */ + /* J3 gate - FIXME should be connected for SW handling */ + /* i2c_main_1 bus */ + i2c1_u32: clock-controller@68 { + compatible = "renesas,9fgv1006"; + reg = <0x68>; + }; + + /* J71 - selection to LP_I2C_SCL_J or LP_I2C_PMC_SCL_J */ + /* J70 - selection to LP_I2C_SDA_J or LP_I2C_PMC_SDA_J */ + /* this should be SW controlable too */ +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + /* Via j11/j12 can also go to u17/IML3112 - 1:2 multiplexer - also accessed from Versal NET */ + /* Connection DDR5_UDIMM - SPD can be from 0x50-0x57 */ + /* FIXME gpio should handle SYSCTLR_PMBUS_ALERT and also INA226_PMBUS_ALERT */ + + /* ina226_pmbus - J55 - disable INA226_PMBUS */ + vcc_ram_ina: power-monitor@40 { /* u1700 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x40>; + shunt-resistor = <1000>; /* R1996 */ + }; + + vcc_lpd_ina: power-monitor@41 { /* u1732 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x41>; + shunt-resistor = <1000>; /* R2017 */ + }; + + vccaux_ina: power-monitor@42 { /* u1733 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x42>; + shunt-resistor = <1000>; /* R2037 */ + }; + + vccaux_lpd_ina: power-monitor@43 { /* u1736 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x43>; + shunt-resistor = <1000>; /* R2057 */ + }; + + vcco_500_ina: power-monitor@44 { /* u1737 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x44>; + shunt-resistor = <1000>; /* R2069 */ + }; + + vcco_501_ina: power-monitor@45 { /* u1739 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x45>; + shunt-resistor = <1000>; /* R2089 */ + }; + + vcco_502_ina: power-monitor@46 { /* u1741 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x46>; + shunt-resistor = <1000>; /* R2108 */ + }; + + vcco_503_ina: power-monitor@47 { /* u1743 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x47>; + shunt-resistor = <1000>; /* R2127 */ + }; + + vcco_700_ina: power-monitor@48 { /* u1745 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x48>; + shunt-resistor = <1000>; /* R2154 */ + }; + + vcco_706_ina: power-monitor@49 { /* u1747 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x49>; + shunt-resistor = <1000>; /* R2175 */ + }; + + gtyp_avcc_ina: power-monitor@4a { /* u1750 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4a>; + shunt-resistor = <1000>; /* R2195 */ + }; + + gtyp_avtt_ina: power-monitor@4b { /* u1752 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4b>; + shunt-resistor = <1000>; /* R2215 */ + }; + + gtyp_avccaux_ina: power-monitor@4c { /* u1754 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4c>; + shunt-resistor = <5000>; /* R2235 */ + }; + + gtm_avcc_ina: power-monitor@4d { /* u1756 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4d>; + shunt-resistor = <1000>; /* R2256 */ + }; + + gtm_avtt_ina: power-monitor@4e { /* u1758 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4e>; + shunt-resistor = <1000>; /* R2276 */ + }; + + gtm_avccaux_ina: power-monitor@4f { /* u1760 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4f>; + shunt-resistor = <5000>; /* R2296 */ + }; + + /* pmbus - J50 - disable main PMBUS - also going to j132 */ + vcc_ram: regulator@a { /* u1730 */ + compatible = "ti,tps544b25"; + reg = <0xa>; + }; + + vcc_lpd: regulator@b { /* u1731 */ + compatible = "ti,tps544b25"; + reg = <0xb>; + }; + + vccaux: regulator@1a { /* u1734 */ + compatible = "ti,tps544b25"; + reg = <0x1a>; + }; + + vcco_503: regulator@12 { /* u1744 */ + compatible = "ti,tps546b24a"; + reg = <0x12>; + }; + + vcco_700: regulator@16 { /* u1746 */ + compatible = "ti,tps544b25"; + reg = <0x16>; + }; + + vcco_706: regulator@17 { /* u1748 */ + compatible = "ti,tps544b25"; + reg = <0x17>; + }; + + gtm_avcc: regulator@23 { /* u1755 */ + compatible = "ti,tps544b25"; + reg = <0x23>; + }; + + gtm_avtt: regulator@24 { /* u1757 */ + compatible = "ti,tps544b25"; + reg = <0x24>; + }; + + gtm_avccaux: regulator@25 { /* u1759 */ + compatible = "ti,tps544b25"; + reg = <0x25>; + }; + + util_1v8: regulator@15 { /* u1765 */ + compatible = "ti,tps544b25"; + reg = <0x15>; + }; + + ucd90320: power-sequencer@73 { /* u1768 */ + compatible = "ti,ucd90320"; + reg = <0x73>; + }; + + /* EXT_PMBUS main - J10 - disable extended PMBUS */ + vccint: tps53681@60 { /* u1712 - J1770 reset jumper */ + compatible = "ti,tps53681", "ti,tps53679"; + reg = <0x60>; + /* vccint, vcc_cpm5n */ + }; + + vcc_io_soc: tps53681@61 { /* u1721 - J1772 reset jumper */ + compatible = "ti,tps53681", "ti,tps53679"; + reg = <0x61>; + /* vcc_io_soc, vcc_fpd */ + }; + + vccaux_lpd: regulator@d { /* u1735 */ + compatible = "ti,tps544b25"; + reg = <0xd>; + }; + + vcco_500: regulator@13 { /* u1738 */ + compatible = "ti,tps546b24a"; + reg = <0x13>; + }; + + vcco_501: regulator@10 { /* u1740 */ + compatible = "ti,tps546b24a"; + reg = <0x10>; + }; + + vcco_502: regulator@11 { /* u1742 */ + compatible = "ti,tps546b24a"; + reg = <0x11>; + }; + + gtyp_avcc: regulator@20 { /* u1749 */ + compatible = "ti,tps544b25"; + reg = <0x20>; + }; + + gtyp_avtt: regulator@21 { /* u1751 */ + compatible = "ti,tps544b25"; + reg = <0x21>; + }; + + gtyp_avccaux: regulator@22 { /* u1753 */ + compatible = "ti,tps544b25"; + reg = <0x22>; + }; + + lp5_vdd1_1v8: regulator@e { /* u1761 - FIXME no ina226 */ + compatible = "ti,tps544b25"; + reg = <0xe>; + }; + + lp5_vdd2_1v05: regulator@f { /* u1762 - FIXME no ina226 */ + compatible = "ti,tps544b25"; + reg = <0xf>; + }; + + lp5_vddq_0v5: regulator@14 { /* u1763 - FIXME no ina226 */ + compatible = "ti,tps546b24a"; + reg = <0x14>; + }; +}; diff --git a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso new file mode 100644 index 0000000..750bc39 --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VPK120 revB + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + + +&{/} { + compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-vpk120-revB", + "xlnx,zynqmp-vpk120", "xlnx,zynqmp"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + tca6416_u233: gpio@20 { /* u233 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "", "", "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", /* 0 - 3 */ + "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */ + "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ + "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + pmbus_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* On connector J325 */ + ir38060_41: regulator@41 { /* IR38060 - u259 */ + compatible = "infineon,ir38060", "infineon,ir38064"; + reg = <0x41>; /* i2c addr 0x11 */ + }; + ir38164_43: regulator@43 { /* IR38164 - u13 */ + compatible = "infineon,ir38164"; + reg = <0x43>; /* i2c addr 0x13 */ + }; + ir35221_46: pmic@46 { /* IR35221 - u152 */ + compatible = "infineon,ir35221"; + reg = <0x46>; /* i2c addr - 0x16 */ + }; + irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ + compatible = "infineon,irps5401"; + reg = <0x47>; /* i2c addr 0x17 */ + }; + ir38164_49: regulator@49 { /* IR38164 - u189 */ + compatible = "infineon,ir38164"; + reg = <0x49>; /* i2c addr 0x19 */ + }; + irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ + compatible = "infineon,irps5401"; + reg = <0x4c>; /* i2c addr 0x1c */ + }; + irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x4d>; /* i2c addr 0x1d */ + }; + ir38164_4e: regulator@4e { /* IR38164 - u185 */ + compatible = "infineon,ir38164"; + reg = <0x4e>; /* i2c addr 0x1e */ + }; + ir38164_4f: regulator@4f { /* IR38164 - u187 */ + compatible = "infineon,ir38164"; + reg = <0x4f>; /* i2c addr 0x1f */ + }; + }; + pmbus1_ina226_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME check alerts coming to SC */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + vcc_soc: ina226@41 { /* u161 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + vcc_pmc: ina226@42 { /* u163 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + vcc_ram: ina226@43 { /* u5 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vcc_pslp: ina226@44 { /* u165 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + vcc_psfp: ina226@45 { /* u164 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + }; + i2c@2 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + pmbus2_ina226_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* FIXME check alerts coming to SC */ + vccaux: ina226@40 { /* u166 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + vccaux_pmc: ina226@41 { /* u168 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + mgtavcc: ina226@42 { /* u265 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + vcc1v5: ina226@43 { /* u264 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vcco_mio: ina226@45 { /* u172 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + mgtavtt: ina226@46 { /* u188 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <2000>; + }; + vcco_502: ina226@47 { /* u174 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + mgtvccaux: ina226@48 { /* u176 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + vcc1v1_lp4: ina226@49 { /* u186 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <2000>; + }; + vadj_fmc: ina226@4a { /* u184 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <2000>; + }; + lpdmgtyavcc: ina226@4b { /* u177 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + lpdmgtyavtt: ina226@4c { /* u260 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <2000>; + }; + lpdmgtyvccaux: ina226@4d { /* u234 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <5000>; + }; + }; + i2c@4 { /* NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + i2c@5 { /* NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + user_si570: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5f>; + temperature-stability = <50>; + factory-fout = <100000000>; + clock-frequency = <100000000>; + clock-output-names = "fmc_si570"; + silabs,skip-recall; + }; + + }; + /* 7 unused */ + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@74 { /* u35 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + ref_clk_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + ref_clk: clock-generator@5d { /* u32 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <33333333>; + clock-frequency = <33333333>; + clock-output-names = "ref_clk"; + silabs,skip-recall; + }; + }; + fmcp1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME connection to Samtec J51C */ + /* expected eeprom 0x50 SE cards */ + }; + i2c@2 { /* NC - FIXME */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + lpddr4_si570_clk3_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + lpddr4_clk3: clock-generator@60 { /* u4 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk3"; + silabs,skip-recall; + }; + }; + lpddr4_si570_clk2_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + lpddr4_clk2: clock-generator@60 { /* u3 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk2"; + silabs,skip-recall; + }; + }; + lpddr4_si570_clk1_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + lpddr4_clk1: clock-generator@60 { /* u248 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk1"; + silabs,skip-recall; + }; + }; + qsfpdd_i2c: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* J1/J2 connectors */ + }; + idt8a34001_i2c: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* Via J310 connector */ + idt_8a34001: phc@5b { + compatible = "idt,8a34001"; /* u219B */ + reg = <0x5b>; /* FIXME not in schematics */ + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso new file mode 100644 index 0000000..551341f --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VPK180 revA + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + + +&{/} { + compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA", + "xlnx,zynqmp-vpk180", "xlnx,zynqmp"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + tca6416_u233: gpio@20 { /* u233 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", "QSFPDD3_MODSELL", "QSFPDD4_MODSELL", /* 0 - 3 */ + "PMBUS2_INA226_ALERT", "QSFPDD5_MODSELL", "QSFPDD6_MODSELL", "", /* 4 - 7 */ + "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "UTIL_3V3_VRHOT_B", /* 10 - 13 */ + "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + pmbus_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* On connector J325 */ + ir38060_41: regulator@41 { /* IR38060 - u259 */ + compatible = "infineon,ir38060", "infineon,ir38064"; + reg = <0x41>; /* i2c addr 0x11 */ + }; + ir35221_45: pmic@45 { /* IR35221 - u291 */ + compatible = "infineon,ir35221"; + reg = <0x45>; /* i2c addr - 0x15 */ + }; + ir35221_46: pmic@46 { /* IR35221 - u152 */ + compatible = "infineon,ir35221"; + reg = <0x46>; /* i2c addr - 0x16 */ + }; + irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ + compatible = "infineon,irps5401"; + reg = <0x47>; /* i2c addr 0x17 */ + }; + irps5401_48: pmic@48 { /* IRPS5401 - u295 */ + compatible = "infineon,irps5401"; + reg = <0x48>; /* i2c addr 0x18 */ + }; + ir38164_49: regulator@49 { /* IR38164 - u189 */ + compatible = "infineon,ir38164"; + reg = <0x49>; /* i2c addr 0x19 */ + }; + irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ + compatible = "infineon,irps5401"; + reg = <0x4c>; /* i2c addr 0x1c */ + }; + irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x4d>; /* i2c addr 0x1d */ + }; + ir38164_4e: regulator@4e { /* IR38164 - u185 */ + compatible = "infineon,ir38164"; + reg = <0x4e>; /* i2c addr 0x1e */ + }; + ir38164_4f: regulator@4f { /* IR38164 - u187 */ + compatible = "infineon,ir38164"; + reg = <0x4f>; /* i2c addr 0x1f */ + }; + }; + pmbus1_ina226_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME check alerts coming to SC */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; /* r440 */ + }; + vcc_soc: ina226@41 { /* u161 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; /* r2174 */ + }; + vcc_pmc: ina226@42 { /* u163 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; /* r1214 */ + }; + vcc_ram: ina226@43 { /* u5 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; /* r2108 */ + }; + vcc_pslp: ina226@44 { /* u165 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; /* r1830 */ + }; + vcc_psfp: ina226@45 { /* u164 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; /* r2086 */ + }; + }; + i2c@2 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + pmbus2_ina226_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* FIXME check alerts coming to SC */ + vccaux: ina226@40 { /* u166 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <2000>; /* r2109 */ + }; + vccaux_pmc: ina226@41 { /* u168 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; /* r1246 */ + }; + mgtavcc: ina226@42 { /* u265 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; /* r1829 */ + }; + vcc1v5: ina226@43 { /* u264 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; /* r1221 */ + }; + vcco_mio: ina226@45 { /* u172 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; /* r1219 */ + }; + mgtavtt: ina226@46 { /* u188 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <2000>; /* r1384 */ + }; + vcco_502: ina226@47 { /* u174 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; /* r1825 */ + }; + mgtvccaux: ina226@48 { /* u176 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; /* r1232 */ + }; + vcc1v1_lp4: ina226@49 { /* u186 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <2000>; /* r1367 */ + }; + vadj_fmc: ina226@4a { /* u184 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <2000>; /* r1350 */ + }; + lpdmgtyavcc: ina226@4b { /* u177 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; /* r2097 */ + }; + lpdmgtyavtt: ina226@4c { /* u260 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <2000>; /* r1834 */ + }; + lpdmgtyvccaux: ina226@4d { /* u234 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <5000>; /* r1679 */ + }; + }; + /* 4 - 7 unused */ + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@74 { /* u35 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c-mux-idle-disconnect; + /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + ref_clk_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + ref_clk: clock-generator@5d { /* u32 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <33333333>; + clock-frequency = <33333333>; + clock-output-names = "ref_clk"; + silabs,skip-recall; + }; + }; + fmcp1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* connection to Samtec J51C */ + /* expected eeprom 0x50 SE cards */ + }; + osfp_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* J362 connector */ + }; + lpddr4_si570_clk3_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + lpddr4_clk3: clock-generator@60 { /* u4 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk3"; + silabs,skip-recall; + }; + /* alternative option DNP - u305 at 0x50 */ + }; + lpddr4_si570_clk2_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + lpddr4_clk2: clock-generator@60 { /* u3 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk2"; + silabs,skip-recall; + }; + /* alternative option DNP - u303 at 0x50 */ + }; + lpddr4_si570_clk1_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + lpddr4_clk1: clock-generator@60 { /* u248 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk1"; + silabs,skip-recall; + }; + /* alternative option DNP - u301 at 0x50 */ + }; + qsfpdd_i2c: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* J1/J2/J355/J354/J359/J358 connectors */ + }; + idt8a34001_i2c: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* Via J310 connector */ + idt_8a34001: phc@5b { /* u219B */ + compatible = "idt,8a34001"; + reg = <0x5b>; + }; + }; + }; + i2c-mux@75 { /* u322 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + sfpdd1_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* J350 sfp-dd at 0x50 */ + }; + sfpdd2_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* J352 sfp-dd at 0x50 */ + }; + sfpdd3_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* J385 sfp-dd at 0x50 */ + }; + sfpdd4_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* J387 sfp-dd at 0x50 */ + }; + rc21008a_gtclk1_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + vc7_1: clock-generator@9 { + compatible = "renesas,rc21008a"; + clock-output-names = "rc21008a-0"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + /* u298 - rc21008a at 0x9 */ + /* connector J370 */ + }; + rc21008a_gtclk2_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + vc7_2: clock-generator@9 { + compatible = "renesas,rc21008a"; + clock-output-names = "rc21008a-1"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + /* u299 - rc21008a at 0x9 */ + /* connector J371 */ + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso new file mode 100644 index 0000000..e70eb4d --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VPK180 revA + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + + +&{/} { + compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-vpk180-revB", + "xlnx,zynqmp-vpk180", "xlnx,zynqmp"; + + vc7_xin: vc7-xin { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <50000000>; + }; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + tca6416_u233: gpio@20 { /* u233 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", "QSFPDD3_MODSELL", "QSFPDD4_MODSELL", /* 0 - 3 */ + "PMBUS2_INA226_ALERT", "QSFPDD5_MODSELL", "QSFPDD6_MODSELL", "", /* 4 - 7 */ + "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "UTIL_3V3_VRHOT_B", /* 10 - 13 */ + "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + pmbus_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* On connector J325 */ + ir38060_41: regulator@41 { /* IR38060 - u259 */ + compatible = "infineon,ir38060", "infineon,ir38064"; + reg = <0x41>; /* i2c addr 0x11 */ + }; + ir35221_45: pmic@45 { /* IR35221 - u291 */ + compatible = "infineon,ir35221"; + reg = <0x45>; /* i2c addr - 0x15 */ + }; + ir35221_46: pmic@46 { /* IR35221 - u152 */ + compatible = "infineon,ir35221"; + reg = <0x46>; /* i2c addr - 0x16 */ + }; + irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ + compatible = "infineon,irps5401"; + reg = <0x47>; /* i2c addr 0x17 */ + }; + irps5401_48: pmic@48 { /* IRPS5401 - u295 */ + compatible = "infineon,irps5401"; + reg = <0x48>; /* i2c addr 0x18 */ + }; + ir38164_49: regulator@49 { /* IR38164 - u189 */ + compatible = "infineon,ir38164"; + reg = <0x49>; /* i2c addr 0x19 */ + }; + irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ + compatible = "infineon,irps5401"; + reg = <0x4c>; /* i2c addr 0x1c */ + }; + irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x4d>; /* i2c addr 0x1d */ + }; + ir38164_4e: regulator@4e { /* IR38164 - u185 */ + compatible = "infineon,ir38164"; + reg = <0x4e>; /* i2c addr 0x1e */ + }; + ir38164_4f: regulator@4f { /* IR38164 - u187 */ + compatible = "infineon,ir38164"; + reg = <0x4f>; /* i2c addr 0x1f */ + }; + }; + pmbus1_ina226_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME check alerts coming to SC */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; /* r440 */ + }; + vcc_soc: ina226@41 { /* u161 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; /* r2174 */ + }; + vcc_pmc: ina226@42 { /* u163 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; /* r1214 */ + }; + vcc_ram: ina226@43 { /* u5 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; /* r2108 */ + }; + vcc_pslp: ina226@44 { /* u165 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; /* r1830 */ + }; + vcc_psfp: ina226@45 { /* u164 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; /* r2086 */ + }; + }; + i2c@2 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + pmbus2_ina226_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* FIXME check alerts coming to SC */ + vccaux: ina226@40 { /* u166 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <2000>; /* r2109 */ + }; + vccaux_pmc: ina226@41 { /* u168 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; /* r1246 */ + }; + mgtavcc: ina226@42 { /* u265 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; /* r1829 */ + }; + vcc1v5: ina226@43 { /* u264 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; /* r1221 */ + }; + vcco_mio: ina226@45 { /* u172 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; /* r1219 */ + }; + mgtavtt: ina226@46 { /* u188 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <2000>; /* r1384 */ + }; + vcco_502: ina226@47 { /* u174 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; /* r1825 */ + }; + mgtvccaux: ina226@48 { /* u176 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; /* r1232 */ + }; + vcc1v1_lp4: ina226@49 { /* u186 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <2000>; /* r1367 */ + }; + vadj_fmc: ina226@4a { /* u184 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <2000>; /* r1350 */ + }; + lpdmgtyavcc: ina226@4b { /* u177 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; /* r2097 */ + }; + lpdmgtyavtt: ina226@4c { /* u260 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <2000>; /* r1834 */ + }; + lpdmgtyvccaux: ina226@4d { /* u234 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <5000>; /* r1679 */ + }; + }; + /* 4 - 7 unused */ + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@74 { /* u35 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c-mux-idle-disconnect; + /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + fmcp1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* connection to Samtec J51C */ + /* expected eeprom 0x50 SE cards */ + }; + osfp_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* J362 connector */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* alternative option DNP - u305 at 0x50 */ + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* alternative option DNP - u303 at 0x50 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* alternative option DNP - u301 at 0x50 */ + }; + qsfpdd_i2c: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* J1/J2/J355/J354/J359/J358 connectors */ + }; + idt8a34001_i2c: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* Via J310 connector */ + idt_8a34001: phc@5b { /* u219B */ + compatible = "idt,8a34001"; + reg = <0x5b>; + }; + }; + }; + i2c-mux@75 { /* u322 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + sfpdd1_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* J350 sfp-dd at 0x50 */ + }; + sfpdd2_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* J352 sfp-dd at 0x50 */ + }; + sfpdd3_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* J385 sfp-dd at 0x50 */ + }; + sfpdd4_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* J387 sfp-dd at 0x50 */ + }; + rc21008a_gtclk1_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + vc7_1: clock-generator@9 { + compatible = "renesas,rc21008a"; + clock-output-names = "rc21008a-0"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + /* u298 - rc21008a at 0x9 */ + /* connector J370 */ + }; + rc21008a_gtclk2_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + vc7_2: clock-generator@9 { + compatible = "renesas,rc21008a"; + clock-output-names = "rc21008a-1"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + /* u299 - rc21008a at 0x9 */ + /* connector J371 */ + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso new file mode 100644 index 0000000..5a5c1ef --- /dev/null +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KD240 revA Carrier Card + * + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sk-kd240-rev1", + "xlnx,zynqmp-sk-kd240-revB", + "xlnx,zynqmp-sk-kd240-revA", + "xlnx,zynqmp-sk-kd240", "xlnx,zynqmp"; + model = "ZynqMP KD240 revA/B/1"; + + ina260-u3 { + compatible = "iio-hwmon"; + io-channels = <&u3 0>, <&u3 1>, <&u3 2>; + }; + + clk_26: clock2 { /* u17 - USB */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; +}; + +&can0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + u3: ina260@40 { /* u3 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + + slg7xl45106: gpio@11 { /* u13 - reset logic */ + compatible = "dlg,slg7xl45106"; + reg = <0x11>; + label = "resetchip"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB0_PHY_RESET_B", "", + "SD_RESET_B", "USB0_HUB_RESET_B", + "", "PS_GEM0_RESET_B", + "", ""; + }; + + /* usb5744@2d */ +}; + +/* USB 3.0 */ +&psgtr { + status = "okay"; + /* usb */ + clocks = <&clk_26>; + clock-names = "ref2"; +}; + +&usb0 { /* mio52 - mio63 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; + + usbhub0: usb-hub { /* u36 */ + i2c-bus = <&i2c1>; + compatible = "microchip,usb5744"; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + usb2244: usb-sd { /* u41 */ + compatible = "microchip,usb2244"; + reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; + }; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; +}; + +&gem1 { /* mdio mio50/51 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem1_default>; + assigned-clock-rates = <250000000>; + + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@8 { /* Adin u31 */ + reg = <8>; + adi,rx-internal-delay-ps = <2000>; + adi,tx-internal-delay-ps = <2000>; + adi,fifo-depth-bits = <8>; + reset-assert-us = <10>; + reset-deassert-us = <5000>; + reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* 2 more ethernet phys u32@2 and u34@3 */ + +&pinctrl0 { /* required by spec */ + status = "okay"; + + pinctrl_can0_default: can0-default { + mux { + function = "can0"; + groups = "can0_16_grp"; + }; + + conf { + groups = "can0_16_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO66"; + bias-pull-up; + }; + + conf-tx { + pins = "MIO67"; + bias-pull-up; + drive-strength = <4>; + }; + }; + + pinctrl_uart0_default: uart0-default { + conf { + groups = "uart0_17_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO70"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO71"; + bias-disable; + }; + + mux { + groups = "uart0_17_grp"; + function = "uart0"; + }; + }; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + output-enable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups = "ethernet1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO45", "MIO46", "MIO47", "MIO48"; + bias-disable; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO44", "MIO49"; + bias-disable; + output-enable; + low-power-disable; + }; + + conf-tx { + pins = "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + output-enable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + bias-disable; + output-enable; + }; + + mux-mdio { + function = "mdio1"; + groups = "mdio1_0_grp"; + }; + + mux { + function = "ethernet1"; + groups = "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = <SLEW_RATE_FAST>; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = <SLEW_RATE_SLOW>; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups = "usb1_0_grp"; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = <SLEW_RATE_FAST>; + }; + + conf-tx { + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = <SLEW_RATE_SLOW>; + }; + + mux { + groups = "usb1_0_grp"; + function = "usb1"; + }; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; + assigned-clock-rates = <100000000>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 55bef1d..22e7d68 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -2,12 +2,13 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * SD level shifter: - * "A" – A01 board un-modified (NXP) - * "Y" – A01 board modified with legacy interposer (Nexperia) - * "Z" – A01 board modified with Diode interposer + * "A" - A01 board un-modified (NXP) + * "Y" - A01 board modified with legacy interposer (Nexperia) + * "Z" - A01 board modified with Diode interposer * * Michal Simek <michal.simek@amd.com> */ @@ -156,7 +157,7 @@ disable-wp; xlnx,mio-bank = <1>; assigned-clock-rates = <187498123>; - bus-width = <8>; + bus-width = <4>; }; &gem3 { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 1b1d9e7..eadc256 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -2,7 +2,8 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -144,7 +145,7 @@ clk-phase-uhs-sdr25 = <120>, <60>; clk-phase-uhs-ddr50 = <126>, <48>; assigned-clock-rates = <187498123>; - bus-width = <8>; + bus-width = <4>; }; &gem3 { diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 80b9fac..1d62c48 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -145,8 +145,6 @@ status = "okay"; spi_flash: flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; @@ -235,9 +233,9 @@ label = "Secure OS Storage"; reg = <0x2280000 0x20000>; /* 128KB */ }; - partition@22A0000 { + partition@22a0000 { label = "User"; - reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ + reg = <0x22a0000 0x1d60000>; /* 29.375 MB */ }; }; }; diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts index 3750bb3..0d96c6f 100644 --- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts +++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts @@ -56,7 +56,6 @@ &qspi { status = "okay"; - is-dual = <1>; flash@0 { compatible = "st,m25p80", "n25q256a", "jedec,spi-nor"; m25p,fast-read; @@ -66,7 +65,6 @@ spi-max-frequency = <166000000>; #address-cells = <1>; #size-cells = <1>; - is-dual = <1>; partition@0 { label = "qspi-boot-bin"; reg = <0x00000 0x60000>; diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts new file mode 100644 index 0000000..2f88aa4 --- /dev/null +++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP System Controller on vp-x-a2785-00 board RevA"; + compatible = "xlnx,zynqmp-vp-x-a2785-00-revA", + "xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + usb1 = &usb1; + nvmem0 = &eeprom; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + j383 { + label = "j383"; + gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; + linux,code = <BTN_MISC>; + wakeup-source; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat-led { /* ds52 */ + label = "heartbeat"; + gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + si5332_0: si5332_0 { /* ps_ref_clk - u142 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33333333>; + }; + + si5332_1: si5332_1 { /* clk0_sgmii - u142 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33333333>; /* FIXME */ + }; + + si5332_2: si5332_2 { /* clk1_usb - u142 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; +}; + +&qspi { /* MIO 0-5 */ + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-tx-bus-width = <4>; /* maybe 4 here */ + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + partition@0 { /* for testing purpose */ + label = "qspi"; + reg = <0 0x4000000>; + }; + }; +}; + +&sdhci1 { /* sd MIO 45-51 */ + status = "okay"; + no-1-8-v; + disable-wp; + xlnx,mio-bank = <1>; +}; + +&uart0 { /* uart0 MIO38-39 */ + status = "okay"; + bootph-all; +}; + +&gem0 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "sgmii"; /* DTG generates this properly 1512 */ + is-internal-pcspma; + /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ + /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { /* u131 - M88e1512 */ + reg = <0>; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ + "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ + "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */ + "", "", "", "", "", /* 15 - 19 */ + "", "", "", "", "", /* 20 - 24 */ + "", "", "", "", "", /* 25 - 29 */ + "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ + "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ + "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ + "SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ + "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ + "", "", "", "", "", /* 65 - 69 */ + "", "", "", "", "", /* 70 - 74 */ + "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ + "", "", /* 78 - 79 */ + "", "", "", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 - 89 */ + "", "", "", "", "", /* 90 - 94 */ + "", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 173 */ +}; + +&i2c0 { /* MIO 34-35 - can't stay here */ + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ + "", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ + "", "", "", "VCCINT_FAULT_B", /* 10 - 13 */ + "VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + pmbus_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* On connector J325 */ + reg_vccint: tps53681@60 { /* u266 - 0xc0 */ + compatible = "ti,tps53681", "ti,tps53679"; + reg = <0x60>; + }; + reg_vcc1v1_lp4: tps544@d { /* u85 */ + compatible = "ti,tps544b25"; + reg = <0xd>; + }; + reg_mgtyavcc: tps544@10 { /* u274 */ + compatible = "ti,tps544b25"; + reg = <0x10>; + }; + reg_mgtyavtt: tps544@11 { /* u275 */ + compatible = "ti,tps544b25"; + reg = <0x11>; + }; + reg_vccaux: tps544@12 { /* u276 */ + compatible = "ti,tps544b25"; + reg = <0x12>; + }; + reg_vcc_cpm: tps544@14 { /* u272 */ + compatible = "ti,tps544b25"; + reg = <0x14>; + }; + reg_util_3v3: tps544@1d { /* u278 */ + compatible = "ti,tps544b25"; + reg = <0x1d>; + }; + }; + pmbus1_ina226_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME check alerts coming to SC */ + vcc_cpm: ina226@44 { /* u273 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + }; + i2c@2 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + pcie_smbus: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + pcie2_smbus: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + i2c@5 { /* NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + user_si570: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + /* 7 unused */ + }; +}; + +&i2c1 { /* i2c1 MIO 36-37 */ + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + i2c-mux@74 { /* u35 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + dc_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* Use for storing information about SC board */ + eeprom: eeprom@54 { /* u34 - m24128 16kB */ + compatible = "st,24c128", "atmel,24c128"; + reg = <0x54>; /* & 0x5c */ + }; + si570_ref_clk: clock-generator@5d { /* u32 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <33333333>; + clock-frequency = <33333333>; + clock-output-names = "ref_clk"; + silabs,skip-recall; + }; + }; + i2c@1 { /* NC - FIXME */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c@2 { /* NC - FIXME */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + i2c@3 { /* NC - FIXME */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + lpddr4_si570_clk2_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + lpddr4_clk2: clock-generator@60 { /* u3 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk2"; + }; + }; + lpddr4_si570_clk1_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + lpddr4_clk1: clock-generator@60 { /* u248 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk1"; + }; + }; + /* 6-7 unused */ + }; +}; + +&usb0 { /* MIO52 - MIO63 */ + status = "okay"; + phy-names = "usb3-phy"; + phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; +}; + +&psgtr { + status = "okay"; + /* sgmii, usb3 */ + clocks = <&si5332_1>, <&si5332_2>; + clock-names = "ref0", "ref1"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + maximum-speed = "super-speed"; +}; + +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + +&pinctrl0 { + status = "okay"; + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_8_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_8_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_34_grp", "gpio0_35_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_34_grp", "gpio0_35_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_9_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_9_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_36_grp", "gpio0_37_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_36_grp", "gpio0_37_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts new file mode 100644 index 0000000..66919f5 --- /dev/null +++ b/arch/arm/dts/zynqmp-vpk120-revA.dts @@ -0,0 +1,574 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VPK120 RevA System Controller + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP System Controller on VPK120 board RevA"; + compatible = "xlnx,zynqmp-vpk120-revA", + "xlnx,zynqmp-vpk120", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + usb1 = &usb1; + nvmem0 = &eeprom; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + sw16 { + label = "sw16"; + gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; + linux,code = <BTN_MISC>; + wakeup-source; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat-led { /* ds40 */ + label = "heartbeat"; + gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + si5332_0: si5332_0 { /* ps_ref_clk */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33333333>; + }; + + si5332_1: si5332_1 { /* clk0_sgmii */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33333333>; /* FIXME */ + }; + + si5332_2: si5332_2 { /* clk1_usb */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; +}; + +&qspi { /* MIO 0-5 */ + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + partition@0 { /* for testing purpose */ + label = "qspi"; + reg = <0 0x4000000>; + }; + }; +}; + +&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ + status = "okay"; + non-removable; + disable-wp; + bus-width = <8>; + xlnx,mio-bank = <0>; +}; + +&uart0 { /* uart0 MIO38-39 */ + status = "okay"; + bootph-all; +}; + +&gem0 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "sgmii"; /* DTG generates this properly 1512 */ + is-internal-pcspma; + /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ + /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ + "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ + "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ + "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ + "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ + "", "", "", "", "", /* 25 - 29 */ + "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ + "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ + "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ + "", "", "", "", "", /* 45 - 49 */ + "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ + "", "", "", "", "", /* 65 - 69 */ + "", "", "", "", "", /* 70 - 74 */ + "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ + "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ + "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ + "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ + "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ + "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 173 */ +}; + +&i2c0 { /* MIO 34-35 - can't stay here */ + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */ + "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ + "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ + "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + pmbus_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* On connector J325 */ + ir38060_41: regulator@41 { /* IR38060 - u259 */ + compatible = "infineon,ir38060", "infineon,ir38064"; + reg = <0x41>; /* i2c addr 0x11 */ + }; + ir38164_43: regulator@43 { /* IR38164 - u13 */ + compatible = "infineon,ir38164"; + reg = <0x43>; /* i2c addr 0x13 */ + }; + ir35221_45: pmic@46 { /* IR35221 - u152 */ + compatible = "infineon,ir35221"; + reg = <0x46>; /* PMBUS - 0x16 */ + }; + irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ + compatible = "infineon,irps5401"; + reg = <0x47>; /* i2c addr 0x17 */ + }; + ir38164_49: regulator@49 { /* IR38164 - u189 */ + compatible = "infineon,ir38164"; + reg = <0x49>; /* i2c addr 0x19 */ + }; + irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ + compatible = "infineon,irps5401"; + reg = <0x4c>; /* i2c addr 0x1c */ + }; + irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x4d>; /* i2c addr 0x1c */ + }; + ir38164_4e: regulator@4e { /* IR38164 - u184 */ + compatible = "infineon,ir38164"; + reg = <0x4e>; /* i2c addr 0x1e */ + }; + ir38164_4f: regulator@4f { /* IR38164 - u187 */ + compatible = "infineon,ir38164"; + reg = <0x4f>; /* i2c addr 0x1f */ + }; + }; + pmbus1_ina226_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME check alerts coming to SC */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + vcc_soc: ina226@41 { /* u161 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + vcc_pmc: ina226@42 { /* u163 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + vcc_ram: ina226@43 { /* u5 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vcc_pslp: ina226@44 { /* u165 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + vcc_psfp: ina226@45 { /* u164 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + }; + i2c@2 { /* NC */ /* FIXME maybe remove */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + pmbus2_ina226_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* FIXME check alerts coming to SC */ + vccaux: ina226@40 { /* u166 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + vccaux_pmc: ina226@41 { /* u168 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + mgtavcc: ina226@42 { /* u265 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + vcc1v5: ina226@43 { /* u264 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vcco_mio: ina226@45 { /* u172 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + mgtavtt: ina226@46 { /* u188 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <2000>; + }; + vcco_502: ina226@47 { /* u174 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + mgtvccaux: ina226@48 { /* u176 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + vcc1v1_lp4: ina226@49 { /* u186 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <2000>; + }; + vadj_fmc: ina226@4a { /* u184 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <2000>; + }; + lpdmgtyavcc: ina226@4b { /* u177 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + lpdmgtyavtt: ina226@4c { /* u260 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <2000>; + }; + lpdmgtyvccaux: ina226@4d { /* u234 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <5000>; + }; + }; + i2c@4 { /* NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + i2c@5 { /* NC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + user_si570: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5f>; + temperature-stability = <50>; + factory-fout = <100000000>; + clock-frequency = <100000000>; + clock-output-names = "fmc_si570"; + }; + + }; + /* 7 unused */ + }; +}; + +&i2c1 { /* i2c1 MIO 36-37 */ + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + i2c-mux@74 { /* u35 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + ref_clk_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* Use for storing information about SC board */ + eeprom: eeprom@54 { /* u34 - m24128 16kB */ + compatible = "st,24c128", "atmel,24c128"; + reg = <0x54>; /* & 0x5c */ + }; + ref_clk: clock-generator@5d { /* u32 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <33333333>; + clock-frequency = <33333333>; + clock-output-names = "ref_clk"; + silabs,skip-recall; + }; + }; + fmcp1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME connection to Samtec J51C */ + /* expected eeprom 0x50 SE cards */ + }; + i2c@2 { /* NC - FIXME */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + lpddr4_si570_clk3_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + lpddr4_clk3: clock-generator@60 { /* u4 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk3"; + }; + }; + lpddr4_si570_clk2_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + lpddr4_clk2: clock-generator@60 { /* u3 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk2"; + }; + }; + lpddr4_si570_clk1_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + lpddr4_clk1: clock-generator@60 { /* u248 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; + temperature-stability = <50>; + factory-fout = <200000000>; + clock-frequency = <200000000>; + clock-output-names = "lpddr4_clk1"; + }; + }; + qsfpdd_i2c: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* J1/J2 connectors */ + }; + idt8a34001_i2c: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* Via J310 connector */ + idt_8a34001: phc@5b { + compatible = "idt,8a34001"; /* u219B */ + reg = <0x5b>; /* FIXME not in schematics */ + }; + }; + }; +}; + +&usb0 { /* MIO52 - MIO63 */ + status = "okay"; + phy-names = "usb3-phy"; + phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; +}; + +&psgtr { + status = "okay"; + /* sgmii, usb3 */ + clocks = <&si5332_1>, <&si5332_2>; + clock-names = "ref0", "ref1"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + maximum-speed = "super-speed"; +}; + +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + +&pinctrl0 { + status = "okay"; + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_8_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_8_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_34_grp", "gpio0_35_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_34_grp", "gpio0_35_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_9_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_9_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_36_grp", "gpio0_37_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_36_grp", "gpio0_37_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index 5c4acd17..cb9ef37 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -2,10 +2,10 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@amd.com> - * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index cffad44..e72ed50 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -97,8 +98,12 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; @@ -349,11 +354,13 @@ &qspi { status = "okay"; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index bb04778..23a3ff2 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -90,12 +91,16 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; - phy0: ethernet-phy@5 { - reg = <5>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@5 { + reg = <5>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index 69ad580..b97f7ee 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -88,8 +88,12 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: ethernet-phy@0 { /* VSC8211 */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { /* VSC8211 */ + reg = <0>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 3017c9b..2b66abc 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -116,17 +116,21 @@ status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; - ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ - reg = <0>; - }; - ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ - reg = <7>; - }; - ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ - reg = <3>; - }; - ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ - reg = <8>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ + reg = <0>; + }; + ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ + reg = <7>; + }; + ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ + reg = <3>; + }; + ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ + reg = <8>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 74a5b02..b1857e1 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> * Michal Simek <michal.simek@amd.com> */ @@ -77,8 +77,12 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem1_default>; - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index a84cd86..44d1b24 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> * Nathalie Chan King Choy @@ -131,13 +132,13 @@ io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; - si5335_0: si5335_0 { /* clk0_usb - u23 */ + si5335_0: si5335-0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; - si5335_1: si5335_1 { /* clk1_dp - u23 */ + si5335_1: si5335-1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts index c0a4d91..c8f71a1 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016 - 2018, Xilinx, Inc. * * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 0f7230b..e166c95 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -970,12 +971,13 @@ &qspi { status = "okay"; - is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index ce0a6e5..3c28130 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 90fbfca..cdfeea2 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 69470f8..4b942ac 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -1,8 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index f8019c5..b90ff61 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -150,6 +151,18 @@ #clock-cells = <0>; clock-frequency = <114285000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &can1 { @@ -965,12 +978,13 @@ &qspi { status = "okay"; - is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ @@ -1065,4 +1079,12 @@ phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 3>, <&psgtr 0 PHY_TYPE_DP 1 3>; + + ports { + port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; + }; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index c9ff99f..ba9e489 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -788,12 +789,13 @@ &qspi { status = "okay"; - is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index 9404c13..095c972 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -5,7 +5,7 @@ * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@amd.com> - * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index c06d262..4060dc3 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -5,7 +5,7 @@ * (C) Copyright 2018 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@amd.com> - * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index 99ea143..4f85837 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -5,7 +5,7 @@ * (C) Copyright 2018 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@amd.com> - * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 0c1f509..22ad8d3 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -57,7 +57,7 @@ leds { compatible = "gpio-leds"; - heartbeat_led { + heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -643,12 +643,13 @@ &qspi { status = "okay"; - is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; - reg = <0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 8ca01f0..575ff5b 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -57,7 +57,7 @@ leds { compatible = "gpio-leds"; - heartbeat_led { + heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -653,12 +653,13 @@ &qspi { status = "okay"; - is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts new file mode 100644 index 0000000..edbbf0b --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu670-revA.dts @@ -0,0 +1,669 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP ZCU670 (67DR) + * + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP ZCU670 RevA"; + compatible = "xlnx,zynqmp-zcu670-revA", "xlnx,zynqmp-zcu670", + "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + nvmem0 = &eeprom; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0 0 0x80000000>, <0x8 0x0 0x0 0x80000000>; + /* Another 4GB connected to PL */ + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + sw1 { + label = "sw1"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = <BTN_MISC>; + wakeup-source; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat-led { + label = "heartbeat"; /* DS1 */ + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + ina226-vccint { + compatible = "iio-hwmon"; + io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; + }; + ina226-vccint-io-bram-ps { + compatible = "iio-hwmon"; + io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; + }; + ina226-vcc1v8 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; + }; + ina226-vcc1v2 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; + }; + ina226-vadj-fmc { + compatible = "iio-hwmon"; + io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; + }; + ina226-mgtavcc { + compatible = "iio-hwmon"; + io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; + }; + ina226-mgt1v2 { + compatible = "iio-hwmon"; + io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; + }; + ina226-mgt1v8 { + compatible = "iio-hwmon"; + io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; + }; + ina226-vccint-ams { + compatible = "iio-hwmon"; + io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; + }; + ina226-dac-avtt { + compatible = "iio-hwmon"; + io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; + }; + ina226-dac-avccaux { + compatible = "iio-hwmon"; + io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; + }; + ina226-adc-avcc { + compatible = "iio-hwmon"; + io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; + }; + ina226-adc-avccaux { + compatible = "iio-hwmon"; + io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; + }; + ina226-dac-avcc { + compatible = "iio-hwmon"; + io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; + }; + + /* 48MHz reference crystal */ + ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + si5381_6: si5381_6 { /* refclk_usb3 - u43 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ + "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ + "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ + "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ + "", "", "BUTTON", "LED", "", /* 20 - 24 */ + "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ + "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ + "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ + "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ + "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ + "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ + "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ + "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ + "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ + "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ + "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ + "", "", /* 78 - 79 */ + "", "", "", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 - 89 */ + "", "", "", "", "", /* 90 - 94 */ + "", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 173 */ +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + tca6416_u15: gpio@20 { /* u15 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ + "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ + "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ + "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@75 { /* u17 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + /* PMBUS_ALERT done via pca9544 */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + vccint_io_bram_ps: ina226@41 { /* u57 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint-io-bram-ps"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + vcc1v8: ina226@42 { /* u60 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v8"; + reg = <0x42>; + shunt-resistor = <2000>; + }; + vcc1v2: ina226@43 { /* u58 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v2"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vadj_fmc: ina226@45 { /* u62 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vadj-fmc"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + mgtavcc: ina226@46 { /* u67 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgtavcc"; + reg = <0x46>; + shunt-resistor = <2000>; + }; + mgt1v2: ina226@47 { /* u63 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgt1v2"; + reg = <0x47>; + shunt-resistor = <5000>; /* Not in schematics */ + }; + mgt1v8: ina226@48 { /* u64 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgt1v8"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + vccint_ams: ina226@49 { /* u61 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint-ams"; + reg = <0x49>; + shunt-resistor = <5000>; + }; + dac_avtt: ina226@4a { /* u59 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avtt"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + dac_avccaux: ina226@4b { /* u124 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avccaux"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + adc_avcc: ina226@4c { /* u75 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-adc-avcc"; + reg = <0x4c>; + shunt-resistor = <5000>; + }; + adc_avccaux: ina226@4d { /* u71 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-adc-avccaux"; + reg = <0x4d>; + shunt-resistor = <5000>; + }; + dac_avcc: ina226@4e { /* u77 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avcc"; + reg = <0x4e>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* NC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* u104 - ir35215 0x10/0x40 */ + /* u127 - ir38164 0x1b/0x4b */ + /* u112 - ir38164 0x13/0x43 */ + /* u123 - ir38164 0x1c/0x4c */ + + irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ + compatible = "infineon,irps5401"; + reg = <0x44>; /* i2c addr 0x14 */ + }; + irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ + compatible = "infineon,irps5401"; + reg = <0x45>; /* i2c addr 0x15 */ + }; + /* J21 header too */ + + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* SYSMON */ + }; + }; + /* u38 MPS430 */ +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + i2c-mux@74 { + compatible = "nxp,pca9548"; /* u20 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c_eeprom: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u21 */ + compatible = "atmel,24c128"; + reg = <0x54>; + }; + }; + i2c_si5381: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* SI5381 - u43 */ + /* si5381: clock-generator@68 { + reg = <0x68>; + };*/ + }; + i2c_si570_user_c0: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + clock-output-names = "si570_user_c0"; + }; + }; + i2c_si570_mgt: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <156250000>; + clock-frequency = <156250000>; + clock-output-names = "si570_mgt"; + }; + }; + i2c_8a34001: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* U409B - 8a34001 */ + }; + i2c_clk104: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* CLK104_SDA */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* RFMCP connector */ + }; + /* 7 NC */ + }; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u22 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* FMCP_HSPC_IIC */ + }; + i2c_si570_psrefclk: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <33333333>; + clock-frequency = <33333333>; + clock-output-names = "si570_ps_ref_clk"; + silabs,skip-recall; + }; + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SFP3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SFP2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SFP1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SFP0 */ + }; + }; + /* u38 MPS430 */ +}; + +&pinctrl0 { + status = "okay"; + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_3_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_3_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_14_grp", "gpio0_15_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_14_grp", "gpio0_15_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_4_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_4_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_16_grp", "gpio0_17_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_16_grp", "gpio0_17_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; +}; + +&qspi { + status = "okay"; + num-cs = <2>; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + +&rtc { + status = "okay"; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + disable-wp; + /* + * This property should be removed for supporting UHS mode + */ + no-1-8-v; + xlnx,mio-bank = <1>; +}; + +&psgtr { + status = "okay"; + /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ + clocks = <&si5381_6>; + clock-names = "ref2"; +}; + +&uart0 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; +}; diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts new file mode 100644 index 0000000..97599c5 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu670-revB.dts @@ -0,0 +1,672 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP ZCU670 (67DR) revB + * + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP ZCU670 RevB"; + compatible = "xlnx,zynqmp-zcu670-revB", "xlnx,zynqmp-zcu670", + "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + nvmem0 = &eeprom; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0 0 0 0x80000000>, <0x8 0x0 0x0 0x80000000>; + /* Another 4GB connected to PL */ + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + sw1 { + label = "sw1"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = <BTN_MISC>; + wakeup-source; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat-led { + label = "heartbeat"; /* DS1 */ + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + ina226-vccint { + compatible = "iio-hwmon"; + io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; + }; + ina226-vccint-io-bram-ps { + compatible = "iio-hwmon"; + io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; + }; + ina226-vcc1v8 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; + }; + ina226-vcc1v2 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; + }; + ina226-vadj-fmc { + compatible = "iio-hwmon"; + io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; + }; + ina226-mgtavcc { + compatible = "iio-hwmon"; + io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; + }; + ina226-mgt1v2 { + compatible = "iio-hwmon"; + io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; + }; + ina226-mgt1v8 { + compatible = "iio-hwmon"; + io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; + }; + ina226-vccint-ams { + compatible = "iio-hwmon"; + io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; + }; + ina226-dac-avtt { + compatible = "iio-hwmon"; + io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; + }; + ina226-dac-avccaux { + compatible = "iio-hwmon"; + io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; + }; + ina226-adc-avcc { + compatible = "iio-hwmon"; + io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; + }; + ina226-adc-avccaux { + compatible = "iio-hwmon"; + io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; + }; + ina226-dac-avcc { + compatible = "iio-hwmon"; + io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; + }; + + /* 48MHz reference crystal */ + ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + si5381_6: si5381_6 { /* refclk_usb3 - u43 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ + "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ + "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ + "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ + "", "", "BUTTON", "LED", "", /* 20 - 24 */ + "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ + "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ + "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ + "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ + "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ + "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ + "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ + "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ + "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ + "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ + "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ + "", "", /* 78 - 79 */ + "", "", "", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 - 89 */ + "", "", "", "", "", /* 90 - 94 */ + "", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 173 */ +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + tca6416_u15: gpio@20 { /* u15 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ + "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ + "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ + "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@75 { /* u17 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + /* PMBUS_ALERT done via pca9544 */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + vccint_io_bram_ps: ina226@41 { /* u57 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint-io-bram-ps"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + vcc1v8: ina226@42 { /* u60 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v8"; + reg = <0x42>; + shunt-resistor = <2000>; + }; + vcc1v2: ina226@43 { /* u58 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v2"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vadj_fmc: ina226@45 { /* u62 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vadj-fmc"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + mgtavcc: ina226@46 { /* u67 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgtavcc"; + reg = <0x46>; + shunt-resistor = <2000>; + }; + mgt1v2: ina226@47 { /* u63 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgt1v2"; + reg = <0x47>; + shunt-resistor = <5000>; /* Not in schematics */ + }; + mgt1v8: ina226@48 { /* u64 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgt1v8"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + vccint_ams: ina226@49 { /* u61 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint-ams"; + reg = <0x49>; + shunt-resistor = <5000>; + }; + dac_avtt: ina226@4a { /* u59 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avtt"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + dac_avccaux: ina226@4b { /* u124 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avccaux"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + adc_avcc: ina226@4c { /* u75 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-adc-avcc"; + reg = <0x4c>; + shunt-resistor = <5000>; + }; + adc_avccaux: ina226@4d { /* u71 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-adc-avccaux"; + reg = <0x4d>; + shunt-resistor = <5000>; + }; + dac_avcc: ina226@4e { /* u77 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avcc"; + reg = <0x4e>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* NC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* u104 - ir35215 0x10/0x40 */ + /* u127 - ir38164 0x1b/0x4b */ + /* u112 - ir38164 0x13/0x43 */ + /* u123 - ir38164 0x1c/0x4c */ + + irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ + compatible = "infineon,irps5401"; + reg = <0x44>; /* i2c addr 0x14 */ + }; + irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ + compatible = "infineon,irps5401"; + reg = <0x45>; /* i2c addr 0x15 */ + }; + /* J21 header too */ + + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* SYSMON */ + }; + }; + /* u38 MPS430 */ +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + i2c-mux@74 { + compatible = "nxp,pca9548"; /* u20 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c_eeprom: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u21 */ + compatible = "atmel,24c128"; + reg = <0x54>; + }; + }; + i2c_si5381: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* SI5381 - u43 */ + /* si5381: clock-generator@68 { + reg = <0x68>; + };*/ + }; + i2c_si570_user_c0: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + clock-output-names = "si570_user_c0"; + }; + }; + i2c_si570_mgt: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <156250000>; + clock-frequency = <156250000>; + clock-output-names = "si570_mgt"; + }; + }; + i2c_8a34001: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* U409B - 8a34001 */ + }; + i2c_clk104: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* CLK104_SDA */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* RFMCP connector */ + }; + /* 7 NC */ + }; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u22 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* FMCP_HSPC_IIC */ + }; + i2c_si570_psrefclk: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <33333333>; + clock-frequency = <33333333>; + clock-output-names = "si570_ps_ref_clk"; + silabs,skip-recall; + }; + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SFP3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SFP2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SFP1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SFP0 */ + }; + }; + /* u38 MPS430 */ +}; + +&pinctrl0 { + status = "okay"; + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_3_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_3_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_14_grp", "gpio0_15_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_14_grp", "gpio0_15_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_4_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_4_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_16_grp", "gpio0_17_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_16_grp", "gpio0_17_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + }; +}; + +&qspi { + status = "okay"; + num-cs = <2>; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + +&rtc { + status = "okay"; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + disable-wp; + /* + * This property should be removed for supporting UHS mode + */ + no-1-8-v; + xlnx,mio-bank = <1>; + clk-phase-sd-hs = <120>, <60>; + clk-phase-uhs-sdr25 = <132>, <60>; + clk-phase-uhs-ddr50 = <153>, <48>; +}; + +&psgtr { + status = "okay"; + /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ + clocks = <&si5381_6>; + clock-names = "ref2"; +}; + +&uart0 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; +}; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 79c5af2..f03c201 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -14,6 +14,8 @@ #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> @@ -118,11 +120,27 @@ }; }; - zynqmp_ipi: zynqmp_ipi { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rproc_0_fw_image: memory@3ed00000 { + no-map; + reg = <0x0 0x3ed00000 0x0 0x40000>; + }; + + rproc_1_fw_image: memory@3ef00000 { + no-map; + reg = <0x0 0x3ef00000 0x0 0x40000>; + }; + }; + + zynqmp_ipi: zynqmp-ipi { bootph-all; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; @@ -152,10 +170,10 @@ pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; - interrupts = <0 143 4>, - <0 144 4>, - <0 145 4>, - <0 146 4>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, @@ -183,17 +201,17 @@ bootph-all; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; - nvmem_firmware { + nvmem-firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; - soc_revision: soc_revision@0 { + soc_revision: soc-revision@0 { reg = <0x0 0x4>; }; }; @@ -227,10 +245,10 @@ timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; edac { @@ -246,6 +264,23 @@ power-domains = <&zynqmp_firmware PD_PL>; }; + remoteproc { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <1>; + + r5f-0 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware PD_RPU_0>; + memory-region = <&rproc_0_fw_image>; + }; + + r5f-1 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware PD_RPU_1>; + memory-region = <&rproc_1_fw_image>; + }; + }; + amba: axi { compatible = "simple-bus"; bootph-all; @@ -258,7 +293,7 @@ status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; - interrupts = <0 23 4>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; @@ -271,7 +306,7 @@ status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; - interrupts = <0 24 4>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; @@ -291,11 +326,11 @@ compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; - interrupts = <0 123 4>, - <0 123 4>, - <0 123 4>, - <0 123 4>, - <0 123 4>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -305,7 +340,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 124 4>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -318,7 +353,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 125 4>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -331,7 +366,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 126 4>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -344,7 +379,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 127 4>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -357,7 +392,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 128 4>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -370,7 +405,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 129 4>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -383,7 +418,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 130 4>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -396,7 +431,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 131 4>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -413,7 +448,7 @@ <0x0 0xf9060000 0x0 0x20000>; interrupt-controller; interrupt-parent = <&gic>; - interrupts = <1 9 0xf04>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; gpu: gpu@fd4b0000 { @@ -421,7 +456,12 @@ compatible = "xlnx,zynqmp-mali", "arm,mali-400"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; - interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; clock-names = "bus", "core"; power-domains = <&zynqmp_firmware PD_GPU>; @@ -436,7 +476,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 77 4>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -449,7 +489,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 78 4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -462,7 +502,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 79 4>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -475,7 +515,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 80 4>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -488,7 +528,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 81 4>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -501,7 +541,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 82 4>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -514,7 +554,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 83 4>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -527,7 +567,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 84 4>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -539,7 +579,7 @@ compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; - interrupts = <0 112 4>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; }; nand0: nand-controller@ff100000 { @@ -548,7 +588,7 @@ reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; interrupt-parent = <&gic>; - interrupts = <0 14 4>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x872>; @@ -559,11 +599,10 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 57 4>, <0 57 4>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; @@ -574,11 +613,10 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 59 4>, <0 59 4>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; @@ -589,11 +627,10 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 61 4>, <0 61 4>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; @@ -604,11 +641,10 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 63 4>, <0 63 4>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; @@ -621,7 +657,7 @@ #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; - interrupts = <0 16 4>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; @@ -632,7 +668,7 @@ compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 17 4>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <400000>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; @@ -644,7 +680,7 @@ compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 18 4>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <400000>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; @@ -668,11 +704,11 @@ msi-controller; device_type = "pci"; interrupt-parent = <&gic>; - interrupts = <0 118 4>, - <0 117 4>, - <0 116 4>, - <0 115 4>, /* MSI_1 [63...32] */ - <0 114 4>; /* MSI_0 [31...0] */ + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, /* MSI_1 [63...32] */ + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; @@ -702,7 +738,7 @@ compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; - interrupts = <0 15 4>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, @@ -727,7 +763,8 @@ status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 26 4>, <0 27 4>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "alarm", "sec"; calibration = <0x7FFF>; }; @@ -737,7 +774,7 @@ status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; - interrupts = <0 133 4>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, @@ -750,7 +787,7 @@ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 48 4>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x870>; @@ -765,7 +802,7 @@ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 49 4>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x871>; @@ -782,18 +819,30 @@ status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; - interrupts = <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 19 4>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; @@ -805,7 +854,7 @@ compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 20 4>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; @@ -817,7 +866,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 36 4>, <0 37 4>, <0 38 4>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_0>; @@ -827,7 +878,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 39 4>, <0 40 4>, <0 41 4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_1>; @@ -837,7 +890,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 42 4>, <0 43 4>, <0 44 4>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_2>; @@ -847,7 +902,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 45 4>, <0 46 4>, <0 47 4>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_3>; @@ -858,7 +915,7 @@ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 21 4>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; @@ -869,7 +926,7 @@ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 22 4>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; @@ -896,7 +953,9 @@ reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; - interrupts = <0 65 4>, <0 69 4>, <0 75 4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; @@ -927,7 +986,9 @@ reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; - interrupts = <0 70 4>, <0 74 4>, <0 76 4>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; @@ -942,7 +1003,7 @@ compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 113 1>; + interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; @@ -952,7 +1013,7 @@ compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 52 1>; + interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; @@ -961,7 +1022,7 @@ compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 56 4>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xffa50000 0x0 0x800>; #address-cells = <1>; #size-cells = <1>; @@ -987,7 +1048,7 @@ compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; - interrupts = <0 122 4>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; @@ -1003,7 +1064,7 @@ <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf", "aud"; - interrupts = <0 119 4>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; @@ -1014,6 +1075,30 @@ <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + port@2 { + reg = <2>; + }; + port@3 { + reg = <3>; + }; + port@4 { + reg = <4>; + }; + port@5 { + reg = <5>; + }; + }; }; }; }; diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h b/arch/arm/mach-versal-net/include/mach/hardware.h index 9bddb8b..767cdd3 100644 --- a/arch/arm/mach-versal-net/include/mach/hardware.h +++ b/arch/arm/mach-versal-net/include/mach/hardware.h @@ -66,6 +66,7 @@ struct crp_regs { #define EMMC_MODE 0x00000006 #define USB_MODE 0x00000007 #define OSPI_MODE 0x00000008 +#define SELECTMAP_MODE 0x0000000A #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h index 000af97..9d1c2f0 100644 --- a/arch/arm/mach-versal/include/mach/hardware.h +++ b/arch/arm/mach-versal/include/mach/hardware.h @@ -82,6 +82,7 @@ struct crp_regs { #define EMMC_MODE 0x00000006 #define USB_MODE 0x00000007 #define OSPI_MODE 0x00000008 +#define SELECTMAP_MODE 0x0000000A #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c index 7bd3928..2487b48 100644 --- a/arch/arm/mach-versal/mp.c +++ b/arch/arm/mach-versal/mp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2019 Xilinx, Inc. - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ #include <common.h> diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index c18be0c..990ca16 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -252,6 +252,9 @@ static int boot_targets_setup(void) mode = "mmc"; bootseq = dev_seq(dev); break; + case SELECTMAP_MODE: + puts("SELECTMAP_MODE\n"); + break; case SD_MODE: puts("SD_MODE\n"); if (uclass_get_device_by_name(UCLASS_MMC, diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index e4bdd5d..8c2e614 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -174,6 +174,9 @@ static int boot_targets_setup(void) mode = "mmc"; bootseq = dev_seq(dev); break; + case SELECTMAP_MODE: + puts("SELECTMAP_MODE\n"); + break; case SD_MODE: puts("SD_MODE\n"); if (uclass_get_device_by_name(UCLASS_MMC, @@ -312,6 +315,7 @@ enum env_location env_get_location(enum env_operation op, int prio) return ENVL_SPI_FLASH; return ENVL_NOWHERE; case JTAG_MODE: + case SELECTMAP_MODE: default: return ENVL_NOWHERE; } diff --git a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c index 4510230..166e614 100644 --- a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c @@ -602,129 +602,6 @@ static unsigned long psu_peripherals_init_data(void) return 1; } -static unsigned long psu_serdes_init_data(void) -{ - psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U); - psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U); - psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); - psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U); - psu_mask_write(0xFD402868, 0x00000082U, 0x00000002U); - psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); - psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U); - psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U); - psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU); - psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U); - psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U); - psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U); - psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU); - psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U); - psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U); - psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U); - psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); - psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); - psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); - psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); - psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); - psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); - psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); - psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); - - serdes_illcalib(0, 0, 3, 0, 4, 0, 4, 0); - psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U); - psu_mask_write(0xFD410014, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U); - psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U); - psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U); - psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U); - psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U); - - return 1; -} - -static unsigned long psu_resetout_init_data(void) -{ - psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U); - psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U); - psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); - psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); - psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); - psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); - psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); - mask_poll(0xFD4063E4, 0x00000010U); - mask_poll(0xFD40A3E4, 0x00000010U); - - return 1; -} - -static unsigned long psu_resetin_init_data(void) -{ - psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU); - psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U); - psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U); - - return 1; -} - static unsigned long psu_afi_config(void) { psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index b284494..239bb1f 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -103,7 +103,7 @@ CONFIG_CMD_UBI=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_BOARD=y -CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu106-rev1.0 zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA zynqmp-dlc21-revA" +CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-e-a2197-00-revB zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu106-rev1.0 zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA zynqmp-dlc21-revA" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts iommus power-domains" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 2e004be..c473643 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -773,7 +773,6 @@ static struct clk_ops versal_clk_ops = { static const struct udevice_id versal_clk_ids[] = { { .compatible = "xlnx,versal-clk" }, - { .compatible = "xlnx,versal-net-clk" }, { } }; diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index b1f201f..2656f5f 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2015 - 2016, Xilinx, Inc, * Michal Simek <michal.simek@amd.com> - * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ #include <console.h> diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c index 1df639d..c07c780 100644 --- a/drivers/net/phy/xilinx_phy.c +++ b/drivers/net/phy/xilinx_phy.c @@ -99,7 +99,6 @@ static int xilinxphy_startup(struct phy_device *phydev) static int xilinxphy_of_init(struct phy_device *phydev) { - u32 phytype; ofnode node; debug("%s\n", __func__); @@ -107,10 +106,6 @@ static int xilinxphy_of_init(struct phy_device *phydev) if (!ofnode_valid(node)) return -EINVAL; - phytype = ofnode_read_u32_default(node, "xlnx,phy-type", -1); - if (phytype == XAE_PHY_TYPE_1000BASE_X) - phydev->flags |= XAE_PHY_TYPE_1000BASE_X; - return 0; } diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 3377e66..7c57d32 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -321,11 +321,38 @@ static int zynq_gem_setup_mac(struct udevice *dev) return 0; } +static u32 gem_mdc_clk_div(struct zynq_gem_priv *priv) +{ + u32 config; + unsigned long pclk_hz; + + pclk_hz = clk_get_rate(&priv->pclk); + if (pclk_hz <= 20000000) + config = GEM_MDC_SET(GEM_CLK_DIV8); + else if (pclk_hz <= 40000000) + config = GEM_MDC_SET(GEM_CLK_DIV16); + else if (pclk_hz <= 80000000) + config = GEM_MDC_SET(GEM_CLK_DIV32); + else if (pclk_hz <= 120000000) + config = GEM_MDC_SET(GEM_CLK_DIV48); + else if (pclk_hz <= 160000000) + config = GEM_MDC_SET(GEM_CLK_DIV64); + else if (pclk_hz <= 240000000) + config = GEM_MDC_SET(GEM_CLK_DIV96); + else if (pclk_hz <= 320000000) + config = GEM_MDC_SET(GEM_CLK_DIV128); + else + config = GEM_MDC_SET(GEM_CLK_DIV224); + + return config; +} + static int zynq_phy_init(struct udevice *dev) { - int ret; + int ret, val; struct zynq_gem_priv *priv = dev_get_priv(dev); struct zynq_gem_regs *regs_mdio = priv->mdiobase; + struct zynq_gem_regs *regs = priv->iobase; const u32 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | @@ -333,6 +360,10 @@ static int zynq_phy_init(struct udevice *dev) SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full; + val = gem_mdc_clk_div(priv); + if (val) + writel(val, ®s->nwcfg); + /* Enable only MDIO bus */ writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s_mdio->nwctrl); @@ -360,35 +391,10 @@ static int zynq_phy_init(struct udevice *dev) return phy_config(priv->phydev); } -static u32 gem_mdc_clk_div(struct zynq_gem_priv *priv) -{ - u32 config; - unsigned long pclk_hz; - - pclk_hz = clk_get_rate(&priv->pclk); - if (pclk_hz <= 20000000) - config = GEM_MDC_SET(GEM_CLK_DIV8); - else if (pclk_hz <= 40000000) - config = GEM_MDC_SET(GEM_CLK_DIV16); - else if (pclk_hz <= 80000000) - config = GEM_MDC_SET(GEM_CLK_DIV32); - else if (pclk_hz <= 120000000) - config = GEM_MDC_SET(GEM_CLK_DIV48); - else if (pclk_hz <= 160000000) - config = GEM_MDC_SET(GEM_CLK_DIV64); - else if (pclk_hz <= 240000000) - config = GEM_MDC_SET(GEM_CLK_DIV96); - else if (pclk_hz <= 320000000) - config = GEM_MDC_SET(GEM_CLK_DIV128); - else - config = GEM_MDC_SET(GEM_CLK_DIV224); - - return config; -} static int zynq_gem_init(struct udevice *dev) { - u32 i, nwconfig; + u32 i, nwconfig, nwcfg; int ret; unsigned long clk_rate = 0; struct zynq_gem_priv *priv = dev_get_priv(dev); @@ -494,8 +500,7 @@ static int zynq_gem_init(struct udevice *dev) return -1; } - nwconfig = gem_mdc_clk_div(priv); - nwconfig |= ZYNQ_GEM_NWCFG_INIT; + nwconfig = ZYNQ_GEM_NWCFG_INIT; /* * Set SGMII enable PCS selection only if internal PCS/PMA @@ -509,19 +514,21 @@ static int zynq_gem_init(struct udevice *dev) switch (priv->phydev->speed) { case SPEED_1000: - writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, - ®s->nwcfg); + nwconfig |= ZYNQ_GEM_NWCFG_SPEED1000; clk_rate = ZYNQ_GEM_FREQUENCY_1000; break; case SPEED_100: - writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, - ®s->nwcfg); + nwconfig |= ZYNQ_GEM_NWCFG_SPEED100; clk_rate = ZYNQ_GEM_FREQUENCY_100; break; case SPEED_10: clk_rate = ZYNQ_GEM_FREQUENCY_10; break; } + nwcfg = readl(®s->nwcfg); + nwcfg |= nwconfig; + if (nwcfg) + writel(nwcfg, ®s->nwcfg); #ifdef CONFIG_ARM64 if (priv->interface == PHY_INTERFACE_MODE_SGMII && diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 5170359..eb17a42 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -548,6 +548,8 @@ static int zynqmp_pinctrl_get_pin_muxing(struct udevice *dev, &pinmux.drive_strength); zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_VOLTAGE_STATUS, &pinmux.volt_sts); + zynqmp_pm_pinctrl_get_config(selector, PM_PINCTRL_CONFIG_TRI_STATE, + &pinmux.tri_state); switch (pinmux.drive_strength) { case PM_PINCTRL_DRIVE_STRENGTH_2MA: @@ -568,13 +570,15 @@ static int zynqmp_pinctrl_get_pin_muxing(struct udevice *dev, return -EINVAL; } - snprintf(buf, size, "slew:%s\tbias:%s\tpull:%s\tinput:%s\tdrive:%dmA\tvolt:%s", + snprintf(buf, size, + "slew:%s\tbias:%s\tpull:%s\tinput:%s\tdrive:%dmA\tvolt:%s\ttri_state:%s", pinmux.slew ? "slow" : "fast", pinmux.bias ? "enabled" : "disabled", pinmux.pull_ctrl ? "up" : "down", pinmux.input_type ? "schmitt" : "cmos", pinmux.drive_strength, - pinmux.volt_sts ? "1.8" : "3.3"); + pinmux.volt_sts ? "1.8" : "3.3", + pinmux.tri_state ? "enabled" : "disabled"); return 0; } diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h index e3e50afe..70d8cc5 100644 --- a/include/dm/pinctrl.h +++ b/include/dm/pinctrl.h @@ -7,7 +7,7 @@ #define __PINCTRL_H #define PINNAME_SIZE 10 -#define PINMUX_SIZE 80 +#define PINMUX_SIZE 90 /** * struct pinconf_param - pin config parameters diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py index cd4b4dc..b2241ae 100644 --- a/test/py/tests/test_net.py +++ b/test/py/tests/test_net.py @@ -6,6 +6,7 @@ import pytest import u_boot_utils +import uuid """ Note: This test relies on boardenv_* containing configuration values to define @@ -61,6 +62,16 @@ env__net_nfs_readable_file = { 'crc32': 'c2244b26', } +# Details regarding a file that may be read from a TFTP server. This variable +# may be omitted or set to None if PXE testing is not possible or desired. +env__net_pxe_readable_file = { + 'fn': 'default', + 'addr': 0x2000000, + 'size': 74, + 'timeout': 50000, + 'pattern': 'Linux', +} + # True if a router advertisement service is connected to the network, and should # be tested. If router advertisement testing is not possible or desired, this variable may be omitted or set to False. @@ -260,3 +271,58 @@ def test_net_nfs(u_boot_console): output = u_boot_console.run_command('crc32 %x $filesize' % addr) assert expected_crc in output + +@pytest.mark.buildconfigspec("cmd_net") +@pytest.mark.buildconfigspec("cmd_pxe") +def test_net_pxe_get(u_boot_console): + """Test the pxe get command. + + A pxe configuration file is downloaded from the TFTP server and interpreted + to boot the images mentioned in pxe configuration file. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + + if not net_set_up: + pytest.skip("Network not initialized") + + test_net_setup_static(u_boot_console) + + f = u_boot_console.config.env.get("env__net_pxe_readable_file", None) + if not f: + pytest.skip("No PXE readable file to read") + + addr = f.get("addr", None) + timeout = f.get("timeout", u_boot_console.p.timeout) + + pxeuuid = uuid.uuid1() + u_boot_console.run_command(f"setenv pxeuuid {pxeuuid}") + expected_text_uuid = f"Retrieving file: pxelinux.cfg/{pxeuuid}" + + ethaddr = u_boot_console.run_command("echo $ethaddr") + ethaddr = ethaddr.replace(':', '-') + expected_text_ethaddr = f"Retrieving file: pxelinux.cfg/01-{ethaddr}" + + ip = u_boot_console.run_command("echo $ipaddr") + ip = ip.split('.') + ipaddr_file = "".join(['%02x' % int(x) for x in ip]).upper() + expected_text_ipaddr = f"Retrieving file: pxelinux.cfg/{ipaddr_file}" + expected_text_default = f"Retrieving file: pxelinux.cfg/default" + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command("pxe get") + + assert "TIMEOUT" not in output + assert expected_text_uuid in output + assert expected_text_ethaddr in output + assert expected_text_ipaddr in output + + i = 1 + for i in range(0, len(ipaddr_file) - 1): + expected_text_ip = f"Retrieving file: pxelinux.cfg/{ipaddr_file[:-i]}" + assert expected_text_ip in output + i += 1 + + assert expected_text_default in output + assert "Config file 'default.boot' found" in output |