arm: Remove spear600 boards and the rest of SPEAr support

These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM.  Remove them.  As this is
the last of the SPEAr platforms, so remove the rest of the remaining
support as well.

Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

51 files changed, 0 insertions, 3912 deletions

diff --git a/Makefile b/Makefile
index d9473fb..0d3192c 100644
--- a/Makefile
+++ b/Makefile
@@ -1561,22 +1561,11 @@ u-boot-signed.sb: u-boot.bin spl/u-boot-spl.bin
 u-boot.sb: u-boot.bin spl/u-boot-spl.bin
 	$(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot.sb
 
-# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
-# Both images are created using mkimage (crc etc), so that the ROM
-# bootloader can check its integrity. Padding needs to be done to the
-# SPL image (with mkimage header) and not the binary. Otherwise the resulting image
-# which is loaded/copied by the ROM bootloader to SRAM doesn't fit.
-# The resulting image containing both U-Boot images is called u-boot.spr
 MKIMAGEFLAGS_u-boot-spl.img = -A $(ARCH) -T firmware -C none \
 	-a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER
 spl/u-boot-spl.img: spl/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)
 
-OBJCOPYFLAGS_u-boot.spr = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
-			  --gap-fill=0xff
-u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
-	$(call if_changed,pad_cat)
-
 ifneq ($(CONFIG_ARCH_SOCFPGA),)
 quiet_cmd_gensplx4 = GENSPLX4 $@
 cmd_gensplx4 = $(OBJCOPY) -I binary -O binary --gap-fill=0x0		\
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 512b2c7..7f493a8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -566,14 +566,6 @@ config ARCH_ORION5X
 	select CPU_ARM926EJS
 	select GPIO_EXTRA_HEADER
 
-config TARGET_SPEAR600
-	bool "Support spear600"
-	select BOARD_EARLY_INIT_F
-	select CPU_ARM926EJS
-	select GPIO_EXTRA_HEADER
-	select PL011_SERIAL
-	imply CMD_SAVES
-
 config TARGET_STV0991
 	bool "Support stv0991"
 	select CPU_V7A
@@ -587,14 +579,6 @@ config TARGET_STV0991
 	select SPI_FLASH
 	imply CMD_DM
 
-config TARGET_X600
-	bool "Support x600"
-	select BOARD_LATE_INIT
-	select CPU_ARM926EJS
-	select GPIO_EXTRA_HEADER
-	select PL011_SERIAL
-	select SUPPORT_SPL
-
 config TARGET_FLEA3
 	bool "Support flea3"
 	select CPU_ARM1136
@@ -2098,8 +2082,6 @@ source "board/kontron/sl28/Kconfig"
 source "board/myir/mys_6ulx/Kconfig"
 source "board/seeed/npi_imx6ull/Kconfig"
 source "board/socionext/developerbox/Kconfig"
-source "board/spear/spear600/Kconfig"
-source "board/spear/x600/Kconfig"
 source "board/st/stv0991/Kconfig"
 source "board/tcl/sl50/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile
deleted file mode 100644
index b1b6b40..0000000
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	:= cpu.o \
-	   reset.o \
-	   timer.o
-
-ifdef CONFIG_SPL_BUILD
-obj-y	+= spl.o
-obj-$(CONFIG_SPEAR600) += spear600.o
-obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
-obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
-obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
-obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
-else
-obj-y += spr_misc.o spr_lowlevel_init.o
-endif
-
-extra-$(CONFIG_SPL_BUILD) := start.o
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
deleted file mode 100644
index 2e0dd9e..0000000
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ /dev/null
@@ -1,108 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_misc.h>
-
-int arch_cpu_init(void)
-{
-	struct misc_regs *const misc_p =
-	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	u32 periph1_clken, periph_clk_cfg;
-
-	periph1_clken = readl(&misc_p->periph1_clken);
-
-#if defined(CONFIG_SPEAR600)
-	periph1_clken |= MISC_GPT3ENB;
-#endif
-
-#if defined(CONFIG_PL011_SERIAL)
-	periph1_clken |= MISC_UART0ENB;
-
-	periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
-	periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
-	periph_clk_cfg |= CONFIG_SPEAR_UART48M;
-	writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
-#endif
-#if defined(CONFIG_ETH_DESIGNWARE)
-	periph1_clken |= MISC_ETHENB;
-#endif
-#if defined(CONFIG_DW_UDC)
-	periph1_clken |= MISC_USBDENB;
-#endif
-#if defined(CONFIG_SYS_I2C_DW)
-	periph1_clken |= MISC_I2CENB;
-#endif
-#if defined(CONFIG_ST_SMI)
-	periph1_clken |= MISC_SMIENB;
-#endif
-#if defined(CONFIG_NAND_FSMC)
-	periph1_clken |= MISC_FSMCENB;
-#endif
-#if defined(CONFIG_USB_EHCI_SPEAR)
-	periph1_clken |= PERIPH_USBH1 | PERIPH_USBH2;
-#endif
-#if defined(CONFIG_SPEAR_GPIO)
-	periph1_clken |= MISC_GPIO3ENB | MISC_GPIO4ENB;
-#endif
-#if defined(CONFIG_PL022_SPI)
-	periph1_clken |= MISC_SSP1ENB | MISC_SSP2ENB | MISC_SSP3ENB;
-#endif
-
-	writel(periph1_clken, &misc_p->periph1_clken);
-
-	return 0;
-}
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void)
-{
-#if defined(CONFIG_SPEAR600)
-	printf("CPU:   SPEAr600\n");
-#else
-#error CPU not supported in spear platform
-#endif
-	return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && defined(CONFIG_NAND_FSMC)
-static int do_switch_ecc(struct cmd_tbl *cmdtp, int flag, int argc,
-			 char *const argv[])
-{
-	if (argc != 2)
-		goto usage;
-
-	if (strncmp(argv[1], "hw", 2) == 0) {
-		/* 1-bit HW ECC */
-		printf("Switching to 1-bit HW ECC\n");
-		fsmc_nand_switch_ecc(1);
-	} else if (strncmp(argv[1], "bch4", 2) == 0) {
-		/* 4-bit SW ECC BCH4 */
-		printf("Switching to 4-bit SW ECC (BCH4)\n");
-		fsmc_nand_switch_ecc(4);
-	} else {
-		goto usage;
-	}
-
-	return 0;
-
-usage:
-	printf("Usage: nandecc %s\n", cmdtp->usage);
-	return 1;
-}
-
-U_BOOT_CMD(
-	nandecc, 2, 0,	do_switch_ecc,
-	"switch NAND ECC calculation algorithm",
-	"hw|bch4 - Switch between NAND hardware 1-bit HW and"
-	" 4-bit SW BCH\n"
-);
-#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/reset.c b/arch/arm/cpu/arm926ejs/spear/reset.c
deleted file mode 100644
index 97a624e..0000000
--- a/arch/arm/cpu/arm926ejs/spear/reset.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_syscntl.h>
-#include <linux/delay.h>
-
-void reset_cpu(void)
-{
-	struct syscntl_regs *syscntl_regs_p =
-	    (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
-
-	printf("System is going to reboot ...\n");
-
-	/*
-	 * This 1 second delay will allow the above message
-	 * to be printed before reset
-	 */
-	udelay((1000 * 1000));
-
-	/* Going into slow mode before resetting SOC */
-	writel(0x02, &syscntl_regs_p->scctrl);
-
-	/*
-	 * Writing any value to the system status register will
-	 * reset the SoC
-	 */
-	writel(0x00, &syscntl_regs_p->scsysstat);
-
-	/* system will restart */
-	while (1)
-		;
-}
diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c b/arch/arm/cpu/arm926ejs/spear/spear600.c
deleted file mode 100644
index b31ede5..0000000
--- a/arch/arm/cpu/arm926ejs/spear/spear600.c
+++ /dev/null
@@ -1,223 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2009
- * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
- * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-#include <asm/io.h>
-#include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_defs.h>
-
-void spear_late_init(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-	writel(0x80000007, &misc_p->arb_icm_ml1);
-	writel(0x80000007, &misc_p->arb_icm_ml2);
-	writel(0x80000007, &misc_p->arb_icm_ml3);
-	writel(0x80000007, &misc_p->arb_icm_ml4);
-	writel(0x80000007, &misc_p->arb_icm_ml5);
-	writel(0x80000007, &misc_p->arb_icm_ml6);
-	writel(0x80000007, &misc_p->arb_icm_ml7);
-	writel(0x80000007, &misc_p->arb_icm_ml8);
-	writel(0x80000007, &misc_p->arb_icm_ml9);
-}
-
-static void sel_1v8(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	u32 ddr1v8, ddr2v5;
-
-	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
-	ddr2v5 &= 0x8080ffc0;
-	ddr2v5 |= 0x78000003;
-	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
-
-	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
-	ddr1v8 &= 0x8080ffc0;
-	ddr1v8 |= 0x78000010;
-	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
-
-	while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
-		;
-}
-
-static void sel_2v5(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	u32 ddr1v8, ddr2v5;
-
-	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
-	ddr1v8 &= 0x8080ffc0;
-	ddr1v8 |= 0x78000003;
-	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
-
-	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
-	ddr2v5 &= 0x8080ffc0;
-	ddr2v5 |= 0x78000010;
-	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
-
-	while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
-		;
-}
-
-/*
- * plat_ddr_init:
- */
-void plat_ddr_init(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	u32 ddrpad;
-	u32 core3v3, ddr1v8, ddr2v5;
-
-	/* DDR pad register configurations */
-	ddrpad = readl(&misc_p->ddr_pad);
-	ddrpad &= ~DDR_PAD_CNF_MSK;
-
-#if (CONFIG_DDR_HCLK)
-	ddrpad |= 0xEAAB;
-#elif (CONFIG_DDR_2HCLK)
-	ddrpad |= 0xEAAD;
-#elif (CONFIG_DDR_PLL2)
-	ddrpad |= 0xEAAD;
-#endif
-	writel(ddrpad, &misc_p->ddr_pad);
-
-	/* Compensation register configurations */
-	core3v3 = readl(&misc_p->core_3v3_compensation);
-	core3v3 &= 0x8080ffe0;
-	core3v3 |= 0x78000002;
-	writel(core3v3, &misc_p->core_3v3_compensation);
-
-	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
-	ddr1v8 &= 0x8080ffc0;
-	ddr1v8 |= 0x78000004;
-	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
-
-	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
-	ddr2v5 &= 0x8080ffc0;
-	ddr2v5 |= 0x78000004;
-	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
-
-	if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
-		/* Software memory configuration */
-		if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
-			sel_1v8();
-		else
-			sel_2v5();
-	} else {
-		/* Hardware memory configuration */
-		if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
-			sel_1v8();
-		else
-			sel_2v5();
-	}
-}
-
-/*
- * xxx_boot_selected:
- *
- * return true if the particular booting option is selected
- * return false otherwise
- */
-static u32 read_bootstrap(void)
-{
-	return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
-		& CONFIG_SPEAR_BOOTSTRAPMASK;
-}
-
-int snor_boot_selected(void)
-{
-	u32 bootstrap = read_bootstrap();
-
-	if (SNOR_BOOT_SUPPORTED) {
-		/* Check whether SNOR boot is selected */
-		if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
-			CONFIG_SPEAR_ONLYSNORBOOT)
-			return true;
-
-		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
-			CONFIG_SPEAR_NORNAND8BOOT)
-			return true;
-
-		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
-			CONFIG_SPEAR_NORNAND16BOOT)
-			return true;
-	}
-
-	return false;
-}
-
-int nand_boot_selected(void)
-{
-	u32 bootstrap = read_bootstrap();
-
-	if (NAND_BOOT_SUPPORTED) {
-		/* Check whether NAND boot is selected */
-		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
-			CONFIG_SPEAR_NORNAND8BOOT)
-			return true;
-
-		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
-			CONFIG_SPEAR_NORNAND16BOOT)
-			return true;
-	}
-
-	return false;
-}
-
-int pnor_boot_selected(void)
-{
-	/* Parallel NOR boot is not selected in any SPEAr600 revision */
-	return false;
-}
-
-int usb_boot_selected(void)
-{
-	u32 bootstrap = read_bootstrap();
-
-	if (USB_BOOT_SUPPORTED) {
-		/* Check whether USB boot is selected */
-		if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
-			return true;
-	}
-
-	return false;
-}
-
-int tftp_boot_selected(void)
-{
-	/* TFTP boot is not selected in any SPEAr600 revision */
-	return false;
-}
-
-int uart_boot_selected(void)
-{
-	/* UART boot is not selected in any SPEAr600 revision */
-	return false;
-}
-
-int spi_boot_selected(void)
-{
-	/* SPI boot is not selected in any SPEAr600 revision */
-	return false;
-}
-
-int i2c_boot_selected(void)
-{
-	/* I2C boot is not selected in any SPEAr600 revision */
-	return false;
-}
-
-int mmc_boot_selected(void)
-{
-	return false;
-}
-
-void plat_late_init(void)
-{
-	spear_late_init();
-}
diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c
deleted file mode 100644
index 693cee1..0000000
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ /dev/null
@@ -1,296 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <init.h>
-#include <spl.h>
-#include <version.h>
-#include <asm/io.h>
-#include <asm/ptrace.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_syscntl.h>
-#include <linux/mtd/st_smi.h>
-
-/* Reserve some space to store the BootROM's stack pointer during SPL operation.
- * The BSS cannot be used for this purpose because it will be zeroed after
- * having stored the pointer, so force the location to the data section.
- */
-u32 bootrom_stash_sp __section(".data");
-
-static void ddr_clock_init(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	u32 clkenb, ddrpll;
-
-	clkenb = readl(&misc_p->periph1_clken);
-	clkenb &= ~PERIPH_MPMCMSK;
-	clkenb |= PERIPH_MPMC_WE;
-
-	/* Intentionally done twice */
-	writel(clkenb, &misc_p->periph1_clken);
-	writel(clkenb, &misc_p->periph1_clken);
-
-	ddrpll = readl(&misc_p->pll_ctr_reg);
-	ddrpll &= ~MEM_CLK_SEL_MSK;
-#if (CONFIG_DDR_HCLK)
-	ddrpll |= MEM_CLK_HCLK;
-#elif (CONFIG_DDR_2HCLK)
-	ddrpll |= MEM_CLK_2HCLK;
-#elif (CONFIG_DDR_PLL2)
-	ddrpll |= MEM_CLK_PLL2;
-#else
-#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
-#endif
-	writel(ddrpll, &misc_p->pll_ctr_reg);
-
-	writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
-			&misc_p->periph1_clken);
-}
-
-static void mpmc_init_values(void)
-{
-	u32 i;
-	u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
-	u32 *mpmc_val_p = &mpmc_conf_vals[0];
-
-	for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
-		writel(*mpmc_val_p, mpmc_reg_p);
-
-	mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
-
-	/*
-	 * MPMC controller start
-	 * MPMC waiting for DLLLOCKREG high
-	 */
-	writel(0x01000100, &mpmc_reg_p[7]);
-
-	while (!(readl(&mpmc_reg_p[3]) & 0x10000))
-		;
-}
-
-static void mpmc_init(void)
-{
-	/* Clock related settings for DDR */
-	ddr_clock_init();
-
-	/*
-	 * DDR pad register bits are different for different SoCs
-	 * Compensation values are also handled separately
-	 */
-	plat_ddr_init();
-
-	/* Initialize mpmc register values */
-	mpmc_init_values();
-}
-
-static void pll_init(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-	/* Initialize PLLs */
-	writel(FREQ_332, &misc_p->pll1_frq);
-	writel(0x1C0A, &misc_p->pll1_cntl);
-	writel(0x1C0E, &misc_p->pll1_cntl);
-	writel(0x1C06, &misc_p->pll1_cntl);
-	writel(0x1C0E, &misc_p->pll1_cntl);
-
-	writel(FREQ_332, &misc_p->pll2_frq);
-	writel(0x1C0A, &misc_p->pll2_cntl);
-	writel(0x1C0E, &misc_p->pll2_cntl);
-	writel(0x1C06, &misc_p->pll2_cntl);
-	writel(0x1C0E, &misc_p->pll2_cntl);
-
-	/* wait for pll locks */
-	while (!(readl(&misc_p->pll1_cntl) & 0x1))
-		;
-	while (!(readl(&misc_p->pll2_cntl) & 0x1))
-		;
-}
-
-static void mac_init(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-	writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
-			&misc_p->periph1_clken);
-
-	writel(SYNTH23, &misc_p->gmac_synth_clk);
-
-	switch (get_socrev()) {
-	case SOC_SPEAR600_AA:
-	case SOC_SPEAR600_AB:
-	case SOC_SPEAR600_BA:
-	case SOC_SPEAR600_BB:
-	case SOC_SPEAR600_BC:
-	case SOC_SPEAR600_BD:
-		writel(0x0, &misc_p->gmac_ctr_reg);
-		break;
-
-	case SOC_SPEAR300:
-	case SOC_SPEAR310:
-	case SOC_SPEAR320:
-		writel(0x4, &misc_p->gmac_ctr_reg);
-		break;
-	}
-
-	writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
-			&misc_p->periph1_clken);
-
-	writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
-			&misc_p->periph1_rst);
-	writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
-			&misc_p->periph1_rst);
-}
-
-static void sys_init(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	struct syscntl_regs *syscntl_p =
-		(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
-
-	/* Set system state to SLOW */
-	writel(SLOW, &syscntl_p->scctrl);
-	writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
-
-	/* Initialize PLLs */
-	pll_init();
-
-	/*
-	 * Ethernet configuration
-	 * To be done only if the tftp boot is not selected already
-	 * Boot code ensures the correct configuration in tftp booting
-	 */
-	if (!tftp_boot_selected())
-		mac_init();
-
-	writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
-	writel(0x555, &misc_p->amba_clk_cfg);
-
-	writel(NORMAL, &syscntl_p->scctrl);
-
-	/* Wait for system to switch to normal mode */
-	while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
-		!= NORMAL)
-		;
-}
-
-/*
- * get_socrev
- *
- * Get SoC Revision.
- * @return SOC_SPEARXXX
- */
-int get_socrev(void)
-{
-#if defined(CONFIG_SPEAR600)
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	u32 soc_id = readl(&misc_p->soc_core_id);
-	u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
-	u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
-
-	if ((pri_socid == 'B') && (sec_socid == 'B'))
-		return SOC_SPEAR600_BB;
-	else if ((pri_socid == 'B') && (sec_socid == 'C'))
-		return SOC_SPEAR600_BC;
-	else if ((pri_socid == 'B') && (sec_socid == 'D'))
-		return SOC_SPEAR600_BD;
-	else if (soc_id == 0)
-		return SOC_SPEAR600_BA;
-	else
-		return SOC_SPEAR_NA;
-#endif
-}
-
-/*
- * SNOR (Serial NOR flash) related functions
- */
-static void snor_init(void)
-{
-	struct smi_regs *const smicntl =
-		(struct smi_regs * const)CONFIG_SYS_SMI_BASE;
-
-	/* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
-	writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
-	       &smicntl->smi_cr1);
-}
-
-u32 spl_boot_device(void)
-{
-	u32 mode = 0;
-
-	if (usb_boot_selected()) {
-		mode = BOOT_DEVICE_BOOTROM;
-	} else if (snor_boot_selected()) {
-		/* SNOR-SMI initialization */
-		snor_init();
-
-		mode = BOOT_DEVICE_NOR;
-	}
-
-	return mode;
-}
-
-void board_boot_order(u32 *spl_boot_list)
-{
-	spl_boot_list[0] = spl_boot_device();
-
-	/*
-	 * If the main boot device (eg. NOR) is empty, try to jump back into the
-	 * BootROM for USB boot process.
-	 */
-	if (USB_BOOT_SUPPORTED)
-		spl_boot_list[1] = BOOT_DEVICE_BOOTROM;
-}
-
-void board_init_f(ulong dummy)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-	/* Initialize PLLs */
-	sys_init();
-
-	preloader_console_init();
-	arch_cpu_init();
-
-	/* Enable IPs (release reset) */
-	writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
-
-	/* Initialize MPMC */
-	puts("Configure DDR\n");
-	mpmc_init();
-	spear_late_init();
-}
-
-/*
- * In a few cases (Ethernet, UART or USB boot, we might want to go back into the
- * BootROM code right after having initialized a few components like the DRAM).
- * The following function is called from SPL common code (board_init_r).
- */
-int board_return_to_bootrom(struct spl_image_info *spl_image,
-			    struct spl_boot_device *bootdev)
-{
-	/*
-	 * Retrieve the BootROM's stack pointer and jump back to the start of
-	 * the SPL, where we can easily branch back into the BootROM. Don't do
-	 * it right here because SPL might be compiled in Thumb mode while the
-	 * BootROM expects ARM mode.
-	 */
-	asm volatile ("ldr r0, =bootrom_stash_sp;"
-		      "ldr r0, [r0];"
-		      "mov sp, r0;"
-#if defined(CONFIG_SPL_SYS_THUMB_BUILD)
-		      "blx back_to_bootrom;"
-#else
-		      "bl back_to_bootrom;"
-#endif
-		      );
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
deleted file mode 100644
index 79ab2a7..0000000
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
+++ /dev/null
@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2009
- * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- */
-
-#include <common.h>
-
-#if (CONFIG_DDR_PLL2)
-
-const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
-	0x00000001,
-	0x00000000,
-	0x01000000,
-	0x00000101,
-	0x00000001,
-	0x01000000,
-	0x00010001,
-	0x00000100,
-	0x00010001,
-	0x00000003,
-	0x01000201,
-	0x06000202,
-	0x06060106,
-	0x03050502,
-	0x03040404,
-	0x02020503,
-	0x02010106,
-	0x03000404,
-	0x02030202,
-	0x03000204,
-	0x0707073f,
-	0x07070707,
-	0x06060607,
-	0x06060606,
-	0x05050506,
-	0x05050505,
-	0x04040405,
-	0x04040404,
-	0x03030304,
-	0x03030303,
-	0x02020203,
-	0x02020202,
-	0x01010102,
-	0x01010101,
-	0x08080a01,
-	0x0000023f,
-	0x00040800,
-	0x00000000,
-	0x00000f02,
-	0x00001b1b,
-	0x7f000000,
-	0x005f0000,
-	0x1c040b6a,
-	0x00640064,
-	0x00640064,
-	0x00640064,
-	0x00000064,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x000007ff,
-	0x00000000,
-	0x47ec00c8,
-	0x00c8001f,
-	0x00000000,
-	0x0000cd98,
-	0x00000000,
-	0x03030100,
-	0x03030303,
-	0x03030303,
-	0x03030303,
-	0x00270000,
-	0x00250027,
-	0x00300000,
-	0x008900b7,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000
-};
-#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
deleted file mode 100644
index 121b636..0000000
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2009
- * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- */
-
-#include <common.h>
-
-#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
-
-const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
-#if (CONFIG_DDR_PLL2)
-	0x00000001,
-	0x00000000,
-#elif (CONFIG_DDR_2HCLK)
-	0x02020201,
-	0x02020202,
-#endif
-	0x01000000,
-	0x00000101,
-	0x00000101,
-	0x01000000,
-	0x00010001,
-	0x00000100,
-	0x01010001,
-	0x00000201,
-	0x01000101,
-	0x06000002,
-	0x06060106,
-	0x03050502,
-	0x03040404,
-	0x02020503,
-	0x02010106,
-	0x03000405,
-	0x03040202,
-	0x04000305,
-	0x0707073f,
-	0x07070707,
-	0x06060607,
-	0x06060606,
-	0x05050506,
-	0x05050505,
-	0x04040405,
-	0x04040404,
-	0x03030304,
-	0x03030303,
-	0x02020203,
-	0x02020202,
-	0x01010102,
-	0x01010101,
-	0x0a0a0a01,
-	0x0000023f,
-	0x00050a00,
-	0x11000000,
-	0x00001302,
-	0x00000A0A,
-	0x72000000,
-	0x00550000,
-	0x2b050e86,
-	0x00640064,
-	0x00640064,
-	0x00640064,
-	0x00000064,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00000a24,
-	0x43C20000,
-	0x5b1c00c8,
-	0x00c8002e,
-	0x00000000,
-	0x0001046b,
-	0x00000000,
-	0x03030100,
-	0x03030303,
-	0x03030303,
-	0x03030303,
-	0x00210000,
-	0x00010021,
-	0x00200000,
-	0x006c0090,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000
-};
-#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
deleted file mode 100644
index 64c8bab..0000000
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
+++ /dev/null
@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2009
- * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- */
-
-#include <common.h>
-
-#if (CONFIG_DDR_HCLK)
-
-const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
-	0x03030301,
-	0x03030303,
-	0x01000000,
-	0x00000101,
-	0x00000001,
-	0x01000000,
-	0x00010001,
-	0x00000100,
-	0x00010001,
-	0x00000003,
-	0x01000201,
-	0x06000202,
-	0x06060106,
-	0x03050502,
-	0x03040404,
-	0x02020503,
-	0x02010106,
-	0x03000404,
-	0x02020202,
-	0x03000203,
-	0x0707073f,
-	0x07070707,
-	0x06060607,
-	0x06060606,
-	0x05050506,
-	0x05050505,
-	0x04040405,
-	0x04040404,
-	0x03030304,
-	0x03030303,
-	0x02020203,
-	0x02020202,
-	0x01010102,
-	0x01010101,
-	0x08080a01,
-	0x0000023f,
-	0x00030600,
-	0x00000000,
-	0x00000a02,
-	0x00001c1c,
-	0x7f000000,
-	0x005f0000,
-	0x12030743,
-	0x00640064,
-	0x00640064,
-	0x00640064,
-	0x00000064,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x0000050e,
-	0x00000000,
-	0x2d8900c8,
-	0x00c80014,
-	0x00000000,
-	0x00008236,
-	0x00000000,
-	0x03030100,
-	0x03030303,
-	0x03030303,
-	0x03030303,
-	0x00400000,
-	0x003a0040,
-	0x00680000,
-	0x00d80120,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000
-};
-#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
deleted file mode 100644
index 8765466..0000000
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2009
- * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- */
-
-#include <common.h>
-
-#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
-
-const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
-#if (CONFIG_DDR_PLL2)
-	0x00000001,
-	0x00000000,
-#elif (CONFIG_DDR_2HCLK)
-	0x02020201,
-	0x02020202,
-#endif
-	0x01000000,
-	0x00000101,
-	0x00000101,
-	0x01000000,
-	0x00010001,
-	0x00000100,
-	0x01010001,
-	0x00000201,
-	0x01000101,
-	0x06000002,
-	0x06060106,
-	0x03050502,
-	0x03040404,
-	0x02020503,
-#ifdef CONFIG_X600
-	0x02030206,
-#else
-	0x02010106,
-#endif
-	0x03000405,
-	0x03040202,
-	0x04000305,
-	0x0707073f,
-	0x07070707,
-	0x06060607,
-	0x06060606,
-	0x05050506,
-	0x05050505,
-	0x04040405,
-	0x04040404,
-	0x03030304,
-	0x03030303,
-	0x02020203,
-	0x02020202,
-	0x01010102,
-	0x01010101,
-	0x0a0a0a01,
-	0x0000023f,
-	0x00050a00,
-	0x11000000,
-	0x00001302,
-	0x00000A0A,
-#ifdef CONFIG_X600
-	0x7f000000,
-	0x005c0000,
-#else
-	0x72000000,
-	0x00550000,
-#endif
-	0x2b050e86,
-	0x00640064,
-	0x00640064,
-	0x00640064,
-	0x00000064,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00000a24,
-	0x43C20000,
-	0x5b1c00c8,
-	0x00c8002e,
-	0x00000000,
-	0x0001046b,
-	0x00000000,
-	0x03030100,
-	0x03030303,
-	0x03030303,
-	0x03030303,
-	0x00210000,
-	0x00010021,
-	0x00200000,
-	0x006c0090,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000
-};
-#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S b/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S
deleted file mode 100644
index 417e87a..0000000
--- a/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S
+++ /dev/null
@@ -1,173 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2006
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#include <config.h>
-
-/*
- * platform specific initializations are already done in Xloader
- * Initializations already done include
- * DDR, PLLs, IP's clock enable and reset release etc
- */
-.globl lowlevel_init
-lowlevel_init:
-	mov	pc, lr
-
-/* void setfreq(unsigned int device, unsigned int frequency) */
-.global setfreq
-setfreq:
-	stmfd 	sp!,{r14}
-	stmfd 	sp!,{r0-r12}
-
-	mov  	r8,sp
-	ldr 	sp,SRAM_STACK_V
-
-	/* Saving the function arguements for later use */
-	mov  	r4,r0
-	mov  	r5,r1
-
-	/* Putting DDR into self refresh */
-	ldr 	r0,DDR_07_V
-	ldr	r1,[r0]
-	ldr	r2,DDR_ACTIVE_V
-	bic	r1, r1, r2
-	str	r1,[r0]
-	ldr 	r0,DDR_57_V
-	ldr	r1,[r0]
-	ldr	r2,CYCLES_MASK_V
-	bic	r1, r1, r2
-	ldr	r2,REFRESH_CYCLES_V
-	orr	r1, r1, r2, lsl #16
-	str	r1,[r0]
-	ldr 	r0,DDR_07_V
-	ldr	r1,[r0]
-	ldr	r2,SREFRESH_MASK_V
-	orr	r1, r1, r2
-	str	r1,[r0]
-
-	/* flush pipeline */
-	b	flush
-	.align 5
-flush:
-	/* Delay to ensure self refresh mode */
-	ldr	r0,SREFRESH_DELAY_V
-delay:
-	sub	r0,r0,#1
-	cmp	r0,#0
-	bne	delay
-
-	/* Putting system in slow mode */
-	ldr	r0,SCCTRL_V
-	mov	r1,#2
-	str	r1,[r0]
-
-	/* Changing PLL(1/2) frequency */
-	mov	r0,r4
-	mov	r1,r5
-
-	cmp	r4,#0
-	beq	pll1_freq
-
-	/* Change PLL2 (DDR frequency) */
-	ldr	r6,PLL2_FREQ_V
-	ldr	r7,PLL2_CNTL_V
-	b	pll2_freq
-
-pll1_freq:
-	/* Change PLL1 (CPU frequency) */
-	ldr	r6,PLL1_FREQ_V
-	ldr	r7,PLL1_CNTL_V
-
-pll2_freq:
-	mov	r0,r6
-	ldr	r1,[r0]
-	ldr	r2,PLLFREQ_MASK_V
-	bic	r1,r1,r2
-	mov	r2,r5,lsr#1
-	orr	r1,r1,r2,lsl#24
-	str	r1,[r0]
-
-	mov	r0,r7
-	ldr	r1,P1C0A_V
-	str	r1,[r0]
-	ldr	r1,P1C0E_V
-	str	r1,[r0]
-	ldr	r1,P1C06_V
-	str	r1,[r0]
-	ldr	r1,P1C0E_V
-	str	r1,[r0]
-
-lock:
-	ldr	r1,[r0]
-	and	r1,r1,#1
-	cmp	r1,#0
-	beq	lock
-
-	/* Putting system back to normal mode */
-	ldr	r0,SCCTRL_V
-	mov	r1,#4
-	str	r1,[r0]
-
-	/* Putting DDR back to normal */
-	ldr	r0,DDR_07_V
-	ldr	r1,[R0]
-	ldr	r2,SREFRESH_MASK_V
-	bic	r1, r1, r2
-	str	r1,[r0]
-	ldr	r2,DDR_ACTIVE_V
-	orr	r1, r1, r2
-	str	r1,[r0]
-
-	/* Delay to ensure self refresh mode */
-	ldr	r0,SREFRESH_DELAY_V
-1:
-	sub	r0,r0,#1
-	cmp	r0,#0
-	bne	1b
-
-	mov	sp,r8
-	/* Resuming back to code */
-	ldmia	sp!,{r0-r12}
-	ldmia	sp!,{pc}
-
-SCCTRL_V:
-	.word 0xfca00000
-PLL1_FREQ_V:
-	.word 0xfca8000C
-PLL1_CNTL_V:
-	.word 0xfca80008
-PLL2_FREQ_V:
-	.word 0xfca80018
-PLL2_CNTL_V:
-	.word 0xfca80014
-PLLFREQ_MASK_V:
-	.word 0xff000000
-P1C0A_V:
-	.word 0x1C0A
-P1C0E_V:
-	.word 0x1C0E
-P1C06_V:
-	.word 0x1C06
-
-SREFRESH_DELAY_V:
-	.word 0x9999
-SRAM_STACK_V:
-	.word 0xD2800600
-DDR_07_V:
-	.word 0xfc60001c
-DDR_ACTIVE_V:
-	.word 0x01000000
-DDR_57_V:
-	.word 0xfc6000e4
-CYCLES_MASK_V:
-	.word 0xffff0000
-REFRESH_CYCLES_V:
-	.word 0xf0f0
-SREFRESH_MASK_V:
-	.word 0x00010000
-
-.global setfreq_sz
-setfreq_sz:
-	.word setfreq_sz - setfreq
diff --git a/arch/arm/cpu/arm926ejs/spear/spr_misc.c b/arch/arm/cpu/arm926ejs/spear/spr_misc.c
deleted file mode 100644
index 044052b..0000000
--- a/arch/arm/cpu/arm926ejs/spear/spr_misc.c
+++ /dev/null
@@ -1,253 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#include <common.h>
-#include <command.h>
-#include <cpu_func.h>
-#include <env.h>
-#include <i2c.h>
-#include <init.h>
-#include <net.h>
-#include <asm/global_data.h>
-#include <linux/mtd/st_smi.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_emi.h>
-#include <asm/arch/spr_defs.h>
-
-#define CPU		0
-#define DDR		1
-#define SRAM_REL	0xD2801000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET)
-static int i2c_read_mac(uchar *buffer);
-#endif
-
-int dram_init(void)
-{
-	/* Store complete RAM size and return */
-	gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE);
-
-	return 0;
-}
-
-int dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = gd->ram_size;
-
-	return 0;
-}
-
-int board_early_init_f()
-{
-#if defined(CONFIG_ST_SMI)
-	smi_init();
-#endif
-	return 0;
-}
-int misc_init_r(void)
-{
-#if defined(CONFIG_CMD_NET)
-	uchar mac_id[6];
-
-	if (!eth_env_get_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
-		eth_env_set_enetaddr("ethaddr", mac_id);
-#endif
-	env_set("verify", "n");
-
-#if defined(CONFIG_SPEAR_USBTTY)
-	env_set("stdin", "usbtty");
-	env_set("stdout", "usbtty");
-	env_set("stderr", "usbtty");
-
-#ifndef CONFIG_SYS_NO_DCACHE
-	dcache_enable();
-#endif
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_SPEAR_EMI
-struct cust_emi_para {
-	unsigned int tap;
-	unsigned int tsdp;
-	unsigned int tdpw;
-	unsigned int tdpr;
-	unsigned int tdcs;
-};
-
-/* EMI timing setting of m28w640hc of linux kernel */
-const struct cust_emi_para emi_timing_m28w640hc = {
-	.tap = 0x10,
-	.tsdp = 0x05,
-	.tdpw = 0x0a,
-	.tdpr = 0x0a,
-	.tdcs = 0x05,
-};
-
-/* EMI timing setting of bootrom */
-const struct cust_emi_para emi_timing_bootrom = {
-	.tap = 0xf,
-	.tsdp = 0x0,
-	.tdpw = 0xff,
-	.tdpr = 0x111,
-	.tdcs = 0x02,
-};
-
-void spear_emi_init(void)
-{
-	const struct cust_emi_para *p = &emi_timing_m28w640hc;
-	struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
-	unsigned int cs;
-	unsigned int val, tmp;
-
-	val = readl(CONFIG_SPEAR_RASBASE);
-
-	if (val & EMI_ACKMSK)
-		tmp = 0x3f;
-	else
-		tmp = 0x0;
-
-	writel(tmp, &emi_regs_p->ack);
-
-	for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
-		writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
-		writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
-		writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
-		writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
-		writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
-		writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
-		       &emi_regs_p->bank_regs[cs].control);
-	}
-}
-#endif
-
-int spear_board_init(ulong mach_type)
-{
-	gd->bd->bi_arch_number = mach_type;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
-
-#ifdef CONFIG_SPEAR_EMI
-	spear_emi_init();
-#endif
-	return 0;
-}
-
-#if defined(CONFIG_CMD_NET)
-static int i2c_read_mac(uchar *buffer)
-{
-	u8 buf[2];
-
-	i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
-
-	/* Check if mac in i2c memory is valid */
-	if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
-		/* Valid mac address is saved in i2c eeprom */
-		i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN);
-		return 0;
-	}
-
-	return -1;
-}
-
-static int write_mac(uchar *mac)
-{
-	u8 buf[2];
-
-	buf[0] = (u8)MAGIC_BYTE0;
-	buf[1] = (u8)MAGIC_BYTE1;
-	i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
-
-	buf[0] = (u8)~MAGIC_BYTE0;
-	buf[1] = (u8)~MAGIC_BYTE1;
-
-	i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
-
-	/* check if valid MAC address is saved in I2C EEPROM or not? */
-	if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
-		i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN);
-		puts("I2C EEPROM written with mac address \n");
-		return 0;
-	}
-
-	puts("I2C EEPROM writing failed\n");
-	return -1;
-}
-#endif
-
-int do_chip_config(struct cmd_tbl *cmdtp, int flag, int argc,
-		   char *const argv[])
-{
-	void (*sram_setfreq) (unsigned int, unsigned int);
-	unsigned int frequency;
-#if defined(CONFIG_CMD_NET)
-	unsigned char mac[6];
-#endif
-
-	if ((argc > 3) || (argc < 2))
-		return cmd_usage(cmdtp);
-
-	if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) {
-
-		frequency = simple_strtoul(argv[2], NULL, 0);
-
-		if (frequency > 333) {
-			printf("Frequency is limited to 333MHz\n");
-			return 1;
-		}
-
-		sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz);
-
-		if (!strcmp(argv[1], "cpufreq")) {
-			sram_setfreq(CPU, frequency);
-			printf("CPU frequency changed to %u\n", frequency);
-		} else {
-			sram_setfreq(DDR, frequency);
-			printf("DDR frequency changed to %u\n", frequency);
-		}
-
-		return 0;
-
-#if defined(CONFIG_CMD_NET)
-	} else if (!strcmp(argv[1], "ethaddr")) {
-
-		u32 reg;
-		char *e, *s = argv[2];
-		for (reg = 0; reg < 6; ++reg) {
-			mac[reg] = s ? simple_strtoul(s, &e, 16) : 0;
-			if (s)
-				s = (*e) ? e + 1 : e;
-		}
-		write_mac(mac);
-
-		return 0;
-#endif
-	} else if (!strcmp(argv[1], "print")) {
-#if defined(CONFIG_CMD_NET)
-		if (!i2c_read_mac(mac)) {
-			printf("Ethaddr (from i2c mem) = %pM\n", mac);
-		} else {
-			printf("Ethaddr (from i2c mem) = Not set\n");
-		}
-#endif
-		return 0;
-	}
-
-	return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
-	   "configure chip",
-	   "chip_config cpufreq/ddrfreq frequency\n"
-#if defined(CONFIG_CMD_NET)
-	   "chip_config ethaddr XX:XX:XX:XX:XX:XX\n"
-#endif
-	   "chip_config print");
diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S
deleted file mode 100644
index 9ac9629..0000000
--- a/arch/arm/cpu/arm926ejs/spear/start.S
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  armboot - Startup Code for ARM926EJS CPU-core
- *
- *  Copyright (c) 2003  Texas Instruments
- *
- *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- */
-
-
-#include <config.h>
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * The BootROM already initialized its own stack in the [0-0xb00] reserved
- * range of the SRAM. The SPL (in _main) will update the stack pointer to
- * its own SRAM area (right before the gd section).
- *
- *************************************************************************
- */
-
-	.globl	reset
-	.globl	back_to_bootrom
-
-reset:
-	/*
-	* SPL has to return back to BootROM in a few cases (eg. Ethernet boot,
-	* UART boot, USB boot): save registers in BootROM's stack and then the
-	* BootROM's stack pointer in the SPL's data section.
-	*/
-	push	{r0-r12,lr}
-	ldr	r0, =bootrom_stash_sp
-	str	sp, [r0]
-
-	/*
-	 * Flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* Flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* Flush v4 TLB */
-
-	/*
-	 * Enable instruction cache
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/*
-	 * Go setup Memory and board specific bits prior to relocation.
-	 * This call is not supposed to return.
-	 */
-	b	_main	/* _main will call board_init_f */
-
-back_to_bootrom:
-	pop	{r0-r12,pc}
diff --git a/arch/arm/cpu/arm926ejs/spear/timer.c b/arch/arm/cpu/arm926ejs/spear/timer.c
deleted file mode 100644
index d5f6ccc..0000000
--- a/arch/arm/cpu/arm926ejs/spear/timer.c
+++ /dev/null
@@ -1,121 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#include <common.h>
-#include <init.h>
-#include <time.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_gpt.h>
-#include <asm/arch/spr_misc.h>
-#include <asm/ptrace.h>
-#include <linux/delay.h>
-
-#define GPT_RESOLUTION	(CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ)
-#define READ_TIMER()	(readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)
-
-static struct gpt_regs *const gpt_regs_p =
-    (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE;
-
-static struct misc_regs *const misc_regs_p =
-    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static ulong get_timer_masked(void);
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-int timer_init(void)
-{
-	u32 synth;
-
-	/* Prescaler setting */
-#if defined(CONFIG_SPEAR600)
-	writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
-	synth = MISC_GPT3SYNTH;
-#else
-# error Incorrect config. Can only be SPEAR{600|300|310|320}
-#endif
-
-	writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
-	       &misc_regs_p->periph_clk_cfg);
-
-	/* disable timers */
-	writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control);
-
-	/* load value for free running */
-	writel(GPT_FREE_RUNNING, &gpt_regs_p->compare);
-
-	/* auto reload, start timer */
-	writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control);
-
-	/* Reset the timer */
-	lastdec = READ_TIMER();
-	timestamp = 0;
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer(ulong base)
-{
-	return (get_timer_masked() / GPT_RESOLUTION) - base;
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong tmo;
-	ulong start = get_timer_masked();
-	ulong tenudelcnt = CONFIG_SPEAR_HZ_CLOCK / (1000 * 100);
-	ulong rndoff;
-
-	rndoff = (usec % 10) ? 1 : 0;
-
-	/* tenudelcnt timer tick gives 10 microsecconds delay */
-	tmo = ((usec / 10) + rndoff) * tenudelcnt;
-
-	while ((ulong) (get_timer_masked() - start) < tmo)
-		;
-}
-
-static ulong get_timer_masked(void)
-{
-	ulong now = READ_TIMER();
-
-	if (now >= lastdec) {
-		/* normal mode */
-		timestamp += now - lastdec;
-	} else {
-		/* we have an overflow ... */
-		timestamp += now + GPT_FREE_RUNNING - lastdec;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SPEAR_HZ;
-}
diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
deleted file mode 100644
index 0964a97..0000000
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 Stefan Roese <sr@denx.de>
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- */
-
-MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
-		LENGTH = IMAGE_MAX_SIZE }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	.text      :
-	{
-		__start = .;
-		*(.vectors)
-		CPUDIR/spear/start.o	(.text*)
-		*(.text*)
-	} > .sram
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
-
-	. = ALIGN(4);
-	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	} > .sram
-
-	. = ALIGN(4);
-	__image_copy_end = .;
-	_end = .;
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start = .;
-		*(.bss*)
-		. = ALIGN(4);
-		__bss_end = .;
-	} > .sram
-}
diff --git a/arch/arm/include/asm/arch-spear/clk.h b/arch/arm/include/asm/arch-spear/clk.h
deleted file mode 100644
index b193f76..0000000
--- a/arch/arm/include/asm/arch-spear/clk.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010, STMicroelectronics - All Rights Reserved
- * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
- */
-
-static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
-{
-	return 83000000;
-}
diff --git a/arch/arm/include/asm/arch-spear/gpio.h b/arch/arm/include/asm/arch-spear/gpio.h
deleted file mode 100644
index 4c8c40b..0000000
--- a/arch/arm/include/asm/arch-spear/gpio.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- */
-
-
-#ifndef __ASM_ARCH_SPEAR_GPIO_H
-#define __ASM_ARCH_SPEAR_GPIO_H
-
-enum gpio_direction {
-	GPIO_DIRECTION_IN,
-	GPIO_DIRECTION_OUT,
-};
-
-struct gpio_regs {
-	u32 gpiodata[0x100];	/* 0x000 ... 0x3fc */
-	u32 gpiodir;		/* 0x400 */
-};
-
-#define SPEAR_GPIO_COUNT		8
-#define DATA_REG_ADDR(gpio)		(1 << (gpio + 2))
-
-#endif	/* __ASM_ARCH_SPEAR_GPIO_H */
diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h
deleted file mode 100644
index 69b97a0..0000000
--- a/arch/arm/include/asm/arch-spear/hardware.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2009, STMicroelectronics - All Rights Reserved
- * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
- */
-
-#ifndef _ASM_ARCH_HARDWARE_H
-#define _ASM_ARCH_HARDWARE_H
-
-#define CONFIG_SYS_USBD_BASE			0xE1100000
-#define CONFIG_SYS_PLUG_BASE			0xE1200000
-#define CONFIG_SYS_FIFO_BASE			0xE1000800
-#define CONFIG_SYS_UHC0_EHCI_BASE		0xE1800000
-#define CONFIG_SYS_UHC1_EHCI_BASE		0xE2000000
-#define CONFIG_SYS_SMI_BASE			0xFC000000
-#define CONFIG_SPEAR_SYSCNTLBASE		0xFCA00000
-#define CONFIG_SPEAR_TIMERBASE			0xFC800000
-#define CONFIG_SPEAR_MISCBASE			0xFCA80000
-#define CONFIG_SPEAR_ETHBASE			0xE0800000
-#define CONFIG_SPEAR_MPMCBASE			0xFC600000
-#define CONFIG_SSP1_BASE			0xD0100000
-#define CONFIG_SSP2_BASE			0xD0180000
-#define CONFIG_SSP3_BASE			0xD8180000
-#define CONFIG_GPIO_BASE			0xD8100000
-
-#define CONFIG_SYS_NAND_CLE			(1 << 16)
-#define CONFIG_SYS_NAND_ALE			(1 << 17)
-
-#if defined(CONFIG_SPEAR600)
-#define CONFIG_SYS_FSMC_BASE			0xD1800000
-#define CONFIG_FSMC_NAND_BASE			0xD2000000
-
-#define CONFIG_SPEAR_BOOTSTRAPCFG		0xFCA80000
-#define CONFIG_SPEAR_BOOTSTRAPSHFT		16
-#define CONFIG_SPEAR_BOOTSTRAPMASK		0xB
-#define CONFIG_SPEAR_ONLYSNORBOOT		0xA
-#define CONFIG_SPEAR_NORNANDBOOT		0xB
-#define CONFIG_SPEAR_NORNAND8BOOT		0x8
-#define CONFIG_SPEAR_NORNAND16BOOT		0x9
-#define CONFIG_SPEAR_USBBOOT			0x8
-
-#define CONFIG_SPEAR_MPMCREGS			100
-
-#endif
-#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-spear/spr_defs.h b/arch/arm/include/asm/arch-spear/spr_defs.h
deleted file mode 100644
index d09e7eb..0000000
--- a/arch/arm/include/asm/arch-spear/spr_defs.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#ifndef __SPR_DEFS_H__
-#define __SPR_DEFS_H__
-
-extern int spear_board_init(ulong);
-extern void setfreq(unsigned int, unsigned int);
-extern unsigned int setfreq_sz;
-
-void plat_ddr_init(void);
-void spear_late_init(void);
-
-int snor_boot_selected(void);
-int nand_boot_selected(void);
-int pnor_boot_selected(void);
-int usb_boot_selected(void);
-int uart_boot_selected(void);
-int tftp_boot_selected(void);
-int i2c_boot_selected(void);
-int spi_boot_selected(void);
-int mmc_boot_selected(void);
-
-extern u32 mpmc_conf_vals[];
-
-struct chip_data {
-	int cpufreq;
-	int dramfreq;
-	int dramtype;
-	uchar version[32];
-};
-
-/* HW mac id in i2c memory definitions */
-#define MAGIC_OFF	0x0
-#define MAGIC_LEN	0x2
-#define MAGIC_BYTE0	0x55
-#define MAGIC_BYTE1	0xAA
-#define MAC_OFF		0x2
-#define MAC_LEN		0x6
-
-#define PNOR_WIDTH_8			0
-#define	PNOR_WIDTH_16			1
-#define	PNOR_WIDTH_32			2
-#define PNOR_WIDTH_NUM			3
-#define PNOR_WIDTH_SEARCH		0xff
-
-#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_emi.h b/arch/arm/include/asm/arch-spear/spr_emi.h
deleted file mode 100644
index 7b1cf35..0000000
--- a/arch/arm/include/asm/arch-spear/spr_emi.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009
- * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
- */
-
-#ifndef __SPEAR_EMI_H__
-#define __SPEAR_EMI_H__
-
-#ifdef CONFIG_SPEAR_EMI
-
-struct emi_bank_regs {
-	u32 tap;
-	u32 tsdp;
-	u32 tdpw;
-	u32 tdpr;
-	u32 tdcs;
-	u32 control;
-};
-
-struct emi_regs {
-	struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS];
-	u32 tout;
-	u32 ack;
-	u32 irq;
-};
-
-#define EMI_ACKMSK		0x40
-
-/* control register definitions */
-#define EMI_CNTL_ENBBYTEW	(1 << 2)
-#define EMI_CNTL_ENBBYTER	(1 << 3)
-#define EMI_CNTL_ENBBYTERW	(EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW)
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_gpt.h b/arch/arm/include/asm/arch-spear/spr_gpt.h
deleted file mode 100644
index dced0a1..0000000
--- a/arch/arm/include/asm/arch-spear/spr_gpt.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#ifndef _SPR_GPT_H
-#define _SPR_GPT_H
-
-struct gpt_regs {
-	u8 reserved[0x80];
-	u32 control;
-	u32 status;
-	u32 compare;
-	u32 count;
-	u32 capture_re;
-	u32 capture_fe;
-};
-
-/*
- * TIMER_CONTROL register settings
- */
-
-#define GPT_PRESCALER_MASK		0x000F
-#define GPT_PRESCALER_1			0x0000
-#define GPT_PRESCALER_2 		0x0001
-#define GPT_PRESCALER_4 		0x0002
-#define GPT_PRESCALER_8 		0x0003
-#define GPT_PRESCALER_16		0x0004
-#define GPT_PRESCALER_32		0x0005
-#define GPT_PRESCALER_64		0x0006
-#define GPT_PRESCALER_128		0x0007
-#define GPT_PRESCALER_256		0x0008
-
-#define GPT_MODE_SINGLE_SHOT		0x0010
-#define GPT_MODE_AUTO_RELOAD		0x0000
-
-#define GPT_ENABLE			0x0020
-
-#define GPT_CAPT_MODE_MASK		0x00C0
-#define GPT_CAPT_MODE_NONE		0x0000
-#define GPT_CAPT_MODE_RE		0x0040
-#define GPT_CAPT_MODE_FE		0x0080
-#define GPT_CAPT_MODE_BOTH		0x00C0
-
-#define GPT_INT_MATCH			0x0100
-#define GPT_INT_FE			0x0200
-#define GPT_INT_RE			0x0400
-
-/*
- * TIMER_STATUS register settings
- */
-
-#define GPT_STS_MATCH			0x0001
-#define GPT_STS_FE			0x0002
-#define GPT_STS_RE			0x0004
-
-/*
- * TIMER_COMPARE register settings
- */
-
-#define GPT_FREE_RUNNING		0xFFFF
-
-/* Timer, HZ specific defines */
-#define CONFIG_SPEAR_HZ			1000
-#define CONFIG_SPEAR_HZ_CLOCK		8300000
-
-#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h
deleted file mode 100644
index c1a30e2..0000000
--- a/arch/arm/include/asm/arch-spear/spr_misc.h
+++ /dev/null
@@ -1,257 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#ifndef _SPR_MISC_H
-#define _SPR_MISC_H
-
-struct misc_regs {
-	u32 auto_cfg_reg;	/* 0x0 */
-	u32 armdbg_ctr_reg;	/* 0x4 */
-	u32 pll1_cntl;		/* 0x8 */
-	u32 pll1_frq;		/* 0xc */
-	u32 pll1_mod;		/* 0x10 */
-	u32 pll2_cntl;		/* 0x14 */
-	u32 pll2_frq;		/* 0x18 */
-	u32 pll2_mod;		/* 0x1C */
-	u32 pll_ctr_reg;	/* 0x20 */
-	u32 amba_clk_cfg;	/* 0x24 */
-	u32 periph_clk_cfg;	/* 0x28 */
-	u32 periph1_clken;	/* 0x2C */
-	u32 soc_core_id;	/* 0x30 */
-	u32 ras_clken;		/* 0x34 */
-	u32 periph1_rst;	/* 0x38 */
-	u32 periph2_rst;	/* 0x3C */
-	u32 ras_rst;		/* 0x40 */
-	u32 prsc1_clk_cfg;	/* 0x44 */
-	u32 prsc2_clk_cfg;	/* 0x48 */
-	u32 prsc3_clk_cfg;	/* 0x4C */
-	u32 amem_cfg_ctrl;	/* 0x50 */
-	u32 expi_clk_cfg;	/* 0x54 */
-	u32 reserved_1;		/* 0x58 */
-	u32 clcd_synth_clk;	/* 0x5C */
-	u32 irda_synth_clk;	/* 0x60 */
-	u32 uart_synth_clk;	/* 0x64 */
-	u32 gmac_synth_clk;	/* 0x68 */
-	u32 ras_synth1_clk;	/* 0x6C */
-	u32 ras_synth2_clk;	/* 0x70 */
-	u32 ras_synth3_clk;	/* 0x74 */
-	u32 ras_synth4_clk;	/* 0x78 */
-	u32 arb_icm_ml1;	/* 0x7C */
-	u32 arb_icm_ml2;	/* 0x80 */
-	u32 arb_icm_ml3;	/* 0x84 */
-	u32 arb_icm_ml4;	/* 0x88 */
-	u32 arb_icm_ml5;	/* 0x8C */
-	u32 arb_icm_ml6;	/* 0x90 */
-	u32 arb_icm_ml7;	/* 0x94 */
-	u32 arb_icm_ml8;	/* 0x98 */
-	u32 arb_icm_ml9;	/* 0x9C */
-	u32 dma_src_sel;	/* 0xA0 */
-	u32 uphy_ctr_reg;	/* 0xA4 */
-	u32 gmac_ctr_reg;	/* 0xA8 */
-	u32 port_bridge_ctrl;	/* 0xAC */
-	u32 reserved_2[4];	/* 0xB0--0xBC */
-	u32 prc1_ilck_ctrl_reg;	/* 0xC0 */
-	u32 prc2_ilck_ctrl_reg;	/* 0xC4 */
-	u32 prc3_ilck_ctrl_reg;	/* 0xC8 */
-	u32 prc4_ilck_ctrl_reg;	/* 0xCC */
-	u32 prc1_intr_ctrl_reg;	/* 0xD0 */
-	u32 prc2_intr_ctrl_reg;	/* 0xD4 */
-	u32 prc3_intr_ctrl_reg;	/* 0xD8 */
-	u32 prc4_intr_ctrl_reg;	/* 0xDC */
-	u32 powerdown_cfg_reg;	/* 0xE0 */
-	u32 ddr_1v8_compensation;	/* 0xE4  */
-	u32 ddr_2v5_compensation;	/* 0xE8 */
-	u32 core_3v3_compensation;	/* 0xEC */
-	u32 ddr_pad;		/* 0xF0 */
-	u32 bist1_ctr_reg;	/* 0xF4 */
-	u32 bist2_ctr_reg;	/* 0xF8 */
-	u32 bist3_ctr_reg;	/* 0xFC */
-	u32 bist4_ctr_reg;	/* 0x100 */
-	u32 bist5_ctr_reg;	/* 0x104 */
-	u32 bist1_rslt_reg;	/* 0x108 */
-	u32 bist2_rslt_reg;	/* 0x10C */
-	u32 bist3_rslt_reg;	/* 0x110 */
-	u32 bist4_rslt_reg;	/* 0x114 */
-	u32 bist5_rslt_reg;	/* 0x118 */
-	u32 syst_error_reg;	/* 0x11C */
-	u32 reserved_3[0x1FB8];	/* 0x120--0x7FFC */
-	u32 ras_gpp1_in;	/* 0x8000 */
-	u32 ras_gpp2_in;	/* 0x8004 */
-	u32 ras_gpp1_out;	/* 0x8008 */
-	u32 ras_gpp2_out;	/* 0x800C */
-};
-
-/* SYNTH_CLK value*/
-#define SYNTH23			0x00020003
-
-/* PLLx_FRQ value */
-#if defined(CONFIG_SPEAR600)
-#define FREQ_332		0xA600010F
-#define FREQ_266		0x8500010F
-#endif
-
-/* PLL_CTR_REG   */
-#define MEM_CLK_SEL_MSK		0x70000000
-#define MEM_CLK_HCLK		0x00000000
-#define MEM_CLK_2HCLK		0x10000000
-#define MEM_CLK_PLL2		0x30000000
-
-#define EXPI_CLK_CFG_LOW_COMPR	0x2000
-#define EXPI_CLK_CFG_CLK_EN	0x0400
-#define EXPI_CLK_CFG_RST	0x0200
-#define EXPI_CLK_SYNT_EN	0x0010
-#define EXPI_CLK_CFG_SEL_PLL2	0x0004
-#define EXPI_CLK_CFG_INT_CLK_EN	0x0001
-
-#define PLL2_CNTL_6UA		0x1c00
-#define PLL2_CNTL_SAMPLE	0x0008
-#define PLL2_CNTL_ENABLE	0x0004
-#define PLL2_CNTL_RESETN	0x0002
-#define PLL2_CNTL_LOCK		0x0001
-
-/* AUTO_CFG_REG value */
-#define MISC_SOCCFGMSK                  0x0000003F
-#define MISC_SOCCFG30                   0x0000000C
-#define MISC_SOCCFG31                   0x0000000D
-#define MISC_NANDDIS			0x00020000
-
-/* PERIPH_CLK_CFG value */
-#define MISC_GPT3SYNTH			0x00000400
-#define MISC_GPT4SYNTH			0x00000800
-#define CONFIG_SPEAR_UART48M		0
-#define CONFIG_SPEAR_UARTCLKMSK		(0x1 << 4)
-
-/* PRSC_CLK_CFG value */
-/*
- * Fout = Fin / (2^(N+1) * (M + 1))
- */
-#define MISC_PRSC_N_1			0x00001000
-#define MISC_PRSC_M_9			0x00000009
-#define MISC_PRSC_N_4			0x00004000
-#define MISC_PRSC_M_399			0x0000018F
-#define MISC_PRSC_N_6			0x00006000
-#define MISC_PRSC_M_2593		0x00000A21
-#define MISC_PRSC_M_124			0x0000007C
-#define MISC_PRSC_CFG			(MISC_PRSC_N_1 | MISC_PRSC_M_9)
-
-/* PERIPH1_CLKEN, PERIPH1_RST value */
-#define MISC_USBDENB			0x01000000
-#define MISC_ETHENB			0x00800000
-#define MISC_SMIENB			0x00200000
-#define MISC_GPIO3ENB			0x00040000
-#define MISC_GPT3ENB			0x00010000
-#define MISC_SSP3ENB			0x00004000
-#define MISC_GPIO4ENB			0x00002000
-#define MISC_GPT2ENB			0x00000800
-#define MISC_FSMCENB			0x00000200
-#define MISC_I2CENB			0x00000080
-#define MISC_SSP2ENB			0x00000040
-#define MISC_SSP1ENB			0x00000020
-#define MISC_UART0ENB			0x00000008
-
-/*   PERIPH_CLK_CFG   */
-#define  XTALTIMEEN		0x00000001
-#define  PLLTIMEEN		0x00000002
-#define  CLCDCLK_SYNTH		0x00000000
-#define  CLCDCLK_48MHZ		0x00000004
-#define  CLCDCLK_EXT		0x00000008
-#define  UARTCLK_MASK		(0x1 << 4)
-#define  UARTCLK_48MHZ		0x00000000
-#define  UARTCLK_SYNTH		0x00000010
-#define  IRDACLK_48MHZ		0x00000000
-#define  IRDACLK_SYNTH		0x00000020
-#define  IRDACLK_EXT		0x00000040
-#define  RTC_DISABLE		0x00000080
-#define  GPT1CLK_48MHZ		0x00000000
-#define  GPT1CLK_SYNTH		0x00000100
-#define  GPT2CLK_48MHZ		0x00000000
-#define  GPT2CLK_SYNTH		0x00000200
-#define  GPT3CLK_48MHZ		0x00000000
-#define  GPT3CLK_SYNTH		0x00000400
-#define  GPT4CLK_48MHZ		0x00000000
-#define  GPT4CLK_SYNTH		0x00000800
-#define  GPT5CLK_48MHZ		0x00000000
-#define  GPT5CLK_SYNTH		0x00001000
-#define  GPT1_FREEZE		0x00002000
-#define  GPT2_FREEZE		0x00004000
-#define  GPT3_FREEZE		0x00008000
-#define  GPT4_FREEZE		0x00010000
-#define  GPT5_FREEZE		0x00020000
-
-/*  PERIPH1_CLKEN bits  */
-#define PERIPH_ARM1_WE		0x00000001
-#define PERIPH_ARM1		0x00000002
-#define PERIPH_ARM2		0x00000004
-#define PERIPH_UART1		0x00000008
-#define PERIPH_UART2		0x00000010
-#define PERIPH_SSP1		0x00000020
-#define PERIPH_SSP2		0x00000040
-#define PERIPH_I2C		0x00000080
-#define PERIPH_JPEG		0x00000100
-#define PERIPH_FSMC		0x00000200
-#define PERIPH_FIRDA		0x00000400
-#define PERIPH_GPT4		0x00000800
-#define PERIPH_GPT5		0x00001000
-#define PERIPH_GPIO4		0x00002000
-#define PERIPH_SSP3		0x00004000
-#define PERIPH_ADC		0x00008000
-#define PERIPH_GPT3		0x00010000
-#define PERIPH_RTC		0x00020000
-#define PERIPH_GPIO3		0x00040000
-#define PERIPH_DMA		0x00080000
-#define PERIPH_ROM		0x00100000
-#define PERIPH_SMI		0x00200000
-#define PERIPH_CLCD		0x00400000
-#define PERIPH_GMAC		0x00800000
-#define PERIPH_USBD		0x01000000
-#define PERIPH_USBH1		0x02000000
-#define PERIPH_USBH2		0x04000000
-#define PERIPH_MPMC		0x08000000
-#define PERIPH_RAMW		0x10000000
-#define PERIPH_MPMC_EN		0x20000000
-#define PERIPH_MPMC_WE		0x40000000
-#define PERIPH_MPMCMSK		0x60000000
-
-#define PERIPH_CLK_ALL		0x0FFFFFF8
-#define PERIPH_RST_ALL		0x00000004
-
-/* DDR_PAD values */
-#define DDR_PAD_CNF_MSK		0x0000ffff
-#define DDR_PAD_SW_CONF		0x00060000
-#define DDR_PAD_SSTL_SEL	0x00000001
-#define DDR_PAD_DRAM_TYPE	0x00008000
-
-/* DDR_COMP values */
-#define DDR_COMP_ACCURATE	0x00000010
-
-/* SoC revision stuff */
-#define SOC_PRI_SHFT		16
-#define SOC_SEC_SHFT		8
-
-/* Revision definitions */
-#define SOC_SPEAR_NA		0
-
-/*
- * The definitons have started from
- * 101 for SPEAr6xx
- * 201 for SPEAr3xx
- * 301 for SPEAr13xx
- */
-#define SOC_SPEAR600_AA		101
-#define SOC_SPEAR600_AB		102
-#define SOC_SPEAR600_BA		103
-#define SOC_SPEAR600_BB		104
-#define SOC_SPEAR600_BC		105
-#define SOC_SPEAR600_BD		106
-
-#define SOC_SPEAR300		201
-#define SOC_SPEAR310		202
-#define SOC_SPEAR320		203
-
-extern int get_socrev(void);
-int fsmc_nand_switch_ecc(uint32_t eccstrength);
-
-#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_ssp.h b/arch/arm/include/asm/arch-spear/spr_ssp.h
deleted file mode 100644
index 088d34b..0000000
--- a/arch/arm/include/asm/arch-spear/spr_ssp.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- */
-
-#ifndef _SPR_SSP_H
-#define _SPR_SSP_H
-
-struct ssp_regs {
-	u32 sspcr0;
-	u32 sspcr1;
-	u32 sspdr;
-	u32 sspsr;
-	u32 sspcpsr;
-	u32 sspimsc;
-	u32 sspicr;
-	u32 sspdmacr;
-};
-
-#define SSPCR0_FRF_MOT_SPI	0x0000
-#define SSPCR0_DSS_16BITS	0x000f
-
-#define SSPCR1_SSE		0x0002
-
-#define SSPSR_TNF		0x2
-#define SSPSR_TFE		0x1
-
-#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_syscntl.h b/arch/arm/include/asm/arch-spear/spr_syscntl.h
deleted file mode 100644
index 6a83d87..0000000
--- a/arch/arm/include/asm/arch-spear/spr_syscntl.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009
- * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
- */
-
-#ifndef __SYSCTRL_H
-#define __SYSCTRL_H
-
-struct syscntl_regs {
-	u32 scctrl;
-	u32 scsysstat;
-	u32 scimctrl;
-	u32 scimsysstat;
-	u32 scxtalctrl;
-	u32 scpllctrl;
-	u32 scpllfctrl;
-	u32 scperctrl0;
-	u32 scperctrl1;
-	u32 scperen;
-	u32 scperdis;
-	const u32 scperclken;
-	const u32 scperstat;
-};
-
-#define MODE_SHIFT          0x00000003
-
-#define NORMAL              0x00000004
-#define SLOW                0x00000002
-#define DOZE                0x00000001
-#define SLEEP               0x00000000
-
-#define PLL_TIM             0x01FFFFFF
-
-#endif
diff --git a/board/spear/spear600/Kconfig b/board/spear/spear600/Kconfig
deleted file mode 100644
index d562e64..0000000
--- a/board/spear/spear600/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_SPEAR600
-
-config SYS_BOARD
-	default "spear600"
-
-config SYS_VENDOR
-	default "spear"
-
-config SYS_SOC
-	default "spear"
-
-config SYS_CONFIG_NAME
-	default "spear6xx_evb"
-
-endif
diff --git a/board/spear/spear600/MAINTAINERS b/board/spear/spear600/MAINTAINERS
deleted file mode 100644
index ddcd11a..0000000
--- a/board/spear/spear600/MAINTAINERS
+++ /dev/null
@@ -1,13 +0,0 @@
-SPEAR600 BOARD
-M:	Vipin Kumar <vipin.kumar@st.com>
-S:	Maintained
-F:	board/spear/spear600/
-F:	include/configs/spear6xx_evb.h
-F:	configs/spear600_defconfig
-
-SPEAR600_NAND BOARD
-#M:	-
-S:	Maintained
-F:	configs/spear600_nand_defconfig
-F:	configs/spear600_usbtty_defconfig
-F:	configs/spear600_usbtty_nand_defconfig
diff --git a/board/spear/spear600/Makefile b/board/spear/spear600/Makefile
deleted file mode 100644
index d25163e..0000000
--- a/board/spear/spear600/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= spear600.o
diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c
deleted file mode 100644
index 4706c52..0000000
--- a/board/spear/spear600/spear600.c
+++ /dev/null
@@ -1,56 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <net.h>
-#include <netdev.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <linux/mtd/fsmc_nand.h>
-#include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
-
-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-
-int board_init(void)
-{
-	return spear_board_init(MACH_TYPE_SPEAR600);
-}
-
-/*
- * board_nand_init - Board specific NAND initialization
- * @nand:	mtd private chip structure
- *
- * Called by nand_init_chip to initialize the board specific functions
- */
-
-void board_nand_init()
-{
-	struct misc_regs *const misc_regs_p =
-	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	struct nand_chip *nand = &nand_chip[0];
-
-#if defined(CONFIG_NAND_FSMC)
-	if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
-		fsmc_nand_init(nand);
-#endif
-	return;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	int ret = 0;
-
-#if defined(CONFIG_ETH_DESIGNWARE)
-	u32 interface = PHY_INTERFACE_MODE_MII;
-	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
-		ret++;
-#endif
-	return ret;
-}
diff --git a/board/spear/x600/Kconfig b/board/spear/x600/Kconfig
deleted file mode 100644
index 59f2b1e..0000000
--- a/board/spear/x600/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-if TARGET_X600
-
-config SPL_LDSCRIPT
-	default "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
-
-config SYS_BOARD
-	default "x600"
-
-config SYS_VENDOR
-	default "spear"
-
-config SYS_SOC
-	default "spear"
-
-config SYS_CONFIG_NAME
-	default "x600"
-
-endif
diff --git a/board/spear/x600/MAINTAINERS b/board/spear/x600/MAINTAINERS
deleted file mode 100644
index bff6824..0000000
--- a/board/spear/x600/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-X600 BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/spear/x600/
-F:	include/configs/x600.h
-F:	configs/x600_defconfig
diff --git a/board/spear/x600/Makefile b/board/spear/x600/Makefile
deleted file mode 100644
index 3ed8415..0000000
--- a/board/spear/x600/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-ifdef CONFIG_SPL_BUILD
-# necessary to create built-in.o
-obj- := __dummy__.o
-else
-obj-y	:= fpga.o x600.o
-endif
diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c
deleted file mode 100644
index 5140694..0000000
--- a/board/spear/x600/fpga.c
+++ /dev/null
@@ -1,265 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <log.h>
-#include <spartan3.h>
-#include <command.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_ssp.h>
-#include <linux/delay.h>
-
-/*
- * FPGA program pin configuration on X600:
- *
- * Only PROG and DONE are connected to GPIOs. INIT is not connected to the
- * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
- * 16bit serial writes via this SSP port to write the data bits into the
- * FPGA.
- */
-#define CONFIG_SYS_FPGA_PROG		2
-#define CONFIG_SYS_FPGA_DONE		3
-
-/*
- * Set the active-low FPGA reset signal.
- */
-static void fpga_reset(int assert)
-{
-	/*
-	 * On x600 we have no means to toggle the FPGA reset signal
-	 */
-	debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
-}
-
-/*
- * Set the FPGA's active-low SelectMap program line to the specified level
- */
-static int fpga_pgm_fn(int assert, int flush, int cookie)
-{
-	debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
-
-	gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
-
-	return assert;
-}
-
-/*
- * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
- * asserted (low).
- */
-static int fpga_init_fn(int cookie)
-{
-	static int state;
-
-	debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
-
-	/*
-	 * On x600, the FPGA INIT signal is not connected to the SoC.
-	 * We can't read the INIT status. Let's return the "correct"
-	 * INIT signal state generated via a local state-machine.
-	 */
-	if (++state == 1) {
-		return 1;
-	} else {
-		state = 0;
-		return 0;
-	}
-}
-
-/*
- * Test the state of the active-high FPGA DONE pin
- */
-static int fpga_done_fn(int cookie)
-{
-	struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
-
-	/*
-	 * Wait for Tx-FIFO to become empty before looking for DONE
-	 */
-	while (!(readl(&ssp->sspsr) & SSPSR_TFE))
-		;
-
-	if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
-		return 1;
-	else
-		return 0;
-}
-
-/*
- * FPGA pre-configuration function. Just make sure that
- * FPGA reset is asserted to keep the FPGA from starting up after
- * configuration.
- */
-static int fpga_pre_config_fn(int cookie)
-{
-	debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
-	fpga_reset(true);
-
-	return 0;
-}
-
-/*
- * FPGA post configuration function. Blip the FPGA reset line and then see if
- * the FPGA appears to be running.
- */
-static int fpga_post_config_fn(int cookie)
-{
-	int rc = 0;
-
-	debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
-
-	fpga_reset(true);
-	udelay(100);
-	fpga_reset(false);
-	udelay(100);
-
-	return rc;
-}
-
-static int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-	/*
-	 * No dedicated clock signal on x600 (data & clock generated)
-	 * in SSP interface. So we don't have to do anything here.
-	 */
-	return assert_clk;
-}
-
-static int fpga_wr_fn(int assert_write, int flush, int cookie)
-{
-	struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
-	static int count;
-	static u16 data;
-
-	/*
-	 * First collect 16 bits of data
-	 */
-	data = data << 1;
-	if (assert_write)
-		data |= 1;
-
-	/*
-	 * If 16 bits are not available, return for more bits
-	 */
-	count++;
-	if (count != 16)
-		return assert_write;
-
-	count = 0;
-
-	/*
-	 * Wait for Tx-FIFO to become ready
-	 */
-	while (!(readl(&ssp->sspsr) & SSPSR_TNF))
-		;
-
-	/* Send 16 bits to FPGA via SSP bus */
-	writel(data, &ssp->sspdr);
-
-	return assert_write;
-}
-
-static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
-	fpga_pre_config_fn,
-	fpga_pgm_fn,
-	fpga_clk_fn,
-	fpga_init_fn,
-	fpga_done_fn,
-	fpga_wr_fn,
-	fpga_post_config_fn,
-};
-
-static xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
-	XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
-};
-
-/*
- * Initialize the SelectMap interface.  We assume that the mode and the
- * initial state of all of the port pins have already been set!
- */
-static void fpga_serialslave_init(void)
-{
-	debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
-	fpga_pgm_fn(false, false, 0);	/* make sure program pin is inactive */
-}
-
-static int expi_setup(int freq)
-{
-	struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
-
-	pll2_m = (freq * 2) / 1000;
-	pll2_n = 15;
-	pll2_p = 1;
-	expi_x = 1;
-	expi_y = 2;
-
-	/*
-	 * Disable reset, Low compression, Disable retiming, Enable Expi,
-	 * Enable soft reset, DMA, PLL2, Internal
-	 */
-	writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
-	       EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
-	       EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
-	       &misc->expi_clk_cfg);
-
-	/*
-	 * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
-	 * Enable PLL2, Disable reset
-	 */
-	writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
-	writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
-	       PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
-
-	/*
-	 * Disable soft reset
-	 */
-	clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
-
-	return 0;
-}
-
-/*
- * Initialize the fpga
- */
-int x600_init_fpga(void)
-{
-	struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
-	struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-	/* Enable SSP2 clock */
-	writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
-	       &misc->periph1_clken);
-
-	/* Set EXPI clock to 45 MHz */
-	expi_setup(45000);
-
-	/* Configure GPIO directions */
-	gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
-	gpio_direction_input(CONFIG_SYS_FPGA_DONE);
-
-	writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
-	writel(SSPCR1_SSE, &ssp->sspcr1);
-
-	/*
-	 * Set lowest prescale divisor value (CPSDVSR) of 2 for max download
-	 * speed.
-	 *
-	 * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
-	 * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
-	 */
-	writel(2, &ssp->sspcpsr);
-
-	fpga_init();
-	fpga_serialslave_init();
-
-	debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
-	fpga_add(fpga_xilinx, &fpga[0]);
-
-	return 0;
-}
diff --git a/board/spear/x600/fpga.h b/board/spear/x600/fpga.h
deleted file mode 100644
index f5e6f31..0000000
--- a/board/spear/x600/fpga.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- */
-
-int x600_init_fpga(void);
diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c
deleted file mode 100644
index 9c30581..0000000
--- a/board/spear/x600/x600.c
+++ /dev/null
@@ -1,150 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <flash.h>
-#include <init.h>
-#include <micrel.h>
-#include <nand.h>
-#include <net.h>
-#include <netdev.h>
-#include <phy.h>
-#include <rtc.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
-#include <linux/mtd/fsmc_nand.h>
-#include "fpga.h"
-
-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-
-int board_init(void)
-{
-	/*
-	 * X600 is equipped with an M41T82 RTC. This RTC has the
-	 * HT bit (Halt Update), which needs to be cleared upon
-	 * power-up. Otherwise the RTC is halted.
-	 */
-	rtc_reset();
-
-	return spear_board_init(MACH_TYPE_SPEAR600);
-}
-
-int board_late_init(void)
-{
-	/*
-	 * Monitor and env protection on by default
-	 */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
-		      CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
-		      2 * CONFIG_ENV_SECT_SIZE - 1,
-		      &flash_info[0]);
-
-	/* Init FPGA subsystem */
-	x600_init_fpga();
-
-	return 0;
-}
-
-/*
- * board_nand_init - Board specific NAND initialization
- * @nand:	mtd private chip structure
- *
- * Called by nand_init_chip to initialize the board specific functions
- */
-
-void board_nand_init(void)
-{
-	struct misc_regs *const misc_regs_p =
-		(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	struct nand_chip *nand = &nand_chip[0];
-
-	if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
-		fsmc_nand_init(nand);
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-	unsigned short id1, id2;
-
-	/* check whether KSZ9031 or AR8035 has to be configured */
-	id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
-	id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
-
-	if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
-		/* PHY configuration for Micrel KSZ9031 */
-		printf("PHY KSZ9031 detected - ");
-
-		phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
-
-		/* control data pad skew - devaddr = 0x02, register = 0x04 */
-		ksz9031_phy_extended_write(phydev, 0x02,
-					   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
-					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					   0x0000);
-		/* rx data pad skew - devaddr = 0x02, register = 0x05 */
-		ksz9031_phy_extended_write(phydev, 0x02,
-					   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
-					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					   0x0000);
-		/* tx data pad skew - devaddr = 0x02, register = 0x05 */
-		ksz9031_phy_extended_write(phydev, 0x02,
-					   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
-					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					   0x0000);
-		/* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */
-		ksz9031_phy_extended_write(phydev, 0x02,
-					   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
-					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					   0x03FF);
-	} else {
-		/* PHY configuration for Vitesse VSC8641 */
-		printf("PHY VSC8641 detected - ");
-
-		/* Extended PHY control 1, select GMII */
-		phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
-
-		/* Software reset necessary after GMII mode selction */
-		phy_reset(phydev);
-
-		/* Enable extended page register access */
-		phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
-
-		/* 17e: Enhanced LED behavior, needs to be written twice */
-		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
-		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
-
-		/* 16e: Enhanced LED method select */
-		phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
-
-		/* Disable extended page register access */
-		phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
-
-		/* Enable clock output pin */
-		phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
-	}
-
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	int ret = 0;
-
-	if (designware_initialize(CONFIG_SPEAR_ETHBASE,
-				  PHY_INTERFACE_MODE_GMII) >= 0)
-		ret++;
-
-	return ret;
-}
diff --git a/configs/spear600_defconfig b/configs/spear600_defconfig
deleted file mode 100644
index 36c55eb..0000000
--- a/configs/spear600_defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_TARGET_SPEAR600=y
-CONFIG_SYS_TEXT_BASE=0x00700000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_IDENT_STRING="-SPEAr"
-CONFIG_SYS_EXTRA_OPTIONS="SPEAR600"
-CONFIG_BOOTDELAY=1
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyAMA0,115200 mem=128M root=/dev/mtdblock3 rootfstype=jffs2"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_MISC_INIT_R=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xF8040000
-CONFIG_SYS_I2C_DW=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_GIGE=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_CONS_INDEX=0
diff --git a/configs/spear600_nand_defconfig b/configs/spear600_nand_defconfig
deleted file mode 100644
index 9465fe1..0000000
--- a/configs/spear600_nand_defconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_TARGET_SPEAR600=y
-CONFIG_SYS_TEXT_BASE=0x00700000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x60000
-CONFIG_IDENT_STRING="-SPEAr"
-CONFIG_SYS_EXTRA_OPTIONS="SPEAR600"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyAMA0,115200 mem=128M root=/dev/mtdblock7 rootfstype=jffs2"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_MISC_INIT_R=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_I2C_DW=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_GIGE=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_CONS_INDEX=0
diff --git a/configs/spear600_usbtty_defconfig b/configs/spear600_usbtty_defconfig
deleted file mode 100644
index e83c748..0000000
--- a/configs/spear600_usbtty_defconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_TARGET_SPEAR600=y
-CONFIG_SYS_TEXT_BASE=0x00700000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_IDENT_STRING="-SPEAr"
-CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,USBTTY"
-CONFIG_BOOTDELAY=-1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyAMA0,115200 mem=128M root=/dev/mtdblock3 rootfstype=jffs2"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_MISC_INIT_R=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xF8040000
-CONFIG_SYS_I2C_DW=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_GIGE=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_CONS_INDEX=0
-CONFIG_USB=y
-CONFIG_USB_GADGET=y
diff --git a/configs/spear600_usbtty_nand_defconfig b/configs/spear600_usbtty_nand_defconfig
deleted file mode 100644
index ec3a440..0000000
--- a/configs/spear600_usbtty_nand_defconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_TARGET_SPEAR600=y
-CONFIG_SYS_TEXT_BASE=0x00700000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x60000
-CONFIG_IDENT_STRING="-SPEAr"
-CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,USBTTY"
-CONFIG_BOOTDELAY=-1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyAMA0,115200 mem=128M root=/dev/mtdblock7 rootfstype=jffs2"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_MISC_INIT_R=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_I2C_DW=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_GIGE=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_CONS_INDEX=0
-CONFIG_USB=y
-CONFIG_USB_GADGET=y
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
deleted file mode 100644
index 8fb29b3..0000000
--- a/configs/x600_defconfig
+++ /dev/null
@@ -1,71 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_SYS_THUMB_BUILD=y
-# CONFIG_SPL_USE_ARCH_MEMCPY is not set
-# CONFIG_SPL_USE_ARCH_MEMSET is not set
-CONFIG_TARGET_X600=y
-CONFIG_SYS_TEXT_BASE=0x00800040
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_TEXT_BASE=0xd2800b00
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xD2801FF8
-CONFIG_SPL=y
-CONFIG_IDENT_STRING="-SPEAr"
-CONFIG_BOOTDELAY=3
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="X600> "
-CONFIG_CMD_IMLS=y
-CONFIG_LOOPW=y
-CONFIG_CMD_MX_CYCLIC=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SAVES=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:64M(ubi0),64M(ubi1)"
-CONFIG_CMD_UBI=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xF8060000
-CONFIG_ENV_ADDR_REDUND=0xF8070000
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_SPARTAN3=y
-CONFIG_SYS_I2C_DW=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_RTC_M41T62=y
-CONFIG_CONS_INDEX=0
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
diff --git a/doc/README.spear b/doc/README.spear
deleted file mode 100644
index 0789b3f..0000000
--- a/doc/README.spear
+++ /dev/null
@@ -1,74 +0,0 @@
-
-SPEAr (Structured Processor Enhanced Architecture).
-
-SPEAr600 is also known as SPEArPlus and SPEAr300 is also known as SPEArBasic
-
-The SPEAr SoC family embeds a customizable logic that can be programmed
-one-time by a customer at silicon mask level (i.e. not at runtime!).
-
-U-Boot supports four SoCs: SPEAr600, SPEAr3xx
-
-All 4 SoCs (SPEAr3xx and SPEAr600) share common peripherals. SPEAr300 and
-SPEAr600 do not have EMI.
-
-1. ARM926ejs core based (sp600 has two cores, the 2nd handled only in Linux)
-2. FastEthernet (sp600 has Gbit version, but same controller - GMAC)
-3. USB Host
-4. USB Device
-5. NAND controller (FSMC)
-6. Serial NOR ctrl
-7. I2C
-8. SPI
-9. CLCD
-10. others ..
-
-Everything is supported in Linux.
-u-boot is currently not supporting all peripeharls (just a few as listed below).
-1. USB Device
-2. NAND controller (FSMC)
-3. Serial Memory Interface
-4. EMI (Parallel NOR interface)
-4. I2C
-5. UART
-
-Build options
-	make spear320_config
-		spear320 build with environment variables placed at default
-		location i.e. Serial NOR device
-	make spear320_pnor_config
-		This option generates a uboot image that supports emi controller
-		for CFI compliant parallel NOR flash. Environment variables are
-		placed in Parallel NOR device
-	make spear320_nand_config
-		spear320 build with environment variables placed in NAND device
-	make spear320_usbtty_config
-		spear320 build with usbtty terminal as default and environment
-		placed at default location
-	make spear320_usbtty_pnor_config
-		spear320 build with usbtty terminal as default and environment
-		placed in pnor device
-	make spear320_usbtty_nand_config
-		Build with usbtty terminal as default and environment placed in
-		NAND device
-	make spear300_config
-	make spear300_nand_config
-	make spear300_usbtty_config
-	make spear300_usbtty_nand_config
-	make spear310_config
-	make spear310_pnor_config
-	make spear310_nand_config
-	make spear310_usbtty_config
-	make spear310_usbtty_pnor_config
-	make spear310_usbtty_nand_config
-	make spear600_config
-	make spear600_nand_config
-	make spear600_usbtty_config
-	make spear600_usbtty_nand_config
-
-Mac id storage and retrieval in spear platforms
-
-Please read doc/README.enetaddr for the implementation guidelines for mac id
-usage. Basically, environment has precedence over board specific storage. The
-ethaddr beeing used for the network interface is always taken only from
-environment variables. Although, we can check the mac id programmed in i2c
-memory by using chip_config command
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 8541ba0..06dfc32 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -33,7 +33,6 @@ obj-$(CONFIG_RCAR_GPIO)		+= gpio-rcar.o
 obj-$(CONFIG_RZA1_GPIO)		+= gpio-rza1.o
 obj-$(CONFIG_S5P)		+= s5p_gpio.o
 obj-$(CONFIG_SANDBOX_GPIO)	+= sandbox.o
-obj-$(CONFIG_SPEAR_GPIO)	+= spear_gpio.o
 obj-$(CONFIG_TEGRA_GPIO)	+= tegra_gpio.o
 obj-$(CONFIG_TEGRA186_GPIO)	+= tegra186_gpio.o
 obj-$(CONFIG_DA8XX_GPIO)	+= da8xx_gpio.o
diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
deleted file mode 100644
index 4e4cd12..0000000
--- a/drivers/gpio/spear_gpio.c
+++ /dev/null
@@ -1,89 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- */
-
-/*
- * Driver for SPEAr600 GPIO controller
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/arch/hardware.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <errno.h>
-
-static int gpio_direction(unsigned gpio,
-			  enum gpio_direction direction)
-{
-	struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
-	u32 val;
-
-	val = readl(&regs->gpiodir);
-
-	if (direction == GPIO_DIRECTION_OUT)
-		val |= 1 << gpio;
-	else
-		val &= ~(1 << gpio);
-
-	writel(val, &regs->gpiodir);
-
-	return 0;
-}
-
-int gpio_set_value(unsigned gpio, int value)
-{
-	struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
-
-	if (value)
-		writel(1 << gpio, &regs->gpiodata[DATA_REG_ADDR(gpio)]);
-	else
-		writel(0, &regs->gpiodata[DATA_REG_ADDR(gpio)]);
-
-	return 0;
-}
-
-int gpio_get_value(unsigned gpio)
-{
-	struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
-	u32 val;
-
-	val = readl(&regs->gpiodata[DATA_REG_ADDR(gpio)]);
-
-	return !!val;
-}
-
-int gpio_request(unsigned gpio, const char *label)
-{
-	if (gpio >= SPEAR_GPIO_COUNT)
-		return -EINVAL;
-
-	return 0;
-}
-
-int gpio_free(unsigned gpio)
-{
-	return 0;
-}
-
-void gpio_toggle_value(unsigned gpio)
-{
-	gpio_set_value(gpio, !gpio_get_value(gpio));
-}
-
-int gpio_direction_input(unsigned gpio)
-{
-	return gpio_direction(gpio, GPIO_DIRECTION_IN);
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-	int ret = gpio_direction(gpio, GPIO_DIRECTION_OUT);
-
-	if (ret < 0)
-		return ret;
-
-	gpio_set_value(gpio, value);
-	return 0;
-}
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index de57ab9..35d6e2c 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -136,16 +136,6 @@ config SYS_I2C_DW
 	  controller is used in various SoCs, e.g. the ST SPEAr, Altera
 	  SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
 
-config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
-	bool "DW I2C Enable Status Register not supported"
-	depends on SYS_I2C_DW && \
-		(TARGET_SPEAR600 || TARGET_X600)
-	default y
-	help
-	  Some versions of the Designware I2C controller do not support the
-	  enable status register. This config option can be enabled in such
-	  cases.
-
 config SYS_I2C_ASPEED
 	bool "Aspeed I2C Controller"
 	depends on DM_I2C && ARCH_ASPEED
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 0728036..e57eed0 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -24,16 +24,6 @@
  */
 #define DW_I2C_COMP_TYPE	0x44570140
 
-#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
-static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
-{
-	u32 ena = enable ? IC_ENABLE_0B : 0;
-
-	writel(ena, &i2c_base->ic_enable);
-
-	return 0;
-}
-#else
 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
 {
 	u32 ena = enable ? IC_ENABLE_0B : 0;
@@ -55,7 +45,6 @@ static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
 
 	return -ETIMEDOUT;
 }
-#endif
 
 /* High and low times in different speed modes (in ns) */
 enum {
diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c
index 1f4c74f..1c24710 100644
--- a/drivers/mtd/nand/raw/fsmc_nand.c
+++ b/drivers/mtd/nand/raw/fsmc_nand.c
@@ -389,55 +389,6 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 	return 0;
 }
 
-#ifndef CONFIG_SPL_BUILD
-/*
- * fsmc_nand_switch_ecc - switch the ECC operation between different engines
- *
- * @eccstrength		- the number of bits that could be corrected
- *			  (1 - HW, 4 - SW BCH4)
- */
-int fsmc_nand_switch_ecc(uint32_t eccstrength)
-{
-	struct nand_chip *nand;
-	struct mtd_info *mtd;
-	int err;
-
-	/*
-	 * This functions is only called on SPEAr600 platforms, supporting
-	 * 1 bit HW ECC. The BCH8 HW ECC (FSMC_VER8) from the ST-Ericsson
-	 * Nomadik SoC is currently supporting this fsmc_nand_switch_ecc()
-	 * function, as it doesn't need to switch to a different ECC layout.
-	 */
-	mtd = get_nand_dev_by_index(nand_curr_device);
-	nand = mtd_to_nand(mtd);
-
-	/* Setup the ecc configurations again */
-	if (eccstrength == 1) {
-		nand->ecc.mode = NAND_ECC_HW;
-		nand->ecc.bytes = 3;
-		nand->ecc.strength = 1;
-		nand->ecc.layout = &fsmc_ecc1_layout;
-		nand->ecc.calculate = fsmc_read_hwecc;
-		nand->ecc.correct = nand_correct_data;
-	} else if (eccstrength == 4) {
-		/*
-		 * .calculate .correct and .bytes will be set in
-		 * nand_scan_tail()
-		 */
-		nand->ecc.mode = NAND_ECC_SOFT_BCH;
-		nand->ecc.strength = 4;
-		nand->ecc.layout = NULL;
-	} else {
-		printf("Error: ECC strength %d not supported!\n", eccstrength);
-	}
-
-	/* Update NAND handling after ECC mode switch */
-	err = nand_scan_tail(mtd);
-
-	return err;
-}
-#endif /* CONFIG_SPL_BUILD */
-
 int fsmc_nand_init(struct nand_chip *nand)
 {
 	static int chip_nr;
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index a12e8f2..eb6fe9f 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -36,7 +36,6 @@ obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
 obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
 obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o
 obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
-obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
 obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c
deleted file mode 100644
index 3e87e0c..0000000
--- a/drivers/usb/host/ehci-spear.c
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Armando Visconti, ST Micoelectronics, <armando.visconti@st.com>.
- *
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <usb.h>
-#include <linux/delay.h>
-#include "ehci.h"
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_misc.h>
-
-static void spear6xx_usbh_stop(void)
-{
-	struct misc_regs *const misc_p =
-	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	u32 periph1_rst = readl(misc_p->periph1_rst);
-
-	periph1_rst |= PERIPH_USBH1 | PERIPH_USBH2;
-	writel(periph1_rst, misc_p->periph1_rst);
-
-	udelay(1000);
-	periph1_rst &= ~(PERIPH_USBH1 | PERIPH_USBH2);
-	writel(periph1_rst, misc_p->periph1_rst);
-}
-
-/*
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
-int ehci_hcd_init(int index, enum usb_init_type init,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	u32 ehci = 0;
-
-	switch (index) {
-	case 0:
-		ehci = CONFIG_SYS_UHC0_EHCI_BASE;
-		break;
-	case 1:
-		ehci = CONFIG_SYS_UHC1_EHCI_BASE;
-		break;
-	default:
-		printf("ERROR: wrong controller index!\n");
-		break;
-	};
-
-	*hccr = (struct ehci_hccr *)(ehci + 0x100);
-	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
-			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-
-	debug("SPEAr-ehci: init hccr %x and hcor %x hc_length %d\n",
-		(uint32_t)*hccr, (uint32_t)*hcor,
-		(uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-
-	return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding
- * the the EHCI host controller.
- */
-int ehci_hcd_stop(int index)
-{
-#if defined(CONFIG_SPEAR600)
-	spear6xx_usbh_stop();
-#endif
-
-	return 0;
-}
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
deleted file mode 100644
index d77ea60..0000000
--- a/include/configs/spear-common.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009
- * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
- */
-
-#ifndef _SPEAR_COMMON_H
-#define _SPEAR_COMMON_H
-/*
- * Common configurations used for both spear3xx as well as spear6xx
- */
-
-/* U-Boot Load Address */
-
-/* Ethernet driver configuration */
-#define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
-
-/* USBD driver configuration */
-#if defined(CONFIG_SPEAR_USBTTY)
-#define CONFIG_DW_UDC
-#define CONFIG_USB_DEVICE
-#define CONFIG_USBD_HS
-#define CONFIG_USB_TTY
-
-#define CONFIG_USBD_PRODUCT_NAME		"SPEAr SoC"
-#define CONFIG_USBD_MANUFACTURER		"ST Microelectronics"
-
-#endif
-
-#define CONFIG_EXTRA_ENV_USBTTY			"usbtty=cdc_acm\0"
-
-/* I2C driver configuration */
-#define CONFIG_SYS_I2C
-#if defined(CONFIG_SPEAR600)
-#define CONFIG_SYS_I2C_BASE			0xD0200000
-#endif
-#define CONFIG_SYS_I2C_SPEED			400000
-#define CONFIG_SYS_I2C_SLAVE			0x02
-
-#define CONFIG_I2C_CHIPADDRESS			0x50
-
-/* Timer, HZ specific defines */
-
-/* Flash configuration */
-#if defined(CONFIG_FLASH_PNOR)
-#define CONFIG_SPEAR_EMI
-#else
-#define CONFIG_ST_SMI
-#endif
-
-#if defined(CONFIG_ST_SMI)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS		2
-#define CONFIG_SYS_FLASH_BASE			0xF8000000
-#define CONFIG_SYS_CS1_FLASH_BASE		0xF9000000
-#define CONFIG_SYS_FLASH_BANK_SIZE		0x01000000
-#define CONFIG_SYS_FLASH_ADDR_BASE		{CONFIG_SYS_FLASH_BASE, \
-						CONFIG_SYS_CS1_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_SECT		128
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)
-
-#endif
-
-/*
- * Serial Configuration (PL011)
- * CONFIG_PL01x_PORTS is defined in specific files
- */
-#define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
-#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
-						57600, 115200 }
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/* NAND FLASH Configuration */
-#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_NAND_FSMC
-#define CONFIG_SYS_MAX_NAND_DEVICE		1
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/*
- * Default Environment Varible definitions
- */
-
-/*
- * U-Boot Environment placing definitions.
- */
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-#ifdef CONFIG_ST_SMI
-/*
- * Environment is in serial NOR flash
- */
-#define CONFIG_SYS_MONITOR_LEN			0x00040000
-#define CONFIG_FSMTDBLK				"/dev/mtdblock3 "
-
-#define CONFIG_BOOTCOMMAND			"bootm 0xf8050000"
-
-#elif defined(CONFIG_SPEAR_EMI)
-/*
- * Environment is in parallel NOR flash
- */
-#define CONFIG_SYS_MONITOR_LEN			0x00060000
-#define CONFIG_FSMTDBLK				"/dev/mtdblock3 "
-
-#define CONFIG_BOOTCOMMAND			"cp.b 0x50080000 0x1600000 " \
-						"0x4C0000; bootm 0x1600000"
-#endif
-#elif defined(CONFIG_ENV_IS_IN_NAND)
-/*
- * Environment is in NAND
- */
-
-#define CONFIG_ENV_RANGE			0x10000
-#define CONFIG_FSMTDBLK				"/dev/mtdblock7 "
-
-#define CONFIG_BOOTCOMMAND			"nand read.jffs2 0x1600000 " \
-						"0x80000 0x4C0000; " \
-						"bootm 0x1600000"
-#endif
-
-#define CONFIG_NFSBOOTCOMMAND						\
-	"bootp; "							\
-	"setenv bootargs root=/dev/nfs rw "				\
-	"nfsroot=$(serverip):$(rootpath) "				\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):"			\
-			"$(netmask):$(hostname):$(netdev):off "		\
-			"console=ttyAMA0,115200 $(othbootargs);"	\
-	"bootm; "
-
-#define CONFIG_RAMBOOTCOMMAND						\
-	"setenv bootargs root=/dev/ram rw "				\
-		"console=ttyAMA0,115200 $(othbootargs);"		\
-	CONFIG_BOOTCOMMAND
-
-#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_TEXT_BASE
-
-/* Miscellaneous configurable options */
-#define CONFIG_BOOT_PARAMS_ADDR			0x00000100
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-#define CONFIG_SYS_MALLOC_LEN			(1024*1024)
-#define CONFIG_SYS_LOAD_ADDR			0x00800000
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Physical Memory Map */
-#define PHYS_SDRAM_1				0x00000000
-#define PHYS_SDRAM_1_MAXSIZE			0x40000000
-
-#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR		0xD2800000
-#define CONFIG_SYS_INIT_RAM_SIZE		0x2000
-
-#define CONFIG_SYS_INIT_SP_OFFSET		\
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_INIT_SP_ADDR			\
-	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-#endif
diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h
deleted file mode 100644
index 4fedc9e..0000000
--- a/include/configs/spear6xx_evb.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009
- * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#if defined(CONFIG_USBTTY)
-#define CONFIG_SPEAR_USBTTY
-#endif
-
-#include <configs/spear-common.h>
-
-/* Serial Configuration (PL011) */
-#define CONFIG_SYS_SERIAL0			0xD0000000
-#define CONFIG_SYS_SERIAL1			0xD0080000
-#define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
-						(void *)CONFIG_SYS_SERIAL1 }
-
-/* NAND flash configuration */
-#define CONFIG_SYS_FSMC_NAND_SP
-#define CONFIG_SYS_FSMC_NAND_8BIT
-#define CONFIG_SYS_NAND_BASE			0xD2000000
-
-/* Ethernet PHY configuration */
-
-/* Environment Settings */
-#define CONFIG_EXTRA_ENV_SETTINGS              CONFIG_EXTRA_ENV_USBTTY
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/x600.h b/include/configs/x600.h
deleted file mode 100644
index 0dd5722..0000000
--- a/include/configs/x600.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2009, STMicroelectronics - All Rights Reserved
- * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
- *
- * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SPEAR600				/* SPEAr600 SoC */
-#define CONFIG_X600				/* on X600 board */
-
-#include <asm/arch/hardware.h>
-
-/* Timer, HZ specific defines */
-#define CONFIG_SYS_HZ_CLOCK			8300000
-
-#define CONFIG_SYS_FLASH_BASE			0xf8000000
-/* Reserve 8KiB for SPL */
-#define CONFIG_SPL_PAD_TO			8192	/* decimal for 'dd' */
-#define CONFIG_SYS_SPL_LEN			CONFIG_SPL_PAD_TO
-#define CONFIG_SYS_UBOOT_BASE			(CONFIG_SYS_FLASH_BASE + \
-						 CONFIG_SYS_SPL_LEN)
-#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN			0x60000
-
-/* Serial Configuration (PL011) */
-#define CONFIG_SYS_SERIAL0			0xD0000000
-#define CONFIG_SYS_SERIAL1			0xD0080000
-#define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
-						(void *)CONFIG_SYS_SERIAL1 }
-#define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
-#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
-						  57600, 115200 }
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/* NOR FLASH config options */
-#define CONFIG_ST_SMI
-#define CONFIG_SYS_MAX_FLASH_BANKS		1
-#define CONFIG_SYS_FLASH_BANK_SIZE		0x01000000
-#define CONFIG_SYS_FLASH_ADDR_BASE		{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_SECT		128
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)
-
-/* NAND FLASH config options */
-#define CONFIG_NAND_FSMC
-#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_SYS_MAX_NAND_DEVICE		1
-#define CONFIG_SYS_NAND_BASE			CONFIG_FSMC_NAND_BASE
-#define CONFIG_MTD_ECC_SOFT
-#define CONFIG_SYS_FSMC_NAND_8BIT
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_ECC_BCH
-
-/* UBI/UBI config options */
-
-/* Ethernet config options */
-#define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
-
-#define CONFIG_SPEAR_GPIO
-
-/* I2C config options */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_BASE			0xD0200000
-#define CONFIG_SYS_I2C_SPEED			400000
-#define CONFIG_SYS_I2C_SLAVE			0x02
-#define CONFIG_I2C_CHIPADDRESS			0x50
-
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-
-/* FPGA config options */
-#define CONFIG_FPGA_COUNT	1
-
-/* USB EHCI options */
-#define CONFIG_USB_EHCI_SPEAR
-#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
-
-/*
- * U-Boot Environment placing definitions.
- */
-
-/* Miscellaneous configurable options */
-#define CONFIG_BOOT_PARAMS_ADDR			0x00000100
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-#define CONFIG_SYS_MALLOC_LEN			(8 << 20)
-#define CONFIG_SYS_LOAD_ADDR			0x00800000
-
-#define CONFIG_HOSTNAME				"x600"
-#define CONFIG_UBI_PART				ubi0
-#define CONFIG_UBIFS_VOLUME			rootfs
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"u-boot_addr=1000000\0"						\
-	"u-boot=" CONFIG_HOSTNAME "/u-boot.spr\0"		\
-	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
-	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
-		" +${filesize};"					\
-		"erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
-		"cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
-		" ${filesize};"						\
-		"protect on " __stringify(CONFIG_SYS_MONITOR_BASE)	\
-		" +${filesize}\0"					\
-	"upd=run load update\0"						\
-	"ubifs=" CONFIG_HOSTNAME "/ubifs.img\0"		\
-	"part=" __stringify(CONFIG_UBI_PART) "\0"			\
-	"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0"			\
-	"load_ubifs=tftp ${kernel_addr} ${ubifs}\0"			\
-	"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}"	\
-		" ${filesize}\0"					\
-	"upd_ubifs=run load_ubifs update_ubifs\0"			\
-	"init_ubifs=nand erase.part ubi0;ubi part ${part};"		\
-		"ubi create ${vol} 4000000\0"				\
-	"netdev=eth0\0"							\
-	"rootpath=/opt/eldk-4.2/arm\0"					\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"boot_part=0\0"							\
-	"altbootcmd=if test $boot_part -eq 0;then "			\
-			"echo Switching to partition 1!;"		\
-			"setenv boot_part 1;"				\
-		"else; "						\
-			"echo Switching to partition 0!;"		\
-			"setenv boot_part 0;"				\
-		"fi;"							\
-		"saveenv;boot\0"					\
-	"ubifsargs=set bootargs ubi.mtd=ubi${boot_part} "		\
-		"root=ubi0:rootfs rootfstype=ubifs\0"			\
-	"kernel=" CONFIG_HOSTNAME "/uImage\0"		\
-	"kernel_fs=/boot/uImage \0"					\
-	"kernel_addr=1000000\0"						\
-	"dtb=" CONFIG_HOSTNAME "/"				\
-		CONFIG_HOSTNAME ".dtb\0"			\
-	"dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0"		\
-	"dtb_addr=1800000\0"						\
-	"load_kernel=tftp ${kernel_addr} ${kernel}\0"			\
-	"load_dtb=tftp ${dtb_addr} ${dtb}\0"				\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addcon=setenv bootargs ${bootargs} console=ttyAMA0,"		\
-		"${baudrate}\0"						\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
-	"net_nfs=run load_dtb load_kernel; "				\
-		"run nfsargs addip addcon addmtd addmisc;"		\
-		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
-	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"					\
-	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"				\
-	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip"		\
-		" addcon addmisc addmtd;"				\
-		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
-	"ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0"	\
-	"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};"		\
-		"ubifsload ${dtb_addr} ${dtb_fs};\0"			\
-	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon "	\
-		"addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0"	\
-	"bootcmd=run nand_ubifs\0"					\
-	"\0"
-
-/* Physical Memory Map */
-#define PHYS_SDRAM_1				0x00000000
-#define PHYS_SDRAM_1_MAXSIZE			0x40000000
-
-#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
-#define CONFIG_SRAM_BASE			0xd2800000
-/* Preserve the last 2 lwords for the boot-counter */
-#define CONFIG_SRAM_SIZE			((8 << 10) - 0x8)
-#define CONFIG_SYS_INIT_RAM_ADDR		CONFIG_SRAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET		\
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_INIT_SP_ADDR			\
-	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/*
- * SPL related defines
- */
-#define CONFIG_SPL_MAX_SIZE		(CONFIG_SRAM_SIZE - 0xb00)
-#define	CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/spear"
-
-/*
- * Please select/define only one of the following
- * Each definition corresponds to a supported DDR chip.
- * DDR configuration is based on the following selection
- */
-#define CONFIG_DDR_MT47H64M16		1
-#define CONFIG_DDR_MT47H32M16		0
-#define CONFIG_DDR_MT47H128M8		0
-
-/*
- * Synchronous/Asynchronous operation of DDR
- *
- * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
- * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
- * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
- */
-#define CONFIG_DDR_2HCLK		1
-#define CONFIG_DDR_HCLK			0
-#define CONFIG_DDR_PLL2			0
-
-/*
- * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
- * or not. Modify/Add to only these macros to define new boot types
- */
-#define USB_BOOT_SUPPORTED		0
-#define PCIE_BOOT_SUPPORTED		0
-#define SNOR_BOOT_SUPPORTED		1
-#define NAND_BOOT_SUPPORTED		1
-#define PNOR_BOOT_SUPPORTED		0
-#define TFTP_BOOT_SUPPORTED		0
-#define UART_BOOT_SUPPORTED		0
-#define SPI_BOOT_SUPPORTED		0
-#define I2C_BOOT_SUPPORTED		0
-#define MMC_BOOT_SUPPORTED		0
-
-#endif  /* __CONFIG_H */