Merge branch '2021-10-11-TI-platform-updates'

- Assorted TI platform updates

13 files changed, 382 insertions, 213 deletions

diff --git a/arch/arm/dts/am33xx-clocks.dtsi b/arch/arm/dts/am33xx-clocks.dtsi
index 9221824..44b6268 100644
--- a/arch/arm/dts/am33xx-clocks.dtsi
+++ b/arch/arm/dts/am33xx-clocks.dtsi
@@ -167,7 +167,7 @@
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-core-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-		reg = <0x0490>, <0x045c>, <0x0468>;
+		reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
 	};
 
 	dpll_core_x2_ck: dpll_core_x2_ck {
@@ -207,7 +207,7 @@
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-		reg = <0x0488>, <0x0420>, <0x042c>;
+		reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
 	};
 
 	dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
@@ -223,7 +223,7 @@
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-no-gate-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-		reg = <0x0494>, <0x0434>, <0x0440>;
+		reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
 	};
 
 	dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
@@ -247,7 +247,7 @@
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-no-gate-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-		reg = <0x0498>, <0x0448>, <0x0454>;
+		reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
 	};
 
 	dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
@@ -264,7 +264,7 @@
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-no-gate-j-type-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-		reg = <0x048c>, <0x0470>, <0x049c>;
+		reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
 	};
 
 	dpll_per_m2_ck: dpll_per_m2_ck@4ac {
diff --git a/arch/arm/dts/am43xx-clocks.dtsi b/arch/arm/dts/am43xx-clocks.dtsi
index d0c0dfa..b1127b5 100644
--- a/arch/arm/dts/am43xx-clocks.dtsi
+++ b/arch/arm/dts/am43xx-clocks.dtsi
@@ -199,7 +199,7 @@
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-core-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-		reg = <0x2d20>, <0x2d24>, <0x2d2c>;
+		reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
 	};
 
 	dpll_core_x2_ck: dpll_core_x2_ck {
@@ -245,7 +245,7 @@
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-		reg = <0x2d60>, <0x2d64>, <0x2d6c>;
+		reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
 	};
 
 	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
@@ -263,7 +263,7 @@
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-		reg = <0x2da0>, <0x2da4>, <0x2dac>;
+		reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
 	};
 
 	dpll_ddr_m2_ck: dpll_ddr_m2_ck {
@@ -281,7 +281,7 @@
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-		reg = <0x2e20>, <0x2e24>, <0x2e2c>;
+		reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
 	};
 
 	dpll_disp_m2_ck: dpll_disp_m2_ck {
@@ -300,7 +300,7 @@
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-j-type-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-		reg = <0x2de0>, <0x2de4>, <0x2dec>;
+		reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
 	};
 
 	dpll_per_m2_ck: dpll_per_m2_ck {
@@ -583,7 +583,7 @@
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-		reg = <0x2e60>, <0x2e64>, <0x2e6c>;
+		reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
 	};
 
 	dpll_extdev_m2_ck: dpll_extdev_m2_ck {
diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2-u-boot.dtsi
new file mode 100644
index 0000000..64dddce
--- /dev/null
+++ b/arch/arm/dts/k3-am65-iot2050-common-pg2-u-boot.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2018-2021
+ *
+ * Authors:
+ *   Chao Zeng <chao.zeng@siemens.com>
+ *
+ * U-Boot bits of the IOT2050 Advanced PG2 variants
+ * (downgrade of usb0 to USB 2.0 mode)
+ */
+
+&serdes0 {
+	status = "disabled";
+};
+
+&dwc3_0 {
+	assigned-clock-parents = <&k3_clks 151 4>,	/* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
+				 <&k3_clks 151 9>;	/* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
+	/delete-property/ phys;
+	/delete-property/ phy-names;
+};
+
+&usb0 {
+	maximum-speed = "high-speed";
+	/delete-property/ snps,dis-u1-entry-quirk;
+	/delete-property/ snps,dis-u2-entry-quirk;
+};
diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
index c25bce7..e7e0ca4 100644
--- a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi
@@ -44,8 +44,10 @@
 	phy-names = "usb3-phy";
 };
 
-&usb0_phy {
+&usb0 {
 	maximum-speed = "super-speed";
 	snps,dis-u1-entry-quirk;
 	snps,dis-u2-entry-quirk;
 };
+
+#include "k3-am65-iot2050-common-pg2-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
index 88c36fc..286e25f 100644
--- a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
@@ -35,7 +35,7 @@
 
 &cbass_main {
 	u-boot,dm-spl;
-	main-navss {
+	main_navss: bus@30800000 {
 		u-boot,dm-spl;
 	};
 };
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 5d77590..79e3b8c 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -78,6 +78,18 @@
 #define CM_CLKSEL_DPLL_N_SHIFT			0
 #define CM_CLKSEL_DPLL_N_MASK			0x7F
 
+/* CM_SSC_DELTAM_DPLL */
+#define CM_SSC_DELTAM_DPLL_FRAC_SHIFT		0
+#define CM_SSC_DELTAM_DPLL_FRAC_MASK		GENMASK(17, 0)
+#define CM_SSC_DELTAM_DPLL_INT_SHIFT		18
+#define CM_SSC_DELTAM_DPLL_INT_MASK		GENMASK(19, 18)
+
+/* CM_SSC_MODFREQ_DPLL */
+#define CM_SSC_MODFREQ_DPLL_MANT_SHIFT		0
+#define CM_SSC_MODFREQ_DPLL_MANT_MASK		GENMASK(6, 0)
+#define CM_SSC_MODFREQ_DPLL_EXP_SHIFT		7
+#define CM_SSC_MODFREQ_DPLL_EXP_MASK		GENMASK(10, 8)
+
 struct dpll_params {
 	u32 m;
 	u32 n;
diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h
index 0de1f2a..3a6f6c1 100644
--- a/board/logicpd/omap3som/omap3logic.h
+++ b/board/logicpd/omap3som/omap3logic.h
@@ -45,209 +45,209 @@ const omap3_sysinfo sysinfo = {
  */
 void set_muxconf_regs(void)
 {
-	MUX_VAL(CP(SDRC_D0), (IEN  | PTD | DIS | M0)); /*SDRC_D0*/
-	MUX_VAL(CP(SDRC_D1), (IEN  | PTD | DIS | M0)); /*SDRC_D1*/
-	MUX_VAL(CP(SDRC_D2), (IEN  | PTD | DIS | M0)); /*SDRC_D2*/
-	MUX_VAL(CP(SDRC_D3), (IEN  | PTD | DIS | M0)); /*SDRC_D3*/
-	MUX_VAL(CP(SDRC_D4), (IEN  | PTD | DIS | M0)); /*SDRC_D4*/
-	MUX_VAL(CP(SDRC_D5), (IEN  | PTD | DIS | M0)); /*SDRC_D5*/
-	MUX_VAL(CP(SDRC_D6), (IEN  | PTD | DIS | M0)); /*SDRC_D6*/
-	MUX_VAL(CP(SDRC_D7), (IEN  | PTD | DIS | M0)); /*SDRC_D7*/
-	MUX_VAL(CP(SDRC_D8), (IEN  | PTD | DIS | M0)); /*SDRC_D8*/
-	MUX_VAL(CP(SDRC_D9), (IEN  | PTD | DIS | M0)); /*SDRC_D9*/
-	MUX_VAL(CP(SDRC_D10), (IEN  | PTD | DIS | M0)); /*SDRC_D10*/
-	MUX_VAL(CP(SDRC_D11), (IEN  | PTD | DIS | M0)); /*SDRC_D11*/
-	MUX_VAL(CP(SDRC_D12), (IEN  | PTD | DIS | M0)); /*SDRC_D12*/
-	MUX_VAL(CP(SDRC_D13), (IEN  | PTD | DIS | M0)); /*SDRC_D13*/
-	MUX_VAL(CP(SDRC_D14), (IEN  | PTD | DIS | M0)); /*SDRC_D14*/
-	MUX_VAL(CP(SDRC_D15), (IEN  | PTD | DIS | M0)); /*SDRC_D15*/
-	MUX_VAL(CP(SDRC_D16), (IEN  | PTD | DIS | M0)); /*SDRC_D16*/
-	MUX_VAL(CP(SDRC_D17), (IEN  | PTD | DIS | M0)); /*SDRC_D17*/
-	MUX_VAL(CP(SDRC_D18), (IEN  | PTD | DIS | M0)); /*SDRC_D18*/
-	MUX_VAL(CP(SDRC_D19), (IEN  | PTD | DIS | M0)); /*SDRC_D19*/
-	MUX_VAL(CP(SDRC_D20), (IEN  | PTD | DIS | M0)); /*SDRC_D20*/
-	MUX_VAL(CP(SDRC_D21), (IEN  | PTD | DIS | M0)); /*SDRC_D21*/
-	MUX_VAL(CP(SDRC_D22), (IEN  | PTD | DIS | M0)); /*SDRC_D22*/
-	MUX_VAL(CP(SDRC_D23), (IEN  | PTD | DIS | M0)); /*SDRC_D23*/
-	MUX_VAL(CP(SDRC_D24), (IEN  | PTD | DIS | M0)); /*SDRC_D24*/
-	MUX_VAL(CP(SDRC_D25), (IEN  | PTD | DIS | M0)); /*SDRC_D25*/
-	MUX_VAL(CP(SDRC_D26), (IEN  | PTD | DIS | M0)); /*SDRC_D26*/
-	MUX_VAL(CP(SDRC_D27), (IEN  | PTD | DIS | M0)); /*SDRC_D27*/
-	MUX_VAL(CP(SDRC_D28), (IEN  | PTD | DIS | M0)); /*SDRC_D28*/
-	MUX_VAL(CP(SDRC_D29), (IEN  | PTD | DIS | M0)); /*SDRC_D29*/
-	MUX_VAL(CP(SDRC_D30), (IEN  | PTD | DIS | M0)); /*SDRC_D30*/
-	MUX_VAL(CP(SDRC_D31), (IEN  | PTD | DIS | M0)); /*SDRC_D31*/
-	MUX_VAL(CP(SDRC_CLK), (IEN  | PTD | DIS | M0)); /*SDRC_CLK*/
-	MUX_VAL(CP(SDRC_DQS0), (IEN  | PTD | DIS | M0)); /*SDRC_DQS0*/
-	MUX_VAL(CP(SDRC_DQS1), (IEN  | PTD | DIS | M0)); /*SDRC_DQS1*/
-	MUX_VAL(CP(SDRC_DQS2), (IEN  | PTD | DIS | M0)); /*SDRC_DQS2*/
-	MUX_VAL(CP(SDRC_DQS3), (IEN  | PTD | DIS | M0)); /*SDRC_DQS3*/
-	MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN  | M0)); /*SDRC_CKE0*/
-	MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/
+	MUX_VAL(CP(SDRC_D0), (IEN  | PTD | DIS | M0)) /*SDRC_D0*/
+	MUX_VAL(CP(SDRC_D1), (IEN  | PTD | DIS | M0)) /*SDRC_D1*/
+	MUX_VAL(CP(SDRC_D2), (IEN  | PTD | DIS | M0)) /*SDRC_D2*/
+	MUX_VAL(CP(SDRC_D3), (IEN  | PTD | DIS | M0)) /*SDRC_D3*/
+	MUX_VAL(CP(SDRC_D4), (IEN  | PTD | DIS | M0)) /*SDRC_D4*/
+	MUX_VAL(CP(SDRC_D5), (IEN  | PTD | DIS | M0)) /*SDRC_D5*/
+	MUX_VAL(CP(SDRC_D6), (IEN  | PTD | DIS | M0)) /*SDRC_D6*/
+	MUX_VAL(CP(SDRC_D7), (IEN  | PTD | DIS | M0)) /*SDRC_D7*/
+	MUX_VAL(CP(SDRC_D8), (IEN  | PTD | DIS | M0)) /*SDRC_D8*/
+	MUX_VAL(CP(SDRC_D9), (IEN  | PTD | DIS | M0)) /*SDRC_D9*/
+	MUX_VAL(CP(SDRC_D10), (IEN  | PTD | DIS | M0)) /*SDRC_D10*/
+	MUX_VAL(CP(SDRC_D11), (IEN  | PTD | DIS | M0)) /*SDRC_D11*/
+	MUX_VAL(CP(SDRC_D12), (IEN  | PTD | DIS | M0)) /*SDRC_D12*/
+	MUX_VAL(CP(SDRC_D13), (IEN  | PTD | DIS | M0)) /*SDRC_D13*/
+	MUX_VAL(CP(SDRC_D14), (IEN  | PTD | DIS | M0)) /*SDRC_D14*/
+	MUX_VAL(CP(SDRC_D15), (IEN  | PTD | DIS | M0)) /*SDRC_D15*/
+	MUX_VAL(CP(SDRC_D16), (IEN  | PTD | DIS | M0)) /*SDRC_D16*/
+	MUX_VAL(CP(SDRC_D17), (IEN  | PTD | DIS | M0)) /*SDRC_D17*/
+	MUX_VAL(CP(SDRC_D18), (IEN  | PTD | DIS | M0)) /*SDRC_D18*/
+	MUX_VAL(CP(SDRC_D19), (IEN  | PTD | DIS | M0)) /*SDRC_D19*/
+	MUX_VAL(CP(SDRC_D20), (IEN  | PTD | DIS | M0)) /*SDRC_D20*/
+	MUX_VAL(CP(SDRC_D21), (IEN  | PTD | DIS | M0)) /*SDRC_D21*/
+	MUX_VAL(CP(SDRC_D22), (IEN  | PTD | DIS | M0)) /*SDRC_D22*/
+	MUX_VAL(CP(SDRC_D23), (IEN  | PTD | DIS | M0)) /*SDRC_D23*/
+	MUX_VAL(CP(SDRC_D24), (IEN  | PTD | DIS | M0)) /*SDRC_D24*/
+	MUX_VAL(CP(SDRC_D25), (IEN  | PTD | DIS | M0)) /*SDRC_D25*/
+	MUX_VAL(CP(SDRC_D26), (IEN  | PTD | DIS | M0)) /*SDRC_D26*/
+	MUX_VAL(CP(SDRC_D27), (IEN  | PTD | DIS | M0)) /*SDRC_D27*/
+	MUX_VAL(CP(SDRC_D28), (IEN  | PTD | DIS | M0)) /*SDRC_D28*/
+	MUX_VAL(CP(SDRC_D29), (IEN  | PTD | DIS | M0)) /*SDRC_D29*/
+	MUX_VAL(CP(SDRC_D30), (IEN  | PTD | DIS | M0)) /*SDRC_D30*/
+	MUX_VAL(CP(SDRC_D31), (IEN  | PTD | DIS | M0)) /*SDRC_D31*/
+	MUX_VAL(CP(SDRC_CLK), (IEN  | PTD | DIS | M0)) /*SDRC_CLK*/
+	MUX_VAL(CP(SDRC_DQS0), (IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/
+	MUX_VAL(CP(SDRC_DQS1), (IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/
+	MUX_VAL(CP(SDRC_DQS2), (IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/
+	MUX_VAL(CP(SDRC_DQS3), (IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/
+	MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN  | M0)) /*SDRC_CKE0*/
+	MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /*SDRC_CKE1*/
 
-	MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN  | M0)); /*GPMC_A1*/
-	MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN  | M0)); /*GPMC_A2*/
-	MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN  | M0)); /*GPMC_A3*/
-	MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN  | M0)); /*GPMC_A4*/
-	MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN  | M0)); /*GPMC_A5*/
-	MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN  | M0)); /*GPMC_A6*/
-	MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN  | M0)); /*GPMC_A7*/
-	MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN  | M0)); /*GPMC_A8*/
-	MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN  | M0)); /*GPMC_A9*/
-	MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN  | M0)); /*GPMC_A10*/
-	MUX_VAL(CP(GPMC_D0), (IEN  | PTU | EN  | M0)); /*GPMC_D0*/
-	MUX_VAL(CP(GPMC_D1), (IEN  | PTU | EN  | M0)); /*GPMC_D1*/
-	MUX_VAL(CP(GPMC_D2), (IEN  | PTU | EN  | M0)); /*GPMC_D2*/
-	MUX_VAL(CP(GPMC_D3), (IEN  | PTU | EN  | M0)); /*GPMC_D3*/
-	MUX_VAL(CP(GPMC_D4),  (IEN  | PTU | EN  | M0)); /*GPMC_D4*/
-	MUX_VAL(CP(GPMC_D5),  (IEN  | PTU | EN  | M0)); /*GPMC_D5*/
-	MUX_VAL(CP(GPMC_D6),  (IEN  | PTU | EN  | M0)); /*GPMC_D6*/
-	MUX_VAL(CP(GPMC_D7),   (IEN  | PTU | EN  | M0)); /*GPMC_D7*/
-	MUX_VAL(CP(GPMC_D8),  (IEN  | PTU | EN  | M0)); /*GPMC_D8*/
-	MUX_VAL(CP(GPMC_D9),  (IEN  | PTU | EN  | M0)); /*GPMC_D9*/
-	MUX_VAL(CP(GPMC_D10), (IEN  | PTU | EN  | M0)); /*GPMC_D10*/
-	MUX_VAL(CP(GPMC_D11), (IEN  | PTU | EN  | M0)); /*GPMC_D11*/
-	MUX_VAL(CP(GPMC_D12), (IEN  | PTU | EN  | M0)); /*GPMC_D12*/
-	MUX_VAL(CP(GPMC_D13), (IEN  | PTU | EN  | M0)); /*GPMC_D13*/
-	MUX_VAL(CP(GPMC_D14), (IEN  | PTU | EN  | M0)); /*GPMC_D14*/
-	MUX_VAL(CP(GPMC_D15), (IEN  | PTU | EN  | M0)); /*GPMC_D15*/
-	MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN  | M0)); /*GPMC_nCS0*/
-	MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN  | M0)); /*GPMC_nCS1*/
-	MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN  | M0)); /*GPMC_nCS2*/
-	MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN  | M0)); /*GPMC_nCS3*/
-	MUX_VAL(CP(GPMC_NCS4), (IEN  | PTU | EN  | M0)); /*GPMC_nCS4*/
-	MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN  | M0)); /*GPMC_nCS5*/
-	MUX_VAL(CP(GPMC_NCS6), (IEN  | PTU | EN | M0)); /*GPMC_nCS6*/
-	MUX_VAL(CP(GPMC_NCS7), (IEN  | PTU | EN  | M0)); /*GPMC_nCS7*/
-	MUX_VAL(CP(GPMC_CLK),  (IDIS | PTU | EN  | M0)); /*GPMC_CLK*/
-	MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/
-	MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/
-	MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/
-	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN  | M0)); /*GPMC_nBE0_CLE*/
-	MUX_VAL(CP(GPMC_NBE1), (IEN  | PTU | EN  | M0)); /*GPMC_nBE1*/
-	MUX_VAL(CP(GPMC_NWP),  (IEN  | PTD | DIS | M0)); /*GPMC_nWP*/
-	MUX_VAL(CP(GPMC_WAIT0), (IEN  | PTU | EN  | M0)); /*GPMC_WAIT0*/
-	MUX_VAL(CP(GPMC_WAIT1), (IEN  | PTU | EN  | M0)); /*GPMC_WAIT1*/
-	MUX_VAL(CP(GPMC_WAIT2), (IEN  | PTU | EN  | M4)); /*GPIO_64*/
-	MUX_VAL(CP(GPMC_WAIT3), (IEN  | PTU | EN  | M0)); /*GPMC_WAIT3*/
+	MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN  | M0)) /*GPMC_A1*/
+	MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN  | M0)) /*GPMC_A2*/
+	MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN  | M0)) /*GPMC_A3*/
+	MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN  | M0)) /*GPMC_A4*/
+	MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN  | M0)) /*GPMC_A5*/
+	MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN  | M0)) /*GPMC_A6*/
+	MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN  | M0)) /*GPMC_A7*/
+	MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN  | M0)) /*GPMC_A8*/
+	MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN  | M0)) /*GPMC_A9*/
+	MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN  | M0)) /*GPMC_A10*/
+	MUX_VAL(CP(GPMC_D0), (IEN  | PTU | EN  | M0)) /*GPMC_D0*/
+	MUX_VAL(CP(GPMC_D1), (IEN  | PTU | EN  | M0)) /*GPMC_D1*/
+	MUX_VAL(CP(GPMC_D2), (IEN  | PTU | EN  | M0)) /*GPMC_D2*/
+	MUX_VAL(CP(GPMC_D3), (IEN  | PTU | EN  | M0)) /*GPMC_D3*/
+	MUX_VAL(CP(GPMC_D4), (IEN  | PTU | EN  | M0)) /*GPMC_D4*/
+	MUX_VAL(CP(GPMC_D5), (IEN  | PTU | EN  | M0)) /*GPMC_D5*/
+	MUX_VAL(CP(GPMC_D6), (IEN  | PTU | EN  | M0)) /*GPMC_D6*/
+	MUX_VAL(CP(GPMC_D7), (IEN  | PTU | EN  | M0)) /*GPMC_D7*/
+	MUX_VAL(CP(GPMC_D8), (IEN  | PTU | EN  | M0)) /*GPMC_D8*/
+	MUX_VAL(CP(GPMC_D9), (IEN  | PTU | EN  | M0)) /*GPMC_D9*/
+	MUX_VAL(CP(GPMC_D10), (IEN  | PTU | EN  | M0)) /*GPMC_D10*/
+	MUX_VAL(CP(GPMC_D11), (IEN  | PTU | EN  | M0)) /*GPMC_D11*/
+	MUX_VAL(CP(GPMC_D12), (IEN  | PTU | EN  | M0)) /*GPMC_D12*/
+	MUX_VAL(CP(GPMC_D13), (IEN  | PTU | EN  | M0)) /*GPMC_D13*/
+	MUX_VAL(CP(GPMC_D14), (IEN  | PTU | EN  | M0)) /*GPMC_D14*/
+	MUX_VAL(CP(GPMC_D15), (IEN  | PTU | EN  | M0)) /*GPMC_D15*/
+	MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/
+	MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/
+	MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/
+	MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/
+	MUX_VAL(CP(GPMC_NCS4), (IEN  | PTU | EN  | M0)) /*GPMC_nCS4*/
+	MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/
+	MUX_VAL(CP(GPMC_NCS6), (IEN  | PTU | EN | M0)) /*GPMC_nCS6*/
+	MUX_VAL(CP(GPMC_NCS7), (IEN  | PTU | EN  | M0)) /*GPMC_nCS7*/
+	MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN  | M0)) /*GPMC_CLK*/
+	MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/
+	MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/
+	MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/
+	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN  | M0)) /*GPMC_nBE0_CLE*/
+	MUX_VAL(CP(GPMC_NBE1), (IEN  | PTU | EN  | M0)) /*GPMC_nBE1*/
+	MUX_VAL(CP(GPMC_NWP),  (IEN  | PTD | DIS | M0)) /*GPMC_nWP*/
+	MUX_VAL(CP(GPMC_WAIT0), (IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/
+	MUX_VAL(CP(GPMC_WAIT1), (IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/
+	MUX_VAL(CP(GPMC_WAIT2), (IEN  | PTU | EN  | M4)) /*GPIO_64*/
+	MUX_VAL(CP(GPMC_WAIT3), (IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/
 
-	MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN  | M0)); /*MMC1_CLK*/
-	MUX_VAL(CP(MMC1_CMD), (IEN  | PTU | EN  | M0)); /*MMC1_CMD*/
-	MUX_VAL(CP(MMC1_DAT0), (IEN  | PTU | EN  | M0)); /*MMC1_DAT0*/
-	MUX_VAL(CP(MMC1_DAT1), (IEN  | PTU | EN  | M0)); /*MMC1_DAT1*/
-	MUX_VAL(CP(MMC1_DAT2), (IEN  | PTU | EN  | M0)); /*MMC1_DAT2*/
-	MUX_VAL(CP(MMC1_DAT3), (IEN  | PTU | EN  | M0)); /*MMC1_DAT3*/
+	MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN  | M0)) /*MMC1_CLK*/
+	MUX_VAL(CP(MMC1_CMD), (IEN  | PTU | EN  | M0)) /*MMC1_CMD*/
+	MUX_VAL(CP(MMC1_DAT0), (IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/
+	MUX_VAL(CP(MMC1_DAT1), (IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/
+	MUX_VAL(CP(MMC1_DAT2), (IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/
+	MUX_VAL(CP(MMC1_DAT3), (IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/
 
-	MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/
-	MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/
-	MUX_VAL(CP(UART1_CTS), (IEN  | PTU | DIS | M0)); /*UART1_CTS*/
-	MUX_VAL(CP(UART1_RX), (IEN  | PTD | DIS | M0)); /*UART1_RX*/
+	MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/
+	MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/
+	MUX_VAL(CP(UART1_CTS), (IEN  | PTU | DIS | M0)) /*UART1_CTS*/
+	MUX_VAL(CP(UART1_RX), (IEN  | PTD | DIS | M0)) /*UART1_RX*/
 
-	MUX_VAL(CP(JTAG_TCK), (IEN  | PTD | DIS | M0)); /*JTAG_TCK*/
-	MUX_VAL(CP(JTAG_TMS), (IEN  | PTD | DIS | M0)); /*JTAG_TMS*/
-	MUX_VAL(CP(JTAG_TDI), (IEN  | PTD | DIS | M0)); /*JTAG_TDI*/
-	MUX_VAL(CP(JTAG_EMU0), (IEN  | PTD | DIS | M0)); /*JTAG_EMU0*/
-	MUX_VAL(CP(JTAG_EMU1), (IEN  | PTD | DIS | M0)); /*JTAG_EMU1*/
+	MUX_VAL(CP(JTAG_TCK), (IEN  | PTD | DIS | M0)) /*JTAG_TCK*/
+	MUX_VAL(CP(JTAG_TMS), (IEN  | PTD | DIS | M0)) /*JTAG_TMS*/
+	MUX_VAL(CP(JTAG_TDI), (IEN  | PTD | DIS | M0)) /*JTAG_TDI*/
+	MUX_VAL(CP(JTAG_EMU0), (IEN  | PTD | DIS | M0)) /*JTAG_EMU0*/
+	MUX_VAL(CP(JTAG_EMU1), (IEN  | PTD | DIS | M0)) /*JTAG_EMU1*/
 
-	MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN  | M0)); /*ETK_CLK*/
-	MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/
-	MUX_VAL(CP(ETK_D0_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D0*/
-	MUX_VAL(CP(ETK_D1_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D1*/
-	MUX_VAL(CP(ETK_D2_ES2), (IEN  | PTD | EN  | M0)); /*ETK_D2*/
-	MUX_VAL(CP(ETK_D3_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D3*/
-	MUX_VAL(CP(ETK_D4_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D4*/
-	MUX_VAL(CP(ETK_D5_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D5*/
-	MUX_VAL(CP(ETK_D6_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D6*/
-	MUX_VAL(CP(ETK_D7_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D7*/
-	MUX_VAL(CP(ETK_D8_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D8*/
-	MUX_VAL(CP(ETK_D9_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D9*/
+	MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN  | M0)) /*ETK_CLK*/
+	MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) /*ETK_CTL*/
+	MUX_VAL(CP(ETK_D0_ES2), (IEN  | PTD | DIS | M0)) /*ETK_D0*/
+	MUX_VAL(CP(ETK_D1_ES2), (IEN  | PTD | DIS | M0)) /*ETK_D1*/
+	MUX_VAL(CP(ETK_D2_ES2), (IEN  | PTD | EN  | M0)) /*ETK_D2*/
+	MUX_VAL(CP(ETK_D3_ES2), (IEN  | PTD | DIS | M0)) /*ETK_D3*/
+	MUX_VAL(CP(ETK_D4_ES2), (IEN  | PTD | DIS | M0)) /*ETK_D4*/
+	MUX_VAL(CP(ETK_D5_ES2), (IEN  | PTD | DIS | M0)) /*ETK_D5*/
+	MUX_VAL(CP(ETK_D6_ES2), (IEN  | PTD | DIS | M0)) /*ETK_D6*/
+	MUX_VAL(CP(ETK_D7_ES2), (IEN  | PTD | DIS | M0)) /*ETK_D7*/
+	MUX_VAL(CP(ETK_D8_ES2), (IEN  | PTD | DIS | M0)) /*ETK_D8*/
+	MUX_VAL(CP(ETK_D9_ES2), (IEN  | PTD | DIS | M0)) /*ETK_D9*/
 #ifndef CONFIG_USB_EHCI_OMAP /* Torpedo does not use EHCI_OMAP */
-	MUX_VAL(CP(ETK_D10_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D10*/
-	MUX_VAL(CP(ETK_D11_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D11*/
-	MUX_VAL(CP(ETK_D12_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D12*/
-	MUX_VAL(CP(ETK_D13_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D13*/
-	MUX_VAL(CP(ETK_D14_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D14*/
-	MUX_VAL(CP(ETK_D15_ES2), (IEN  | PTD | DIS | M0)); /*ETK_D15*/
+	MUX_VAL(CP(ETK_D10_ES2), (IEN  | PTD | DIS | M0)) /*ETK_D10*/
+	MUX_VAL(CP(ETK_D11_ES2), (IEN  | PTD | DIS | M0)) /*ETK_D11*/
+	MUX_VAL(CP(ETK_D12_ES2), (IEN  | PTD | DIS | M0)) /*ETK_D12*/
+	MUX_VAL(CP(ETK_D13_ES2), (IEN  | PTD | DIS | M0)) /*ETK_D13*/
+	MUX_VAL(CP(ETK_D14_ES2), (IEN  | PTD | DIS | M0)) /*ETK_D14*/
+	MUX_VAL(CP(ETK_D15_ES2), (IEN  | PTD | DIS | M0)) /*ETK_D15*/
 #endif
 
-	MUX_VAL(CP(D2D_MCAD1), (IEN  | PTD | EN  | M0)); /*d2d_mcad1*/
-	MUX_VAL(CP(D2D_MCAD2), (IEN  | PTD | EN  | M0)); /*d2d_mcad2*/
-	MUX_VAL(CP(D2D_MCAD3), (IEN  | PTD | EN  | M0)); /*d2d_mcad3*/
-	MUX_VAL(CP(D2D_MCAD4), (IEN  | PTD | EN  | M0)); /*d2d_mcad4*/
-	MUX_VAL(CP(D2D_MCAD5), (IEN  | PTD | EN  | M0)); /*d2d_mcad5*/
-	MUX_VAL(CP(D2D_MCAD6), (IEN  | PTD | EN  | M0)); /*d2d_mcad6*/
-	MUX_VAL(CP(D2D_MCAD7), (IEN  | PTD | EN  | M0)); /*d2d_mcad7*/
-	MUX_VAL(CP(D2D_MCAD8), (IEN  | PTD | EN  | M0)); /*d2d_mcad8*/
-	MUX_VAL(CP(D2D_MCAD9), (IEN  | PTD | EN  | M0)); /*d2d_mcad9*/
-	MUX_VAL(CP(D2D_MCAD10), (IEN  | PTD | EN  | M0)); /*d2d_mcad10*/
-	MUX_VAL(CP(D2D_MCAD11), (IEN  | PTD | EN  | M0)); /*d2d_mcad11*/
-	MUX_VAL(CP(D2D_MCAD12), (IEN  | PTD | EN  | M0)); /*d2d_mcad12*/
-	MUX_VAL(CP(D2D_MCAD13), (IEN  | PTD | EN  | M0)); /*d2d_mcad13*/
-	MUX_VAL(CP(D2D_MCAD14), (IEN  | PTD | EN  | M0)); /*d2d_mcad14*/
-	MUX_VAL(CP(D2D_MCAD15), (IEN  | PTD | EN  | M0)); /*d2d_mcad15*/
-	MUX_VAL(CP(D2D_MCAD16), (IEN  | PTD | EN  | M0)); /*d2d_mcad16*/
-	MUX_VAL(CP(D2D_MCAD17), (IEN  | PTD | EN  | M0)); /*d2d_mcad17*/
-	MUX_VAL(CP(D2D_MCAD18), (IEN  | PTD | EN  | M0)); /*d2d_mcad18*/
-	MUX_VAL(CP(D2D_MCAD19), (IEN  | PTD | EN  | M0)); /*d2d_mcad19*/
-	MUX_VAL(CP(D2D_MCAD20), (IEN  | PTD | EN  | M0)); /*d2d_mcad20*/
-	MUX_VAL(CP(D2D_MCAD21), (IEN  | PTD | EN  | M0)); /*d2d_mcad21*/
-	MUX_VAL(CP(D2D_MCAD22), (IEN  | PTD | EN  | M0)); /*d2d_mcad22*/
-	MUX_VAL(CP(D2D_MCAD23), (IEN  | PTD | EN  | M0)); /*d2d_mcad23*/
-	MUX_VAL(CP(D2D_MCAD24), (IEN  | PTD | EN  | M0)); /*d2d_mcad24*/
-	MUX_VAL(CP(D2D_MCAD25), (IEN  | PTD | EN  | M0)); /*d2d_mcad25*/
-	MUX_VAL(CP(D2D_MCAD26), (IEN  | PTD | EN  | M0)); /*d2d_mcad26*/
-	MUX_VAL(CP(D2D_MCAD27), (IEN  | PTD | EN  | M0)); /*d2d_mcad27*/
-	MUX_VAL(CP(D2D_MCAD28), (IEN  | PTD | EN  | M0)); /*d2d_mcad28*/
-	MUX_VAL(CP(D2D_MCAD29), (IEN  | PTD | EN  | M0)); /*d2d_mcad29*/
-	MUX_VAL(CP(D2D_MCAD30), (IEN  | PTD | EN  | M0)); /*d2d_mcad30*/
-	MUX_VAL(CP(D2D_MCAD31), (IEN  | PTD | EN  | M0)); /*d2d_mcad31*/
-	MUX_VAL(CP(D2D_MCAD32), (IEN  | PTD | EN  | M0)); /*d2d_mcad32*/
-	MUX_VAL(CP(D2D_MCAD33), (IEN  | PTD | EN  | M0)); /*d2d_mcad33*/
-	MUX_VAL(CP(D2D_MCAD34), (IEN  | PTD | EN  | M0)); /*d2d_mcad34*/
-	MUX_VAL(CP(D2D_MCAD35), (IEN  | PTD | EN  | M0)); /*d2d_mcad35*/
-	MUX_VAL(CP(D2D_MCAD36), (IEN  | PTD | EN  | M0)); /*d2d_mcad36*/
-	MUX_VAL(CP(D2D_CLK26MI), (IEN  | PTD | DIS | M0)); /*d2d_clk26mi*/
-	MUX_VAL(CP(D2D_NRESPWRON), (IEN  | PTD | EN  | M0)); /*d2d_nrespwron*/
-	MUX_VAL(CP(D2D_NRESWARM), (IEN  | PTU | EN  | M0)); /*d2d_nreswarm */
-	MUX_VAL(CP(D2D_ARM9NIRQ), (IEN  | PTD | DIS | M0)); /*d2d_arm9nirq */
-	MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN  | PTD | DIS | M0)); /*d2d_uma2p6fiq*/
-	MUX_VAL(CP(D2D_SPINT), (IEN  | PTD | EN  | M0)); /*d2d_spint*/
-	MUX_VAL(CP(D2D_FRINT), (IEN  | PTD | EN  | M0)); /*d2d_frint*/
-	MUX_VAL(CP(D2D_DMAREQ0), (IEN  | PTD | DIS | M0)); /*d2d_dmareq0*/
-	MUX_VAL(CP(D2D_DMAREQ1), (IEN  | PTD | DIS | M0)); /*d2d_dmareq1*/
-	MUX_VAL(CP(D2D_DMAREQ2), (IEN  | PTD | DIS | M0)); /*d2d_dmareq2*/
-	MUX_VAL(CP(D2D_DMAREQ3), (IEN  | PTD | DIS | M0)); /*d2d_dmareq3*/
-	MUX_VAL(CP(D2D_N3GTRST), (IEN  | PTD | DIS | M0)); /*d2d_n3gtrst*/
-	MUX_VAL(CP(D2D_N3GTDI),  (IEN  | PTD | DIS | M0)); /*d2d_n3gtdi*/
-	MUX_VAL(CP(D2D_N3GTDO),  (IEN  | PTD | DIS | M0)); /*d2d_n3gtdo*/
-	MUX_VAL(CP(D2D_N3GTMS),  (IEN  | PTD | DIS | M0)); /*d2d_n3gtms*/
-	MUX_VAL(CP(D2D_N3GTCK),  (IEN  | PTD | DIS | M0)); /*d2d_n3gtck*/
-	MUX_VAL(CP(D2D_N3GRTCK), (IEN  | PTD | DIS | M0)); /*d2d_n3grtck*/
-	MUX_VAL(CP(D2D_MSTDBY),  (IEN  | PTU | EN  | M0)); /*d2d_mstdby*/
-	MUX_VAL(CP(D2D_SWAKEUP), (IEN  | PTD | EN  | M0)); /*d2d_swakeup*/
-	MUX_VAL(CP(D2D_IDLEREQ), (IEN  | PTD | DIS | M0)); /*d2d_idlereq*/
-	MUX_VAL(CP(D2D_IDLEACK), (IEN  | PTU | EN  | M0)); /*d2d_idleack*/
-	MUX_VAL(CP(D2D_MWRITE),  (IEN  | PTD | DIS | M0)); /*d2d_mwrite*/
-	MUX_VAL(CP(D2D_SWRITE),  (IEN  | PTD | DIS | M0)); /*d2d_swrite*/
-	MUX_VAL(CP(D2D_MREAD),   (IEN  | PTD | DIS | M0)); /*d2d_mread*/
-	MUX_VAL(CP(D2D_SREAD),   (IEN  | PTD | DIS | M0)); /*d2d_sread*/
-	MUX_VAL(CP(D2D_MBUSFLAG), (IEN  | PTD | DIS | M0)); /*d2d_mbusflag*/
-	MUX_VAL(CP(D2D_SBUSFLAG), (IEN  | PTD | DIS | M0)); /*d2d_sbusflag*/
+	MUX_VAL(CP(D2D_MCAD1), (IEN  | PTD | EN  | M0)) /*d2d_mcad1*/
+	MUX_VAL(CP(D2D_MCAD2), (IEN  | PTD | EN  | M0)) /*d2d_mcad2*/
+	MUX_VAL(CP(D2D_MCAD3), (IEN  | PTD | EN  | M0)) /*d2d_mcad3*/
+	MUX_VAL(CP(D2D_MCAD4), (IEN  | PTD | EN  | M0)) /*d2d_mcad4*/
+	MUX_VAL(CP(D2D_MCAD5), (IEN  | PTD | EN  | M0)) /*d2d_mcad5*/
+	MUX_VAL(CP(D2D_MCAD6), (IEN  | PTD | EN  | M0)) /*d2d_mcad6*/
+	MUX_VAL(CP(D2D_MCAD7), (IEN  | PTD | EN  | M0)) /*d2d_mcad7*/
+	MUX_VAL(CP(D2D_MCAD8), (IEN  | PTD | EN  | M0)) /*d2d_mcad8*/
+	MUX_VAL(CP(D2D_MCAD9), (IEN  | PTD | EN  | M0)) /*d2d_mcad9*/
+	MUX_VAL(CP(D2D_MCAD10), (IEN  | PTD | EN  | M0)) /*d2d_mcad10*/
+	MUX_VAL(CP(D2D_MCAD11), (IEN  | PTD | EN  | M0)) /*d2d_mcad11*/
+	MUX_VAL(CP(D2D_MCAD12), (IEN  | PTD | EN  | M0)) /*d2d_mcad12*/
+	MUX_VAL(CP(D2D_MCAD13), (IEN  | PTD | EN  | M0)) /*d2d_mcad13*/
+	MUX_VAL(CP(D2D_MCAD14), (IEN  | PTD | EN  | M0)) /*d2d_mcad14*/
+	MUX_VAL(CP(D2D_MCAD15), (IEN  | PTD | EN  | M0)) /*d2d_mcad15*/
+	MUX_VAL(CP(D2D_MCAD16), (IEN  | PTD | EN  | M0)) /*d2d_mcad16*/
+	MUX_VAL(CP(D2D_MCAD17), (IEN  | PTD | EN  | M0)) /*d2d_mcad17*/
+	MUX_VAL(CP(D2D_MCAD18), (IEN  | PTD | EN  | M0)) /*d2d_mcad18*/
+	MUX_VAL(CP(D2D_MCAD19), (IEN  | PTD | EN  | M0)) /*d2d_mcad19*/
+	MUX_VAL(CP(D2D_MCAD20), (IEN  | PTD | EN  | M0)) /*d2d_mcad20*/
+	MUX_VAL(CP(D2D_MCAD21), (IEN  | PTD | EN  | M0)) /*d2d_mcad21*/
+	MUX_VAL(CP(D2D_MCAD22), (IEN  | PTD | EN  | M0)) /*d2d_mcad22*/
+	MUX_VAL(CP(D2D_MCAD23), (IEN  | PTD | EN  | M0)) /*d2d_mcad23*/
+	MUX_VAL(CP(D2D_MCAD24), (IEN  | PTD | EN  | M0)) /*d2d_mcad24*/
+	MUX_VAL(CP(D2D_MCAD25), (IEN  | PTD | EN  | M0)) /*d2d_mcad25*/
+	MUX_VAL(CP(D2D_MCAD26), (IEN  | PTD | EN  | M0)) /*d2d_mcad26*/
+	MUX_VAL(CP(D2D_MCAD27), (IEN  | PTD | EN  | M0)) /*d2d_mcad27*/
+	MUX_VAL(CP(D2D_MCAD28), (IEN  | PTD | EN  | M0)) /*d2d_mcad28*/
+	MUX_VAL(CP(D2D_MCAD29), (IEN  | PTD | EN  | M0)) /*d2d_mcad29*/
+	MUX_VAL(CP(D2D_MCAD30), (IEN  | PTD | EN  | M0)) /*d2d_mcad30*/
+	MUX_VAL(CP(D2D_MCAD31), (IEN  | PTD | EN  | M0)) /*d2d_mcad31*/
+	MUX_VAL(CP(D2D_MCAD32), (IEN  | PTD | EN  | M0)) /*d2d_mcad32*/
+	MUX_VAL(CP(D2D_MCAD33), (IEN  | PTD | EN  | M0)) /*d2d_mcad33*/
+	MUX_VAL(CP(D2D_MCAD34), (IEN  | PTD | EN  | M0)) /*d2d_mcad34*/
+	MUX_VAL(CP(D2D_MCAD35), (IEN  | PTD | EN  | M0)) /*d2d_mcad35*/
+	MUX_VAL(CP(D2D_MCAD36), (IEN  | PTD | EN  | M0)) /*d2d_mcad36*/
+	MUX_VAL(CP(D2D_CLK26MI), (IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/
+	MUX_VAL(CP(D2D_NRESPWRON), (IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/
+	MUX_VAL(CP(D2D_NRESWARM), (IEN  | PTU | EN  | M0)) /*d2d_nreswarm */
+	MUX_VAL(CP(D2D_ARM9NIRQ), (IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */
+	MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/
+	MUX_VAL(CP(D2D_SPINT), (IEN  | PTD | EN  | M0)) /*d2d_spint*/
+	MUX_VAL(CP(D2D_FRINT), (IEN  | PTD | EN  | M0)) /*d2d_frint*/
+	MUX_VAL(CP(D2D_DMAREQ0), (IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/
+	MUX_VAL(CP(D2D_DMAREQ1), (IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/
+	MUX_VAL(CP(D2D_DMAREQ2), (IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/
+	MUX_VAL(CP(D2D_DMAREQ3), (IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/
+	MUX_VAL(CP(D2D_N3GTRST), (IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/
+	MUX_VAL(CP(D2D_N3GTDI), (IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/
+	MUX_VAL(CP(D2D_N3GTDO), (IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/
+	MUX_VAL(CP(D2D_N3GTMS), (IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/
+	MUX_VAL(CP(D2D_N3GTCK), (IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/
+	MUX_VAL(CP(D2D_N3GRTCK), (IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/
+	MUX_VAL(CP(D2D_MSTDBY),  (IEN  | PTU | EN  | M0)) /*d2d_mstdby*/
+	MUX_VAL(CP(D2D_SWAKEUP), (IEN  | PTD | EN  | M0)) /*d2d_swakeup*/
+	MUX_VAL(CP(D2D_IDLEREQ), (IEN  | PTD | DIS | M0)) /*d2d_idlereq*/
+	MUX_VAL(CP(D2D_IDLEACK), (IEN  | PTU | EN  | M0)) /*d2d_idleack*/
+	MUX_VAL(CP(D2D_MWRITE), (IEN  | PTD | DIS | M0)) /*d2d_mwrite*/
+	MUX_VAL(CP(D2D_SWRITE), (IEN  | PTD | DIS | M0)) /*d2d_swrite*/
+	MUX_VAL(CP(D2D_MREAD), (IEN  | PTD | DIS | M0)) /*d2d_mread*/
+	MUX_VAL(CP(D2D_SREAD), (IEN  | PTD | DIS | M0)) /*d2d_sread*/
+	MUX_VAL(CP(D2D_MBUSFLAG), (IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/
+	MUX_VAL(CP(D2D_SBUSFLAG), (IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/
 
 #ifdef CONFIG_USB_EHCI_OMAP /* SOM-LV Uses EHCI-OMAP */
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M3));	/*HSUSB2_DATA0*/
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M3));	/*HSUSB2_DATA1*/
-	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0));	/*HSUSB2_DATA2*/
-	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M0));	/*HSUSB2_DATA3*/
-	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0));	/*HSUSB2_DATA4*/
-	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0));	/*HSUSB2_DATA5*/
-	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M0));	/*HSUSB2_DATA6*/
-	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0));	/*HSUSB2_DATA7*/
-	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4))	/* GPIO_4 */
-	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTU | DIS | M3));	/*HSUSB2_CLK*/
-	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M3));	/*HSUSB2_STP*/
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M3));	/*HSUSB2_DIR*/
-	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M3));	/*HSUSB2_NXT*/
+	MUX_VAL(CP(ETK_D14_ES2), (IEN  | PTD | DIS | M3)) /*HSUSB2_DATA0*/
+	MUX_VAL(CP(ETK_D15_ES2), (IEN  | PTD | DIS | M3)) /*HSUSB2_DATA1*/
+	MUX_VAL(CP(MCSPI1_CS3), (IEN  | PTD | EN  | M0)) /*HSUSB2_DATA2*/
+	MUX_VAL(CP(MCSPI2_CS1), (IEN  | PTD | EN  | M0)) /*HSUSB2_DATA3*/
+	MUX_VAL(CP(MCSPI2_SIMO), (IEN  | PTD | DIS | M0)) /*HSUSB2_DATA4*/
+	MUX_VAL(CP(MCSPI2_SOMI), (IEN  | PTD | DIS | M0)) /*HSUSB2_DATA5*/
+	MUX_VAL(CP(MCSPI2_CS0), (IEN  | PTD | EN  | M0)) /*HSUSB2_DATA6*/
+	MUX_VAL(CP(MCSPI2_CLK), (IEN  | PTD | DIS | M0)) /*HSUSB2_DATA7*/
+	MUX_VAL(CP(SYS_BOOT2),	(IEN  | PTD | DIS | M4)) /* GPIO_4 */
+	MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/
+	MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/
+	MUX_VAL(CP(ETK_D12_ES2), (IEN  | PTU | DIS | M3)) /*HSUSB2_DIR*/
+	MUX_VAL(CP(ETK_D13_ES2), (IEN  | PTD | DIS | M3)) /*HSUSB2_NXT*/
 #endif
 
 }
diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig
index 72ee5c8..84e387a 100644
--- a/configs/iot2050_defconfig
+++ b/configs/iot2050_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_ARCH_K3=y
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -10,15 +11,16 @@ CONFIG_TARGET_IOT2050_A53=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x680000
 CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic"
 CONFIG_SPL_TEXT_BASE=0x80080000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_ENV_OFFSET_REDUND=0x6a0000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
 CONFIG_DISTRO_DEFAULTS=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index 9d8ac94..db38d78 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL_TEXT_BASE=0x40200000
 CONFIG_TARGET_OMAP3_LOGIC=y
 # CONFIG_SPL_OMAP3_ID_NAND is not set
 CONFIG_SPL=y
+CONFIG_LTO=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_ANDROID_BOOT_IMAGE=y
 # CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index ee0c58a..9abfe95 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL_TEXT_BASE=0x40200000
 CONFIG_TARGET_OMAP3_LOGIC=y
 # CONFIG_SPL_OMAP3_ID_NAND is not set
 CONFIG_SPL=y
+CONFIG_LTO=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_ANDROID_BOOT_IMAGE=y
 # CONFIG_USE_BOOTCOMMAND is not set
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index ece92fe..fb1ee3a 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL_TEXT_BASE=0x40200000
 CONFIG_TARGET_OMAP3_LOGIC=y
 # CONFIG_SPL_OMAP3_ID_NAND is not set
 CONFIG_SPL=y
+CONFIG_LTO=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_ANDROID_BOOT_IMAGE=y
 # CONFIG_USE_BOOTCOMMAND is not set
diff --git a/drivers/clk/ti/clk-am3-dpll.c b/drivers/clk/ti/clk-am3-dpll.c
index 916d308..398a011 100644
--- a/drivers/clk/ti/clk-am3-dpll.c
+++ b/drivers/clk/ti/clk-am3-dpll.c
@@ -27,11 +27,17 @@ struct clk_ti_am3_dpll_priv {
 	struct clk_ti_reg clkmode_reg;
 	struct clk_ti_reg idlest_reg;
 	struct clk_ti_reg clksel_reg;
+	struct clk_ti_reg ssc_deltam_reg;
+	struct clk_ti_reg ssc_modfreq_reg;
 	struct clk clk_bypass;
 	struct clk clk_ref;
 	u16 last_rounded_mult;
 	u8 last_rounded_div;
+	u8 min_div;
 	ulong max_rate;
+	u32 ssc_modfreq;
+	u32 ssc_deltam;
+	bool ssc_downspread;
 };
 
 static ulong clk_ti_am3_dpll_round_rate(struct clk *clk, ulong rate)
@@ -51,7 +57,7 @@ static ulong clk_ti_am3_dpll_round_rate(struct clk *clk, ulong rate)
 	err = rate;
 	err_min = rate;
 	ref_rate = clk_get_rate(&priv->clk_ref);
-	for (d = 1; err_min && d <= 128; d++) {
+	for (d = priv->min_div; err_min && d <= 128; d++) {
 		for (m = 2; m <= 2047; m++) {
 			r = (ref_rate * m) / d;
 			err = abs(r - rate);
@@ -71,8 +77,8 @@ static ulong clk_ti_am3_dpll_round_rate(struct clk *clk, ulong rate)
 
 	priv->last_rounded_mult = mult;
 	priv->last_rounded_div = div;
-	dev_dbg(clk->dev, "rate=%ld, best_rate=%ld, mult=%d, div=%d\n", rate,
-		ret, mult, div);
+	dev_dbg(clk->dev, "rate=%ld, min-div: %d, best_rate=%ld, mult=%d, div=%d\n",
+		rate, priv->min_div, ret, mult, div);
 	return ret;
 }
 
@@ -107,6 +113,96 @@ static int clk_ti_am3_dpll_state(struct clk *clk, u8 state)
 	return 0;
 }
 
+/**
+ * clk_ti_am3_dpll_ssc_program - set spread-spectrum clocking registers
+ * @clk:	struct clk * of DPLL to set
+ *
+ * Enable the DPLL spread spectrum clocking if frequency modulation and
+ * frequency spreading have been set, otherwise disable it.
+ */
+static void clk_ti_am3_dpll_ssc_program(struct clk *clk)
+{
+	struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
+	unsigned long ref_rate;
+	u32 v, ctrl, mod_freq_divider, exponent, mantissa;
+	u32 deltam_step, deltam_ceil;
+
+	ctrl = clk_ti_readl(&priv->clkmode_reg);
+
+	if (priv->ssc_modfreq && priv->ssc_deltam) {
+		ctrl |= CM_CLKMODE_DPLL_SSC_EN_MASK;
+
+		if (priv->ssc_downspread)
+			ctrl |= CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
+		else
+			ctrl &= ~CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
+
+		ref_rate = clk_get_rate(&priv->clk_ref);
+		mod_freq_divider =
+		    (ref_rate / priv->last_rounded_div) / (4 * priv->ssc_modfreq);
+		if (priv->ssc_modfreq > (ref_rate / 70))
+			dev_warn(clk->dev,
+				 "clock: SSC modulation frequency of DPLL %s greater than %ld\n",
+				 clk->dev->name, ref_rate / 70);
+
+		exponent = 0;
+		mantissa = mod_freq_divider;
+		while ((mantissa > 127) && (exponent < 7)) {
+			exponent++;
+			mantissa /= 2;
+		}
+		if (mantissa > 127)
+			mantissa = 127;
+
+		v = clk_ti_readl(&priv->ssc_modfreq_reg);
+		v &= ~(CM_SSC_MODFREQ_DPLL_MANT_MASK | CM_SSC_MODFREQ_DPLL_EXP_MASK);
+		v |= mantissa << __ffs(CM_SSC_MODFREQ_DPLL_MANT_MASK);
+		v |= exponent << __ffs(CM_SSC_MODFREQ_DPLL_EXP_MASK);
+		clk_ti_writel(v, &priv->ssc_modfreq_reg);
+		dev_dbg(clk->dev,
+			"mod_freq_divider: %u, exponent: %u, mantissa: %u, modfreq_reg: 0x%x\n",
+			mod_freq_divider, exponent, mantissa, v);
+
+		deltam_step = priv->last_rounded_mult * priv->ssc_deltam;
+		deltam_step /= 10;
+		if (priv->ssc_downspread)
+			deltam_step /= 2;
+
+		deltam_step <<= __ffs(CM_SSC_DELTAM_DPLL_INT_MASK);
+		deltam_step /= 100;
+		deltam_step /= mod_freq_divider;
+		if (deltam_step > 0xFFFFF)
+			deltam_step = 0xFFFFF;
+
+		deltam_ceil = (deltam_step & CM_SSC_DELTAM_DPLL_INT_MASK) >>
+			__ffs(CM_SSC_DELTAM_DPLL_INT_MASK);
+		if (deltam_step & CM_SSC_DELTAM_DPLL_FRAC_MASK)
+			deltam_ceil++;
+
+		if ((priv->ssc_downspread &&
+		     ((priv->last_rounded_mult - (2 * deltam_ceil)) < 20 ||
+		      priv->last_rounded_mult > 2045)) ||
+		    ((priv->last_rounded_mult - deltam_ceil) < 20 ||
+		     (priv->last_rounded_mult + deltam_ceil) > 2045))
+			dev_warn(clk->dev,
+				 "clock: SSC multiplier of DPLL %s is out of range\n",
+				 clk->dev->name);
+
+		v = clk_ti_readl(&priv->ssc_deltam_reg);
+		v &= ~(CM_SSC_DELTAM_DPLL_INT_MASK | CM_SSC_DELTAM_DPLL_FRAC_MASK);
+		v |= deltam_step << __ffs(CM_SSC_DELTAM_DPLL_INT_MASK |
+					  CM_SSC_DELTAM_DPLL_FRAC_MASK);
+		clk_ti_writel(v, &priv->ssc_deltam_reg);
+		dev_dbg(clk->dev,
+			"deltam_step: %u, deltam_ceil: %u, deltam_reg: 0x%x\n",
+			deltam_step, deltam_ceil, v);
+	} else {
+		ctrl &= ~CM_CLKMODE_DPLL_SSC_EN_MASK;
+	}
+
+	clk_ti_writel(ctrl, &priv->clkmode_reg);
+}
+
 static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
 {
 	struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
@@ -136,6 +232,8 @@ static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
 
 	clk_ti_writel(v, &priv->clksel_reg);
 
+	clk_ti_am3_dpll_ssc_program(clk);
+
 	/* lock dpll */
 	clk_ti_am3_dpll_clken(priv, DPLL_EN_LOCK);
 
@@ -229,6 +327,7 @@ static int clk_ti_am3_dpll_of_to_plat(struct udevice *dev)
 	struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
 	struct clk_ti_am3_dpll_drv_data *data =
 		(struct clk_ti_am3_dpll_drv_data *)dev_get_driver_data(dev);
+	u32 min_div;
 	int err;
 
 	priv->max_rate = data->max_rate;
@@ -251,6 +350,32 @@ static int clk_ti_am3_dpll_of_to_plat(struct udevice *dev)
 		return err;
 	}
 
+	err = clk_ti_get_reg_addr(dev, 3, &priv->ssc_deltam_reg);
+	if (err) {
+		dev_err(dev, "failed to get SSC deltam register\n");
+		return err;
+	}
+
+	err = clk_ti_get_reg_addr(dev, 4, &priv->ssc_modfreq_reg);
+	if (err) {
+		dev_err(dev, "failed to get SSC modfreq register\n");
+		return err;
+	}
+
+	if (dev_read_u32(dev, "ti,ssc-modfreq-hz", &priv->ssc_modfreq))
+		priv->ssc_modfreq = 0;
+
+	if (dev_read_u32(dev, "ti,ssc-deltam", &priv->ssc_deltam))
+		priv->ssc_deltam = 0;
+
+	priv->ssc_downspread = dev_read_bool(dev, "ti,ssc-downspread");
+
+	if (dev_read_u32(dev, "ti,min-div", &min_div) || min_div == 0 ||
+	    min_div > 128)
+		priv->min_div = 1;
+	else
+		priv->min_div = min_div;
+
 	return 0;
 }
 
diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h
index ddb4cfc..91ed76b 100644
--- a/include/configs/iot2050.h
+++ b/include/configs/iot2050.h
@@ -17,8 +17,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SPL_TEXT_BASE + \
 					 CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
 
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
 #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
 
 #define CONFIG_SYS_BOOTM_LEN		SZ_64M